CMOS ANALOG IC DESIGN

QUESTION BANK
M.TECH
(I YEAR – I SEM)
(2023-24)

Department of Electronics and Communication Engineering

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)
Recognized under 2(f) and 12 (B) of UGC ACT 1956
(Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO 9001:2015 Certified)
Maisammaguda, Dhulapally (Post Via. Kompally), Secunderabad – 500100, Telangana State, India
 R22
Code No: R22D6803
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
M.Tech I Year I Semester Supplementary Examinations, August 2023
CMOS Analog IC Design
(VLSI&ES)
Roll No

Time: 3 hours Max. Marks: 60

Note: This question paper contains two parts A and B
Part A is compulsory which carries 10 marks and Answer all questions.
Part B Consists of 5 SECTIONS (One SECTION for each UNIT). Answer FIVE Questions,
Choosing ONE Question from each SECTION and each Question carries 10 marks.
****
PART-A (10 MARKS)
(Write all answers of this PART at one place)
1 A Define threshold voltage? Give the expression for it? [1M]
B Draw the small signal model for NMOS MOSFET with all considerations [1M]
C Draw the circuit diagram for Wilson current mirror? [1M]
D What is the value of output resistance when MOSFET is in degeneration? [1M]
E What is Current amplifier? [1M]
F Draw the single ended differential amplifier circuit diagram? [1M]
G List out the op-amp operation parameters. [1M]
H Explain about OTA? [1M]
I Sketch the transfer characteristic and model for comparator with finite [1M]
gain?
J Differentiate the Two-stage comparator and Discrete time Comparator [1M]
PART-B( 50 MARKS)
SECTION-I
2 A Derive the I-V relationship of the MOSFET in all the possible regions. [6M]
B Suggest a region of operation for the same if one wants to design a switch [4M]
OR
3 A Explain about subthreshold conduction? [5M]
B Discuss the various short channel effects in MOS devices [5M]
SECTION-II
4 A Draw and explain about simple current mirror with beat helper. [5M]
B Explain about cascode current mirrors. [5M]
OR
5 A Discuss about the charge injection errors in MOS switch. [5M]
B Draw the circuit diagram of High swing cascode current mirror circuit? [5M]
SECTION-III
6 A Derive the voltage gain for telescopic op amp? [5M]
B Discuss the principle of current feedback op amp [5M]
OR
7 A Discuss the disadvantages of cascode amplifier under low voltage condition [5M]
Page 1 of 2
 and hence discuss the folded cascode structure to address the same
B Explain the various architectures of high gain amplifiers. [5M]
SECTION-IV
8 A Explain about PSRS of two stage op amp [5M]
B Explain what is meant by dominant pole compensation in operational [5M]
amplifiers
OR
9 Explain about single and two stage op amp with neat circuit diagrams [10M]
SECTION-V
10 A Explain the auto zeroing concept of improving the performance of a [5M]
comparator.
B Discuss the dynamic characteristics of a Comparator? [5M]
OR
11 A Give the principle of comparators and characterize the same? [5M]
B Explain about Switched capacitor comparators? [5M]
***

Page 2 of 2
Code No: R20D6803 R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
M.Tech I Year I Semester Supplementary Examinations, August 2023
CMOS Analog IC Design
(VLSI&ES)
Roll No

Time: 3 hours Max. Marks:

70
Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
1 A Design the Physical structure of an n-channel and a p-channel [7M]
transistor in a p-well technology.
B Define the threshold voltages in MOS transistor and derive the [7M]
threshold voltage equation.
OR
2 A Define latch up and explaintwo prevention methods. What are the [7M]
advantages of latch up?
B Design the small-signal model for the MOS transistor. [7M]
SECTION-II
3 A Illustrate the hierarchy of analog circuits for the operational amplifier. [7M]
B Derive the active resistor equation rdsfor the MOS diode resistor. [7M]
OR
4 A Design current sinks and source characteristics. [7M]
B Draw the I-V characteristics of ideal current and voltage references. [7M]
SECTION-III
5 A Compare Active PMOS load inverter and Current source load [7M]
inverter.
B Design the noise calculations in a current-source load inverter. [7M]
OR
6 A Design the CMOS differential amplifier using a current-mirror load. [7M]
B Calculate the minimum output voltage for the simple Cascode [7M]
Amplifier.
SECTION-IV
7 A Design of CMOS Op-Amps and simplified inverting voltage amplifier [7M]
using an op-amp.
B Give the design procedure for the Two-stage CMOS op-amp. [7M]
OR
8 Design the power-supply rejection ratio of two-stage op amps. [14M]
SECTION-V
9 A Design the two-stage, open-loop comparators and its performances. [7M]
B Design the clamped push-pull output comparators. [7M]
OR
10 Calculate the Propagation delay time of a two-stage open-loop [14M]
comparator.

Page 1 of 1
Code No: R18D6808
R18
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
M.Tech I Year I Semester Supplementary Examinations, August 2023
CMOS Analog Integrated Circuit Design
(VLSI&ES)
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
1 A Explain the operation of a MOS transistor and derive the mathematical [7M]
model (drain current equation) in all operating regions
B Determine the operating region and of each of the following MOSFETs. [7M]
Assume
W/L=10µm/0.5 µm. lambda=0, gamma=0

OR
2 A What are the different capacitor components compatible with [7M]
fabrication steps used to build MOS device. Mention the range of values
and matching accuracy.
B Draw the small signal model of a MOSFET and derive the small signal [7M]
parameters
SECTION-II
3 A Derive (using small signal analysis) the on-channel resistance of a [7M]
(i) Diode connected MOSFET in saturation region
(ii) MOSFET in linear region
B With neat sketches, compare basic current sink and cascode current sink [7M]
in terms of voltage overhead and output resistance.
OR
4 A Design a basic NMOS current mirror for a output current of 0.75mA [7M]
from a reference current of 0.5mA and a voltage overhead of 0.3V.
Assume
B What is an ideal voltage/current reference and mention their [7M]
performance characteristics? Describe the general principle of a
bandgap reference circuit
SECTION-III
5 A Draw the circuit diagram of an current source load interver, plot the [7M]
voltage transfer function and derive its small signal voltage gain
Page 1 of 2
 B Give a neat sketch of CMOS differential amplifier with active current [7M]
mirror load and derive the voltage gain, slew rate and voltage transfer
curve
OR
6 A What are the advantages of cascading?? Provide a circuit [7M]
implementation of a cascode amplifier (with current mirror biasing) and
derive its voltage gain
B Write short notes on high gain amplifier architectures [7M]
SECTION-IV
7 A What is the need for frequency compensation in an opamp? Describe [7M]
the miller compensation of a two stage op-amp
B Design a two-stage opamp for the below specifications [7M]
Av=3000V/V, Vdd=2.5V, Vss = -2.5V, GB=10MHz, CL=10pF, SR >
20V/uS, Vout,range=+-2V, ICMR=-1V to 2V, Pdiss=2mW. Assume
appropriate material and device parameters
OR
8 A Provide a neat sketch of nMOS input PMOS cascode folded cascode [7M]
opamp and derive the output voltage swing, output resistance and small
signal voltage gain
B Write short notes on measurement/simulation of gain, bandwidth, [7M]
CMRR and PSRR of an opamp
SECTION-V
9 A Describe the model of a comparator with finite gain. Define the static [7M]
and dynamic characteristics of a comparator
B With a neat sketch, describe the methods to increase the capacitive drive [7M]
of a tw-stage open loop comparator
OR
10 A Draw a neat sketch of two-stage open loop comparator and derive its [7M]
VOH, small signal gain, frequency response and slew rate
B What is the need for comparator with hysteresis? Provide a neat sketch [7M]
of comparator with hysteresis and plot input/output waveforms with and
without hysteresis

Page 2 of 2
Code No: R20D6803
R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year I Semester Supplementary Examinations, November 2022

CMOS Analog IC Design

(VLSI&ES)

Roll No

Time: 3 hours Max. Marks: 70

Answer Any Five Questions

All Questions carries equal marks.

***

1 A Discuss the Passive Components of the MOS transistor? [7M]

B Explain sub threshold MOS model? [7M]

2 A Explain the CMOS device Modelling? [7M]

B Draw the small-signal model for the MOS transistor. Briefly explain each [7M]
component in that?

3 A Explain the given simplest forms of the current mirror, the MOS version of [7M]
the current mirror?
B Explain the Bipolar simple current mirror with degeneration helper with [7M]
necessary equations?

4 What is the Current Mirror? Explain the general properties of current mirrors [14M]
with a block Diagram?

5 A Design a CMOS current mirror load differential amplifier? [7M]

B Explain the slew rate and noise for a p-channel differential amplifier with [7M]
necessary equations?

6 A Explain about cascade amplifier? [7M]

B Explain about the design of CMOS opamps? [7M]

7 A Explain about the Cascode Op-amps? [7M]

Page 1 of 21
 B Explain the design of Two-stage op-amps? [7M]

8 A Compare the dynamic latch with the NMOS and PMOS latches. What are [7M]
the advantages and disadvantages of the two latches?
B Explain the different types of Open-loop comparator? [7M]

Page 2 of 21
Code No: R20D6803 R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year I Semester Regular/Supplementary Examinations, June 2022

CMOS Analog IC Design

(VLSI&ES)

Roll No

Time: 3 hours Max. Marks: 70

Answer Any Five Questions

All Questions carries equal marks.

***

1 A Explain the Large-signal model for the MOS Transistor? [7M]

B Explain about computer simulation model? [7M]

2 A Draw the small-signal model for the MOS transistor. Briefly explain [7M]
each component in that?
B Choose values of VGS = 1,2,3,4 and 5V, assume that the channel [7M]
modulation parameter is zero. Sketch to scale the output characteristics
of an enhancement n-channel device if VT = 0.7V and ID = 500μA when
VGS = 5 Vin saturation.

3 A Explain the simplest forms of the current mirror and the Bipolar version of [7M]
the current mirror?

B Explain in detail the MOS cascode current mirror with necessary equations? [7M]

4 A Explain the difference between cascade current mirror and Wilson current [7M]
mirror?

B Write a short notes on current sinks and sources? [7M]

Page 3 of 21
5 A Briefly explain the differential amplifiers. With necessary equation give the [7M]
large-signal analysis of CMOS differential amplifiers?

B Derive the expression for power-supply rejection ratio of Two-stage op- [7M]
amps?

6 A Explain about current amplifier? [7M]

B Explain the concept of push-pull inverter with a neat diagram. Derive the [7M]
small signal voltage gain and find the zero in plane?

7 A Explain about the design of Two-stage op-amps? [7M]

B Explain the compensation of Op-amps? [7M]

8 A Differentiate the Two-stage comparator and Discrete-time Comparator? [7M]

B With neat sketch and necessary equations explain the Design aspect of a [7M]
two stage open loop comparator for slewing response?

*****

Page 4 of 21
Code No: R18D6808

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year I Semester Supplementary Examinations, November 2022

CMOS Analog Integrated Circuit Design

(VLSI&ES)

Roll No

Time: 3 hours Max. Marks: 70

Answer Any Five Questions

All Questions carries equal marks.

***

1 Explain about the computer simulation models. [14M]

2 Explain the Large-signal model for the MOS Transistor. [14M]

3 Discuss about current sinks and sources. [14M]

4 Explain the difference between cascade current mirror and Wilson current mirror. [14M]

5 Explain about the current amplifier. [14M]

6 Explain about the output amplifier. [14M]

Page 5 of 21
7 Explain about the design of CMOS op-amps. [14M]

8 How to improve the performance of Open loop comparator. [14M]

**********

Page 6 of 21
Code No: R20D6803 R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year I Semester Regular Examinations, July 2021

CMOS Analog IC Design

(VLSI&ES)

Roll No

Time: 3 hours Max. Marks: 70

Answer Any Five Questions

All Questions carries equal marks.

***

1 Find the Threshold voltage and Body factor of an n-channel [14M]

transistor with an n+ silicon gate if tox = 200 oA, NA= 3 X 1016

cm-3, gate doping ND = 4 X 1019 cm-3, and if the number of

positively charged ions at Gate-Silicon interface per area is 1010

cm-2.

2 Interpret the simple MOS large signal model using mathematical [14M]

models.

3 Model the Voltage reference circuits using voltage division of [14M]

Resistor and Active device implementation.

4 What is current mirror circuit and discusses its operation using [14M]

various blocks

Page 7 of 21
5 What is Active load inverter? Develop small signal model for the Active [14M]

load inverter.

6 Develop CMOS differential Amplifier and obtain the Differential [14M]

transconductance of the amplifier.

7 Draw the block diagram of a general two stage Op-Amp and explain the [14M]

functionality each block.

8 Identify model of an Ideal comparator, comparator with finite gain and [14M]

comparator with input-offset voltage.

**********

Page 8 of 21
 Code No: R20D6803

MALLA REDDY COLLEGE OF ENGINEERING &

TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year I Semester Supplementary Examinations, December 2021

CMOS Analog IC Design

(VLSI&ES)

Roll No

Time: 3 hours
Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE

Questions, Choosing ONE Question from each SECTION and each
Question carries 14 marks.

***

SECTION-I

1 Develop the small signal model of MOS [14M]

transistor and derive the equation for its
transconductance.
OR

2 For an n-channel MOSFET with an n+ silicon [14M]

gate if tox = 200 oA, NA= 3 X 1015 cm-3, gate
doping ND = 4 X 1018 cm-3, and if the number of
positively charged ions at Gate-Silicon interface
per area is 1010 cm-2. Find the Vt and γ of the
transistor.
SECTION-II

3 What is Standard Cascode current circuit and [14M]

discusses its operation using output
characteristics.
OR

Page 9 of 21
4 What happens when Gate and Drain of MOS [14M]
transistor are tied together? Show its I-V
characteristics and its small signal model.
SECTION-III

5 Identify the circuit models for Active load, [14M]

current source and Push-pull inverters.
OR

6 Develop CMOS differential Amplifier using [14M]

current mirror load and obtain the Differential
transconductance of the amplifier.
SECTION-IV

7 List the design procedure parameters of two [14M]

stage CMOS Op-Amp.
OR

8 Derive the method for calculating Power-Supply [14M]

Rejection Ratio and its model.
SECTION-V

9 Build the circuit model and frequency response [14M]

of two stage comparator.
OR

10 Find the propagation delay time of open-loop [14M]

comparator that has a dominant pole at 103 rad/s,
DC gain of 104, slew rate 1 V/μs, and a binary
output voltage swing of 1 V for an applied input
voltage 10 mV.
**********

Page 10 of 21
Code No: R18D6808 R18
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year I Semester Supplementary Examinations, December 2021

CMOS Analog Integrated Circuit Design

(VLSI&ES)

Roll No

Time: 3 hours Max. Marks:

70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing
ONE Question from each SECTION and each Question carries 14 marks.

***

SECTION-I

1 a).Discuss about the Passive Components of the MOS transistor. [7M]

b).Explain about the computer simulation models. [7M]

OR

2 a).Compare NMOS and CMOS technologies with an example. [7M]

b).Explain sub threshold MOS model. [7M]

SECTION-II

3 a).Write a short note on current sinks and sources. [7M]

b).Explain the difference between cascade current mirror and
[7M]
Wilson current mirror.
OR

4 a).Explain in details the MOS cascode current mirror with [7M]

necessary equations.
[7M]
b).Illustrate the Bipolar version of current mirror with necessary
equations.
SECTION-III

5 a).Explain the concept of push-pull inverter with neat diagram. [7M]

Page 11 of 21
 b).Derive the small signal voltage gain and find the zero in plane. [7M]

OR

6 a).Name the different output amplifiers and explain any one in [7M]
detailed.
[7M]
b).Illustrate the Architectures of High Gain Amplifiers.

SECTION-IV

7 a).Explain about the design of Two-stage op-amps. [7M]

b).Demonstrate the Cascode Op-amps. [7M]

OR

8 a).Derive the expression for power-supply rejection ratio of Two- [7M]

stage op-amps.
[7M]
b).Write a short note on design aspects of Op-Amp.

SECTION-V

9 a).Explain about the different types of Open loop comparator [7M]

b).Discuss various types of open loop comparators [7M]

OR

10 Elaborate the Performance improvement of Open-Loop [14M]

Comparators.

**********

Page 12 of 21
Code No: R18D6808 R18
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year I Semester Supplementary Examinations, February/March

2021

CMOS Analog Integrated Circuit Design

(VLSI&ES)

Roll No

Time: 2 hours 30 min Max. Marks:

70

Answer Any Five Questions

All Questions carries equal marks.

****

1 a).Draw the small-signal model for the MOS transistor. Briefly [7M]
explain each component in that. [7M]

b). Explain about the CMOS device Modelling.

2 a).Choose values of VGS = 1,2,3,4 and 5V, assume that the channel [7M]
modulation parameter is zero. Sketch to scale the output
characteristics of an enhancement n-channel device if VT = 0.7V and
ID = 500µA when VGS = 5Vin saturation.
[7M]
b).Explain the Large-signal model for the MOS Transistor.

3 a).What is Current sink .Explain the general properties of [7M]

current sink with block diagram?
b).Explain in detailed about MOS switch and MOS Diode.
[7M]

4 a).Write a short note on MOS switch model. [7M]

b).Explain about the Bipolar simple current mirror with
degeneration helper with necessary equations.
[7M]

Page 13 of 21
5 a).Briefly explain the differential amplifiers. With necessary [7M]
equation give the large signal analysis of CMOS differential
amplifiers.
[7M]
b).Design a CMOS current mirror load differential amplifier.
6 Explain about a) Current Amplifier b) Cascode Amplifier. [14M]

7 With neat sketch explain the following [7M]

a) Characteristics of Op-Amp b) Classification of Op-Amp [7M]

8 Explain the following terms with neat sketch. [7M]

a) Switched capacitor comparators b) Regenerative comparators. [7M]

**********

Page 14 of 21
Code No: R18D6808 R18
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year - I Semester Regular/Supplementary Examinations,

January-2020
CMOS Analog Integrated Circuit Design

(VLSI&ES)

Roll No

Time: 3 hours Max. Marks:

70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing
ONE Question from each SECTION and each Question carries 14 marks.

***

SECTION-I

1 Analyze the Simple MOS Small-Signal Model with the associated [14M]
parameters in detail.
OR

2 a) Illustrate the formation of MOS transistor using n-well [7M]

technology and threshold voltage.
b) Describe the importance of Sub-threshold MOS Model
with relevant diagram
[7M]

SECTION-II

3 a) Draw the model for a non ideal switch and explain its [6M]
parameters in detail
b) Draw and explain about a simple current mirror with Beta [8M]
helper.
OR

4 a) Describe the concept of increasing the output resistance in [7M]

current sink and the factor by which it is increased?
b) Differentiate between Wilson current mirror and cascode
Wilson current mirror
[7M]]

Page 15 of 21
 SECTION-III

5 Illustrate the design of Cascode Amplifiers. [14M]

OR

6 Design a CMOS differential amplifier with current mirror load [14M]

SECTION-IV

7 a) With a schematic explain about operational-amplifier with its [4M]

equivalent circuit

b) Define and explain the following terms

[10M]
i) Common-Mode Input Range

ii) Common-Mode Rejection Ratio

OR

8 a) Briefly explain the Miller compensating networks in op-Amps. [7M]

b) Design the two stage CMOS op-amp to meet the important [7M]
specifications

SECTION-V

9 Describe the following [7M]

(a) Auto zeroing technique (b) Comparator using hysteresis [7M]

OR

10 a) Discuss the Characterization of Comparator [7M]

b) Explain the types of discrete time Comparator.
[7M]

**********

Page 16 of 21
Code No: : R17D6805
R17

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)

M.Tech I-Year - I Semester Supplementary Examinations, Dec-18/Jan-19

CMOS Analog Integrated Circuit Design
(VLSI&ES)

Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE Question from
each SECTION and each Question carries 14 marks.

*****

Blooms
Marks CO
Level
SECTION-I
Q.1. a) Draw the physical structure of n channel and p channel MOS transistor [7M] CO1 2
using well technology and highlight the importance points?
b) Explain the importance of BSIM3 model addresses threshold voltage [7M] CO1 2
reduction
OR
Q.2. a) Explain the small signal model for the MOS transistor [7M] CO2 2

b) Explain about CMOS device model? [7M]

SECTION-II
Q.3. a) Explain the the feedback through effects by using a dummy transistor? [7M] CO3 2

b) Draw the circuit diagram of standard cascode current sink and how its
reduces the errors in V or I [7M]
OR
Q.4. a) What do you mean by band gap reference and list the principle involved? [7M] CO2 4
b) Explain 2 Input NOR gate with depletion NMOS loads. Calculate
output high
voltage and output low voltage? [7M]
SECTION-III
Q.5. a) Draw the circuit diagram of output amplifier using push pull inverting CO3 2
amplifier and comment on [7M]

Page 17 of 21
 it?

b) Explain the noise model of a p channel differential amplifier ? [7M] CO3 2

OR
Q.6. a) Explain the design relationships for the differential amplifier? [7M] CO3 2
b) Draw the circuit diagram of differential mode and common mode CO3 3
circuits using CMOS and
explain? [7M]
SECTION-IV
Q.7. What is compensation of Op-amp? Explain the operation of Miller CO4 4
compensation [14M]
OR
Q.8. a) Explain the design procedure for the 2 stage CMOS opamp? [7M] [7M] CO4 3

b) Explain folded cascode op amp? [7M] [7M]

SECTION-V
Q.9. a) Explain regenerative comparators? [7M] [7M] CO5 4

b) Draw the switched capacitor comparator and highlight four important

points [7M]
OR
Q.10. a) How to improve the performance of an open loop high gain [7M] CO5 5
comparator by auto zeroing?

b) Explain clamped push pull output comparator [7M]

Page 18 of 21
Code No: R18D6808

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY R18

(Autonomous Institution – UGC, Govt. of India)

M.Tech I Year I Semester Supplementary Examinations, October/November 2020

CMOS Analog Integrated Circuit Design

(VLSI&ES)

Roll No

Time: 2 hours Max. Marks: 70

Answer Any Four Questions

All Questions carries equal marks.

***

1 Write a brief note on various passive components that are available in CMOS

technologies with relevant layout diagrams

2 Analyze the Simple MOS Large-Signal Model with the associated parameters in

detail.

3 Illustrate the MOS switch operation and various models with application

4 Explain the concept of current sink and Design a current sink of 250µA and a VMIN of 0.5V

using self biased high-swing cascade current source.

5 Illustrate the various types of CMOS inverting Amplifiers and small signal model

demonstrating the parasitic capacitances

6 a) Design a differential Input Current Amplifier

b) Briefly give a overview of High Gain Amplifiers Architectures

7 Describe the miller compensation of a two stage op amp.

Page 19 of 21
 8 Illustrate the discrete-time comparators with relevant schematics

**********

R15
Code No: R15D6805

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)

M.Tech I-Year - I Semester Supplementary Examinations, Dec-18/Jan-19

CMOS Analog Integrated Circuit Design
(VLSI&ES)

Roll No

Time: 3 hours Max. Marks: 75

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE Question from
each SECTION and each Question carries 15 marks.

*****

Bloo
Marks CO ms
Level
SECTION-I
Q.1. a) Explain about MOS large- signal analysis of CMOS Device Modeling [10M] CO1 2

b) Explain sub-threshold MOS model Parameters. [5M] CO1 2

OR
Q.2. a) Discuss about the passive components of the MOS transistor. [7M] CO2 2

b) Write about computer simulation models for MOS transistor [8M] CO2 2
SECTION-II
Q.3. a) Explain the working of current mirror with beta helper [10M] CO2 2

b) Explain the operation of MOS Diode [5M] CO2 1

OR
Q.4. Discuss the Cascode current Mirror and Wilson Current Mirror CO2 2
[15M]

Page 20 of 21
 SECTION-III
Q.5. a) Explain about working of differential amplifier [10M] CO3 3
b) Explain the operation of CMOS inverter [5M] CO3 3
OR
Q.6. Discuss the principle of High Gain Amplifiers Architectures CO3 1

[15M]
SECTION-IV
Q.7. Discuss the concept of op amp compensation and give the necessary CO4 2
expressions.
[15M]
OR
Q.8. a) Explain the Design of Two-Stage Op Amps [10M] CO4 6

b) What are the various measurements of op amp? [5M] CO4 5

SECTION-V
Q.9. a) Explain the Discrete-Time Comparators. [7M] CO4 2

b) What is a comparator and list the important characteristics of a comparator [8M] CO4 2
OR
Q.10. What are the various forms of improving the slew-rate of a 2-stage op [15M] CO5 2
amp and obtain the expression for slew rate of CMOS op amp

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