SSK PUBLICATION CHAPTER NOTES 1

(2) Decimal number system:

SECTION-C
LOGIC GATES A number system which has ten digits i.e. 0 to 9
are known as decimal system.
 Communication signal (Analog and
digital signal): TYPE-I: Conversion of Decimal number to
Binary number
(1) Analog Signal:

Analog signal is continuous time varying (i) 310   ......2 (ii) 1210   ....2

current (or) voltage signal e.g., a sine wave.

TYPE-II: Conversion of Binary to decimal
number
+ V0
V
(i) 1012   .....10 (ii) 1112   ......10
Time
– V0
 Binary Addition:

Rules: (i) 0  0  0 (ii) 0  1  1

(2) Digital Signal:
(iii) 1  0  1 (iv) 1  1  10 (v) 1  1  1  11
It is a pulsating waveform having only two
discrete values of current (or) voltage
(i) Add: 11010 and 11011
represented as a 0 and 1.
1 1 0 1 0
0 0 1 1 0 0
+ 1 1 0 1 1

11 0 1 0 1

OFF, OPEN, NO 
0
 Binary Subtraction:
ON, CLOSE, YES 
1
Rules: (i) 0  0  0 (ii) 1  0  1
NOTE: The electronic circuit used to process the
(iii) 1  1  0 (iv) 10  1  1
digital signals is known as digital circuit.

(i) Subtract: 11110 from 1011

 Number-System
1 1 1 1 0
(1) Binary number system:
- 0 1 0 1 1
A number system which has only two digits i.e. 0
and 1 is known as binary number system. 1 0 0 1 1
SSK PUBLICATION CHAPTER NOTES 1
 Logic Gate:
A

A gate is a digital circuit that is designed for

performing a particular logical operation. It is B

called gate because it controls the flow of

information.  Boolean-Expression: A  B  Y
As it works according to some logical A
 Logic symbol:
relationship between input and output Y

voltages, so it is also known as a logic gate. B

Truth-Table:
 Truth table:
𝑰𝒏𝒑𝒖𝒕 𝑶𝒖𝒕𝒑𝒖𝒕
It is a table that shows all possible input
𝑨 𝑩 𝒀
combinations and the corresponding output for
a logic gate. 0 0 0

0 1 1
 All possibilities for logic gates:
1 0 1
𝑰𝒏𝒑𝒖𝒕 𝑶𝒖𝒕𝒑𝒖𝒕
1 1 1
𝑨 𝑩 𝒀

0 0 …….
 Realization of OR gate:
1 0 ……. D1
A
0 1 ……. Y
R
1 1 ……. B
D2

(i) A = 0, B = 0
 Boolean expression:
Both diodes D1 and D2 do not conduct,Y = 0
“It is a shorthand method to describe the
functioning of a logic gate in the form of an (ii) A = 0, B = 1
equation (or) an expression.” D1 = Does not conducts, D2 = Conducts, Y = 1

AND GATE - OR GATE - NOT GATE

(iii) A = 1, B = 0
D1 = Conducts, D2 = Does not conduct,  Y = 1
 OR-Gate (Represented by (+) sign):

An OR gate has two or more inputs but only one (iv) A = 1, B = 1

output. Both D1 and D2 conducts,  Y = 1
 SSK PUBLICATION CHAPTER NOTES 2
 AND-Gate (Represented by (·) sign): (ii) A = 0, B = 1

An AND gate has two (or) more inputs but only D1 = conducts, D2 = Not Conducts
one output.
The out voltage at Y =The voltage across the
A B
diode (D1) = 0

(iii) A = 1, B = 0

 Boolean-expression: Y  A. B D1 = Conducts, D2 = Not conducts

The out voltage at Y= The voltage across the

 Logic symbol: A
Y diode (D2) = 0
B

(iv) A = 1, B = 1
Truth-Table:
None of the diode conducts
𝑰𝒏𝒑𝒖𝒕 𝑶𝒖𝒕𝒑𝒖𝒕
The out voltage at Y= Battery voltage =1
𝑨 𝑩 𝒀

0 0 0  NOT-Gate

0 1 0 A NOT gate is simplest gate, with one input and

1 0 0 one output.

1 1 1

 Realization of AND gate:

D1
A
 Boolean-expression: Y  A  B
Y
V R
B V  Logic symbol:
D2
0 A Y

(i) A = 0, B = 0 Truth-Table:

The voltage supply through R is forward biasing 𝑰𝒏𝒑𝒖𝒕 (𝑨) 𝑶𝒖𝒕𝒑𝒖𝒕 (𝒀)
diodes D1 and D2 (offers low resistance) the 0 1
voltage V would drop across R
1 0
The output voltage at Y = the voltage across
diode = 0
SSK PUBLICATION CHAPTER NOTES 3
 Realization of NOT gate:

The transistor is so biased that the collector

voltage VCC = V (Voltage corresponding to 1 state)

The resistors R and R1 are so chosen that if the

input is low i.e. O, the transistor is in the cut off
and hence the voltage appearing at the output
will be the same as applied V. Hence Y = V (or
state 1)

If the input is high, the transistor current is in

saturation and the net voltage at the output Y is
0 (in state 0)

VCC = V

R
Y
R1 C
1 A
B
V E

0
SSK PUBLICATION CHAPTER NOTES 1
Truth-Table:
 Combination of Gates:
𝑰𝒏𝒑𝒖𝒕𝒔 𝑶𝒖𝒕𝒑𝒖𝒕
(1) NAND Gate:

A NAND gate is a combination of AND

𝑨 𝑩 Y '  A B Y Y '

and NOT gates. 0 0 0 1

 Boolean-expression: Y  A. B 1 0 1 0

0 1 1 0
 Logic symbol:
1 1 1 0
A Y = A ·B
AND NOT
B
 NOR gate is a universal gate because it can be
A
 Y used to perform the basic logic function, AND,
B
OR and NOT.
Truth-Table:

𝑰𝒏𝒑𝒖𝒕𝒔 𝑶𝒖𝒕𝒑𝒖𝒕

𝑨 𝑩 Y '  A. B Y Y '

0 0 0 1

1 0 0 1

0 1 0 1

1 1 1 0

(2) NOR-Gate:

A NOR gate is a combination of OR

and NOT gates.

 Boolean-expression: Y  A  B

 Logic symbol:
A Y = A + B
OR NOT
B

A
 Y
B
SSK PUBLICATION CHAPTER NOTES 1
 Construction of primary logic gates using (c) OR-Gate from a NAND-Gate:

NAND-Gate: When the output of two NOT gate (obtained

from the NAND gate) is given the inputs of
(a) NOT Gate from NAND-Gate:
the NAND gate, the resultant logic gate works as
When two inputs A and B of a NAND gate are
the OR-Gate.
joined together them it works as NOT gate.
A
A
A Y

B Y

B
B
Truth-Table:
Truth-Table:
𝑰𝒏𝒑𝒖𝒕𝒔 (𝑨 = 𝑩) 𝑶𝒖𝒕𝒑𝒖𝒕 (𝒀)
𝑰𝒏𝒑𝒖𝒕𝒔 𝑶𝒖𝒕𝒑𝒖𝒕
0 1
𝑨 𝑩 A B A .B Y  A.B
1 0

0 0 1 1 1 0
(b) AND Gate from a NAND-Gate:
1 0 0 1 0 1
To get an AND gate from a NAND gate, a NOT
0 1 1 0 0 1
gate is used after the NAND gate.
1 1 0 0 0 1
Y Y
A

B
NOTE: (i ) Y  A.B  A  B (ii ) Y  A  B  A.B

Truth-Table:

𝑰𝒏𝒑𝒖𝒕𝒔

𝑨 𝑩 Y '  A. B Y Y1

0 0 1 0

1 0 1 0

0 1 1 0

1 1 0 1
SSK PUBLICATION CHAPTER NOTES 1
(3) The ‘XOR’ gate: Miscellaneous Exercise

The logic gate which gives high output (i.e., 1) if Q.1. In circuit in following figure the value of Y:
either input A (or) input B but not both are high
(i.e. 1) is called exclusive OR gate or the XOR
gate (it not a universal gate because they are
not gives OR /AND/NOR/NAND).

If both the inputs of the XOR gate are high, then

the output is low (i.e., 0).
(a) Zero
A
A Y   A. B
B (b) 1
Y
(c) Fluctuates between 0 and 1
A
B
(d) Indeterminate as the circuit cannot be
B Y   A. B
A realized
 Y
B

SOLUTION: (a)
Boolean expression: Y = A  B = AB  AB

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

(4) The exclusive NOR (XNOR) gate:

XOR + NOT XNOR

A
Y
B

A
 Y
B

 Boolean expression: Y = A  B = A B  AB
SSK PUBLICATION DAILY ACTIVITY 1
DIGITAL ELECTRONICS (a) XOR (b) AND

(c) XNOR (d) OR

1. The following truth table corresponds
to the logic gate 4. For the given combination of gates, if the

A 0 0 1 1 logic states of inputs A, B, C are as

follows A = B = C = 0 and A = B = 1, C = 0
B 0 1 0 1
then the logic states of output D are
X 0 1 1 1 A
(a) 0, 0
(a) NAND ✔(b) OR B G2
(b) 0, 1 G1
D
(c) AND (d) XOR
(c) 1, 0 C
2. The combination of ‘NAND’ gates
(d)
✔ 1, 1
shown here under are equivalent to
5. The logic behind ‘NOR’ gate is that it
A gives
C
(a) High output when both the inputs are
✔
B
low

(b) Low output when both the inputs are

A C
B low

(c) High output when both the inputs are

(a) An OR gate and an AND gate high
respectively
(d) None of these
(b) An AND gate and a NOT gate
6. What will be the input of A and B for the
respectively
Boolean expression ( A  B )( A  B )  1
(c) An AND gate and an OR gate
respectively (a)
✔ 0, 0 (b) 0, 1

(d) An OR gate and a NOT gate (c) 1, 0 (d) 1, 1

respectively. 7. If A and B are two inputs in AND gate,

3. The truth table shown in figure is for then AND gate has an output of 1 when
the values of A and B are
A 0 0 1 1
(a) A = 0, B = 0 (b) A = 1, B = 1
✔
B 0 1 0 1
(c) A = 1, B = 0 (d) A = 0, B = 1
Y 1 0 0 1
SSK PUBLICATION DAILY ACTIVITY 2
8. To get an output 1 from the circuit
shown in the figure, the input must be

(a) A  0, B  1, C  0
A
B
(b) A  1, B  0, C  0
C
(c) A  1, B  0, C  1

(d) A  1, B  1, C  0

9. The combination of the gates shown in

the figure below produces

(a) NOR gate A

A
(b)
✔ OR gate
Y
(c) AND gate B
B
(d) XOR gate

10. A gate in which all the inputs must be

low to get a high output is called [UPSEAT 2004]

(a) NAND gate (b) An inverter

(c) NOR gate (d) An AND gate

11. Sum of the two binary numbers

(100010)2 and (11011)2 is [DCE 2004]

✔ (111101)2
(a) (b) (111111)2

(c) (101111)2 (d) (111001)2

12. The truth-table given below is for which

gate

A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

(a) XOR (b) OR

(c) AND (d)

✔ NAND
SSK PUBLICATION DAILY ACTIVITY 3
SOLUTION 5. (a) Boolean expression for ‘NOR’ gate is

1. (b) For ‘OR’ gate: X  A  B Y  A B

i.e. 0  0  0 , 0  1  1 , 1  0  1 , 1  1  1 i.e. if A  B  0 (Low), Y  0  0  0  1 (High)

2. (a) 6. (a) Given: Boolean expression can be

A A
Y  ( A  B ).( A.B )  ( A.B ).( A  B )  ( A A).B  A(B.B )
C

 A.B  A B  A B
B
B
A B Y
C  A.B  A  B  A  B (De morgan’s theorem)
0 0 1
Hence output C is equivalent to OR gate.
1 0 0
AB
A
C 0 1 0
B

1 1 0
C  AB. AB  AB  AB  AB  AB  AB

Output C is equivalent to AND gate. 7. (b) For ‘AND’ gate, if output is 1 then
both inputs must be 1.
3. (c)For ‘XNOR’ gate Y  A B  AB
8. (c) The Boolean expression for the
i.e. 0.0  0.0  1.1  0.0  1  0  1 given combination is output Y   ( A  B ).C
0.1  0.1  1.0  0.1  0  0  0
The truth table is
1.0  1.0  0.1  1.0  0  0  0
A B C Y =(A+B).C
1.1  1.1  0.0  1.1  0  1  1
0 0 0 0

4. (d) The output D for given combination 1 0 0 0

D  ( A  B ).C  ( A  B )  C 0 1 0 0

 If A  B  C  0 then 0 0 1 0

D  (0  0)  0  0  0  1  1  1 1 1 0 0

 If A  B  1 , C  0 then 0 1 1 1

D  (1  1)  0  1  0  0  1  1
SSK PUBLICATION DAILY ACTIVITY 4
1 0 1 1  Required sum (in binary system)

1 1 1 1 1000102  110112  1111012

Hence A  1 , B  0 , C  1 12. (d) For ‘NAND’ gate: C  A.B

9. (b) i.e. 0.0  0  1 , 0.1  0  1

A A
1.0  0  1 , 1.1  1  0
Y

B
B
Y  A.B  A  B  A  B

Output equation is equivalent to OR gate.

10. (b)

11. (a) 100010 2  25  1  24  0

23  0  22  0  21  1  20  0  34 10

 110112  24  1  23  1  22  0  21  1  20  1

 16  8  0  2  1  27 10

 Sum 100010 2  11011 2

 34 10  27 10   6110

2 61 Remainder

2 30 1 LSD

2 15 0

2 7 1

2 3 1

2 1 1

0 1 MSD
SSK PUBLICATION 1
(a) NAND OR
A
BOUNCE SERIES (b) XOR
B
G1 AND
Y
NAND
(c) OR G3
LOGIC GATES
(d) None of these G2

1. In a negative logic the following wave

4. Figure gives a system of logic gates. From
form corresponds to the
the study of truth table it can be found
Voltag that to produce a high output (1) at R, we
e
10 volt
must have
X
5 volt P
Y R

5 10 15 20 25 30 35 40 45 50
Time in s
Q
(a) 0000000000 (b) 0101101000
(a) X = 0, Y = 1 (b) X = 1, Y = 1
(c) 1111111111 (d)
✔ 1010010111
(c) X = 1, Y = 0 (d) X = 0, Y = 0
2. The given figure shows the wave forms
for two inputs A and B and that for the 5. The combination of gates shown below

output Y of a logic circuit. The logic produces

circuit is (a) AND gate A G1

(A) (b) XOR gate G3 Y

G4

(c) NOR gate

O T1 T2 T3 T4 t B G2
(d) NAND gate

6. The shows two NAND gates followed by a

(B)
O T1 T2 T3 T4 t NOR gate. The system is equivalent to
the following logic gate
A X
(a) OR
(Y)
(b) AND Z
O T1 T2 T3 T4 t B

(c) NAND
(a) An AND gate
✔ (b) An OR gate
C Y
(d) None of these
(c) A NAND gate (d) An NOT gate

3. The following configuration of gate is

equivalent to
SSK PUBLICATION 2
7. The diagram of a logic circuit is given SOLUTION
below. The output F of the circuit is
1. (d) 5 volt is low signal (0) and 10 volt is
represented by
high signal (1) and taking 5 -sec as 1 unit.
W In a negative logic, low signal (0) gives high
X output (1) and high signal (1) gives low

F
output (0). The output is therefore
1010010111.
W
Y
2. (a) From the given waveforms, the
following truth table can be made
(a) W   X  Y  (b) W  X Y 
Time interval Inputs Output
(c) W   X Y  (d) W   X  Y 
A B Y

0  T1 0 0 0

T1 T2 0 1 0

T2T3 1 0 0

T 3 T 4 1 1 1

This truth table is equivalent to ‘AND’ gate.

3. (b)

A (A + B)
B
G1 Y

A G3
Y (A B).AB
B AB
G2

Output Y    A  B  .  A  B 

 AA  AB  BA  BB  0  AB  AB  0  AB  AB

This is the expression for XOR gate.

SSK PUBLICATION 3
4. (c)
X
X
P
Y
Y R

Q
Y R  P Q

Hence X = 1, Y = 0 gives output R =1

5. (d)
A
A
NOR NOT
NOT

A B
NOT A  B  AB

B
B

6. (b) Output Z  R  P  Q  of single three

input gate is that of AND gate.

7. (c) Output of upper OR gate = W + X

Output of lower OR gate = W + Y

Net output: F = (W + X) (W + Y)

= WW + WY + XW + XY (Since WW = W)

= W (1 + Y) + XW + XY (Since 1 + Y= 1)

= W + XW + XY = W (1 + X) + XY = W + XY
 CHAPTER-19 A B A C  A B D  A B E CD

ELECTRONIC DEVICE 0 0 1 0 0 0

SEQUENCE-4 0 1 1 0 1 1

LOGIC GATES 1 0 0 0 0 0

1 1 0 1 0 1
Only One Option Correct Type

1. Truth table for the given circuit (fig) is

Solution: (c)

1 SSK PUBLICATION