Received 21 November 2024; accepted 2 December 2024.

Date of publication 9 December 2024;

date of current version 18 December 2024. The review of this article was arranged by Associate Editor Marco Jung.
Digital Object Identifier 10.1109/OJPEL.2024.3513219

A Novel Soft-Switched SEPIC-Based DC–DC

Converter With High Voltage Gain
REZA ASGARNIA 1, EHSAN ADIB 2 (Member, IEEE), EBRAHIM AFJEI 1 (Member, IEEE),
AND HADI TARZAMNI 3 (Student Member, IEEE)
1
Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran 19839-69411, Iran
2
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan 84156-83111, Iran
3
Department of Electrical Engineering and Automation, Aalto University, 02150 Espoo, Finland
CORRESPONDING AUTHOR: HADI TARZAMNI (e-mail: [email protected])
This work was supported by the Finnish Electronic Library (FinElib), Finland, under Grant FinELib Consortium’s Agreement with IEEE.

ABSTRACT This study introduces a novel high-gain DC-DC converter by integrating a coupled inductor
(CI) and a voltage multiplier cell (VMC) into the conventional SEPIC topology. An auxiliary switch,
benefiting from zero voltage switching (ZVS), is applied to provide ZVS for the main switch over a wide
output power range. Moreover, the employed diodes turn off under zero current switching (ZCS), thus
eliminating reverse recovery losses and increasing efficiency. This study conducts a comprehensive analysis
and compares the proposed converter with state-of-the-art topologies. The claimed features are verified by
implementing a prototype that converts 36 to 250 V.

INDEX TERMS Zero voltage switching (ZVS), zero current switching (ZCS), high step-up converter,
coupled inductor.

I. INTRODUCTION Diverse techniques and circuits have been suggested to

The escalating consumption of fossil fuels in recent years overcome the limitations of the boost structure. Cascading
has exacerbated global warming, emerging as one of the ma- two converters is one way to increase voltage gain. A
jor concerns worldwide. Therefore, numerous solutions have cascaded converter with a lossless snubber circuit to recover
been proposed to reduce the impact of this crisis on the planet. leakage inductance energy is introduced in [5]. However, the
Renewable energy sources, such as photovoltaic panels, have number of components utilized in this topology is substantial,
gained popularity as a practical solution due to their remark- resulting in a significant increase in loss and cost. In addition,
able advantages. However, the output voltage of these sources using three magnetic cores in the structure makes the circuit
needs to be enhanced to supply the DC link of inverters. bulky and heavy.
Hence, increasing the output voltage amplitude of panels is The authors in [6] suggest a three-level boost converter to
inevitable, and high-gain converters are required to achieve reduce semiconductor voltage stress. However, the provided
this goal [1], [2]. voltage gain is small, and the duty cycle is the only variable
The ideal conventional boost converter can provide the that influences voltage gain. Consequently, there is a necessity
desired voltage gain by setting the duty cycle properly. Ac- to substantially increase the duty cycle to achieve high gain,
cordingly, infinite voltage gain is accessible as the duty leading to an increase in conduction loss.
cycle approaches the unity. However, under non-ideal cir- The interleaved technique is extensively employed to mit-
cumstances, increasing the duty cycle to considerable val- igate input current ripple and reduce current stress across
ues leads to decreased power transferring time to the semiconductors. The interleaved converters suggested in [7],
output and a rise in losses. Furthermore, the boost con- [8], [9] accomplish this purpose. Besides using too many
verter encounters significant voltage stress across semicon- diodes and switches in [7] and [8], both converters use three
ductors and offers limited voltage gain, presenting chal- magnetic cores, increasing the weight and volume. Also, using
lenges for its utilization in high-voltage applications [3],
[4].
© 2024 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
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ASGARNIA ET AL.: NOVEL SOFT-SWITCHED SEPIC-BASED DC–DC CONVERTER WITH HIGH VOLTAGE GAIN

four active switches in [9] complicates the control and drive

circuits and increases cost.
Z-source converters can achieve a high voltage gain at
small duty cycle values. However, the discontinuous input
current of these converters makes their use in PV panel
applications challenging [10]. To address this issue, quasi-
z-source converters are introduced. The proposed structures
in [11] and [12] simultaneously draw a continuous input
current and have the benefits of z-source topologies. Neverthe-
less, using numerous components is the significant drawback
of the converters. FIGURE 1. The proposed converter.
A single-switch high-gain CI-based converter is presented
in [13]. Despite the reduced number of components and sim-
ple structure, the loss of the switch is remarkable due to hard- turning on. Notably, diodes turn off at ZCS, significantly re-
switching performance and significant current stress. In [14] ducing switching and reverse recovery losses.
and [15], high-gain converters employing the switched-
capacitor technique are proposed. The bold disadvantages of II. PRINCIPLE OPERATION
the introduced topologies are the use of many capacitors and The proposed converter based on the SEPIC structure is il-
diodes to achieve high voltage gain and substantial switching lustrated in Fig. 1. L1 , C1 , and Q1 are the components of
loss due to the hard-switching performance. VMC with a the conventional SEPIC converter. It is observable that the
combination of diodes and capacitors in [16] and a combi- second inductor and output diode in the conventional SEPIC
nation of switch, diodes, and inductor in [17] are presented. converter are replaced with a CI and a switch, respectively.
Although the voltage gain rises by these cells, providing a The CI model includes a leakage inductance (LLK ) referred
significant voltage gain requires adding many cells in the con- to the secondary side, magnetizing inductance (Lm ), and an
verter. Consequently, the number of components in high-gain ideal transformer with the turn ratio of n = NS /N p . A VMC
applications is significantly increased. In addition, switches consisting of CI secondary, C3 and D2 , is added to the circuit
in [17] turn off/on under hard switching, increasing switching to increase voltage gain.
loss. D1 and C2 also make a clamp circuit to eliminate the
The converters proposed in [18] and [19] employ auxil- voltage spike across the main switch. Q2 is the auxiliary
iary switches to provide soft-switching performance, and both switch employed to create the ZVS circumstances for the
converters provide significant voltage gain. However, [18] main switch. Notably, Cs1 and Cs2 are the snubber capacitors
utilizes many components, and the topology in [19] has the of Q1 and Q2 , respectively. L1 operates in the continuous
drawbacks of omitting common ground and the substantial current mode (CCM) in the entire switching cycle, while Lm is
input current ripple. Soft-switched structures without auxil- assumed to be small enough that its current polarity changes
iary switches are given in [20], [21], [22], [23]. Nevertheless, in one switching period. Moreover, the semiconductors are
the voltage gain provided by [20] is small, necessitating mul- considered ideal for simplifying calculation and analysis in
tiple VMCs for high-voltage applications. Converters in [21] the steady state. Fig. 2 illustrates the key waveforms of the
and [22] have the disadvantages of discontinuous input current proposed converter, and anticipated operating modes are de-
and employing many semiconductors, respectively. Notably, picted in Fig. 3.
the diodes in [23] withstand the stress identical to the output Mode 1 [t0 −t1 ]: Q1 is turned on, and the input voltage
voltage irrespective of duty cycle value and turn ratio. magnetizes L1 . Consequently, the input current, identical to
Several topologies utilizing the SEPIC structure are intro- the L1 current, increases linearly. Since the voltage difference
duced in [24], [25], [26], [27], [28]. However, the topologies between C1 and C2 is applied to Lm , its current decreases to
introduced in [24], [25], [26], [27] suffer from hard-switching zero. D1 is deactivated with the clamped voltage stress equals
performance, whereas the design presented in [28] provides the C2 voltage. Moreover, Q2 is turned off and withstands
limited voltage gain. The modified SEPIC-based converter voltage stress of difference between C1 and Co voltages. D2
presented in [29] achieves substantial voltage gain by employ- current is diminished because of the linear decline in the
ing a CI and a VMC. Nevertheless, this design only provide current of the leakage inductor. Notably, the output capacitor
ZCS during the switch turn-on. supplies the load, and the following equations can be derived.
This paper proposes a novel high step-up fully soft-
switched converter based on SEPIC structure and CI. Besides VL1 = Vin (1)
common ground between input and load, the proposed con- VLm = VC1 − VC2 (2)
verter provides a continuous input current with a small ripple.
Both switches turn off/on at ZVS, eliminating switching loss Mode 2 [t1 −t2 ]: This mode begins when Lm current falls
in the topology. Additionally, ZVS turn on of switches re- below zero, decreasing linearly after the polarity reverses.
moves capacitive loss caused by snubber capacitors during Notably, the CI secondary current still declines.

2 VOLUME 6, 2025
 Mode 7 [t6 −t7 ]: Q2 turns on at ZVS due to the conduction
of its body diode. Q2 current linearly decreases until it reaches
zero, after which its polarity reverses. Furthermore, the Lm
current increases until it approaches zero.
Mode 8 [t7 −t8 ]: The polarity of the Lm current changes,
and its increase continues. Moreover, the leakage inductor
current is still decreasing linearly. The leakage current reaches
zero as the Lm current equals the input current.
Mode 9 [t8 −t9 ]: This mode commences when the polarity
of the leakage current is reversed. The current passing through
Q2 matches the leakage inductor current, leading to a linear in-
crease in the amplitude of the Q2 current. The leakage current
can be determined using Kirchhoff’s law, as indicated in (5).
ILm − Iin
ILk = (5)
1+n
Mode10 [t9 −t10 ]: Due to the presence of the Cs2 , Q2 can be
turned off at ZVS. Resonating with leakage inductance causes
the voltage of Cs2 to increase until its maximum voltage is
reached. Q2 turning off besides stored energy in the leak-
FIGURE 2. Key waveforms.
age inductance creates the circumstances in which D2 starts
conducting. Additionally, Cs1 discharges with the current dif-
ference between Lm , L1 , and the primary of the CI. This mode
continues until Cs1 is completely discharged and Cs2 reaches
Mode 3 [t2 −t3 ]: Since the passing current reaches zero, D2 its maximum value.
becomes deactivated at ZCS, eliminating the reverse recovery Mode 11 [t10 −t11 ]: The discharge of Cs1 causes the diode
loss. The voltage stress is then clamped to the sum of C3 and body of Q1 to conduct. Consequently, the main switch can be
the CI secondary voltages. Furthermore, the currents of Lm activated at ZVS, eliminating switching loss. After Q1 turns
and C1 become identical, and the sum of L1 and Lm currents on, C1 current decreases until reversing the polarity, and the
flows through the main switch. The Lm current continues to next cycle can be started.
decrease with the same applied voltage as in the previous
modes. III. STEADY-STATE ANALYSIS
Mode 4 [t3 −t4 ]: Q1 is turned off, and the snubber capacitor Using (1), (2), (3), and (4) along with the volt-second balance
restricts the rate of voltage variation across it. Therefore, Q1 of L1 and Lm results in the following average capacitor volt-
is turned off at ZVS. Meanwhile, the current passes through ages.
D2 and the leakage inductor discharges the snubber capacitor
of Q2 . At the end of the mode, Cs1 voltage increases to its D
VC1 = Vin (6)
maximum value, while Cs2 voltage decreases until it reaches 1−D
zero. Vin
Mode 5 [t4 −t5 ]: The discharging of Cs2 and the leakage VC2 = (7)
1−D
inductance presence cause the body diode of Q2 to conduct.
Once voltage of Cs1 reaches VC2 , D1 begins conducting. Con- Considering leakage inductance impact, the C3 voltage can be
sequently, the applied voltage to Lm is equal to VC1 , which obtained as (8).
means the slope of its current becomes positive. Also, C1 VC3 = nVin − VLK (8)
discharges until its current equals the input current, causing
D1 to turn off at ZCS. Employing (4), (7), and (8) results in the output voltage equa-
Mode 6 [t5 −t6 ]: After D1 turns off, part of the stored en- tion as follows.
ergy in L1 and Lm is transferred to the output through the body 1+D+n VLK
diode of Q2 . Consequently, Q2 can be activated at any time at Vo = Vin − (9)
1−D 1−D
ZVS. The leakage current decreases from the maximum value
reached in the previous mode. The following equations can be Considering the linear decrease of the current in the leakage
derived. inductor when the main switch is turned on, the time at which
the leakage current reaches zero and the leakage inductor
VL1 = Vin + VC1 − VLm − VC2 (3) voltage can be expressed as (10) and (11), respectively.
Vo VC2 VC3 VLK 2Io (1 + n)Ts
VLm = − − − (4) t = (10)
1+n 1+n 1+n 1+n ILm ,peak − IL1 ,min

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FIGURE 3. Operation modes of the proposed converter, (a) mode 1 [t0 − t1 ], (b) mode 2 [t1 − t2 ], (c) mode 3 [t2 − t3 ], (d) mode 4 [t3 − t4 ], (e) mode 5
[t4 − t5 ], (f) mode 6 [t5 − t6 ], (g) mode 7 [t6 − t7 ], (h) mode 8 [t7 − t8 ], (i) mode 9 [t8 − t9 ], (j) mode 10 [t9 − t10 ], (k) mode 11 [t10 − t11 ].

LLK (ILm ,peak − IL1 ,min ) during the main switch ON-time.
VLK = (11)
t  (1 + n) (VC1 − VC2 )D
Regarding (3), (4), and (6)–(8), the voltage stresses across the ILm = (16)
Lm f
semiconductors are as follows.
Substituting (16) in (15) results in a critical inductance value
Vin
VQ1 = VD1 = (12) of Lm as below.
1−D
(1 + n)Vin − VLK (VC1 − VC2 )D
VQ2 = (13) Lm < (17)
1−D 2 f (Iin − Io )
nVin − VLK To create the ZVS condition for switches in mode 10, the
VD2 = (14)
1−D snubber capacitors of Q1 and Q2 must be discharged and
charged, respectively. It can be assumed that the leakage in-
IV. DESIGN CONSIDERATIONS ductance is referred to the primary side. Hence, the series Lm
According to (5), the peak of Lm current must exceed the and LLK , parallel with the L1 , can be considered the equivalent
input current to reverse the leakage current. Therefore, the inductor that charges/discharges snubber capacitors. In other
following equation must be satisfied. words, the equation below must be satisfied.
ILm 1 1
+ ILm ,avg > Iin (15) Leq Ieq 2 > CeqV 2 (18)
2 2 2
Where ILm and ILm indicate the current ripple and aver-
where Ieq can be calculated as follow.
age current of the magnetizing inductor, respectively. Using
ampere-second balance and Kirchhoff’s law, the average cur- ILm − Iin
rent of Lm equals −Io. Also, ILm can be calculated as (16) Ieq = (19)
1+n
4 VOLUME 6, 2025
 FIGURE 6. The prototype.

FIGURE 4. Voltage gain for investigated converters.

the gain ratio to components count is calculated with the duty

cycle of 50% and the turn ratio of 2.
As a summary of Table 1, the proposed converter has a
significant gain ratio to components count, which means the
introduced topology can provide a high voltage gain using
few components. Besides insignificant input current ripple,
the proposed converter provides soft-switching for switches
and common ground between the input source and the load.
Fig. 4 illustrates the voltage gain of different topologies. The
proposed converter demonstrates a higher voltage gain than
the others over a wide range of duty cycles below 45%, ex-
cept [29]. However, it is important to note that [29] uses more
components than the proposed converter and only provides
ZCS for the switch during turn-on. As the duty cycle exceeds
55%, the voltage gain provided by [5], [24] significantly rises.
FIGURE 5. The normalized voltage stress across main switches in the
investigated topologies.
Nevertheless, The mentioned topologies suffer from hard-
switching performance.
Table 1 also presents the normalized voltage stress across
Assuming the same value for snubber capacitors, the critical diodes and switches, defined as the ratio of the voltage stress
capacitance value can be expressed below. on each semiconductor to the converter’s output voltage.
   Fig. 5 shows the voltage stress across the main switch in the
LLK
(ILm − Iin )2 Lm + 2 ||L1 studied topologies. The key point is that the voltage stress
n
Cs1,2 < (20) on the main switch of the proposed converter remains below
(1 + n) Vin (1 + (1 + n)2 )
2 2
one-third of the output voltage across the entire duty cycle
The value of L1 , C1 , C2 , C3 , and Co can be written as follows. range.
Vin D
L1 = (21)
f IL VI. EXPERIMENTAL RESULTS AND EFFICIENCY ANALYSIS
A prototype with 36 V input voltage, 250 V output voltage,
Io (n + D)
C1 = C2 = (22) and 100 W output power is implemented to approve the per-
f VC formance and theoretical relations. Notably, the duty cycle
IoD is about 50%, and the turn ratio is considered 2. Fig. 6 and
C3 = Co = (23)
f VC Table 2 represent the prototype photograph and the character-
istics of the implemented converter, respectively.
V. COMPARISON Fig. 7 illustrates the breakdown of losses in the converter
To evaluate performance, the converter’s characteristics are at 100 W, utilizing parasitic component values obtained from
compared with recently introduced topologies. Table 1 dis- the datasheets and equations provided in Table 3. Notably,
plays different features and parameters of the surveyed topolo- the switching loss of the switches and reverse recovery loss
gies. The voltage gain relations in Table 1 are calculated by of diodes are ignored due to the soft-switching performance
choosing k = m = 1, where k represents the coupling factor, of the converter. Observably, a substantial portion of the con-
and m is the number of stages in extendable topologies. Also, verter loss is related to the inductor.

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TABLE 1. Different Features and Parameters of the Surveyed Topologies

observable that voltage stress across diodes validates the

theoretical expectations. Additionally, both diodes turn off
at ZCS, eliminating their switching and reverse recovery
losses.
The gate-source voltages besides the L1 current are indi-
cated in Fig. 8(c). The L1 current represents the input current
appropriate for renewable energy applications due to con-
tinuity. Additionally, L1 is magnetized as the main switch,
or its body diode conducts, leading to a linear rise in the
current. The voltage and current of capacitors are shown in
Fig. 8(d)–(f). Notably, the current flowing through C3 is the
FIGURE 7. Loss breakdown of the proposed converter for 100 W output same as the referred leakage inductor current.
power. Q1 voltage reaches zero before its current rises due to the
ZVS condition, as depicted in Fig. 8(g). Also, the figure shows
the ZVS performance of Q1 at turning off, which happens
The experimental waveforms of the proposed converter due to the existence of Cs1 . The voltage and current of Q2
under full load are depicted in Fig. 8. The voltage and are shown in Fig. 8(h). The initial passing current is negative,
current of diodes are displayed in Fig. 8(a) and (b). It is indicating that the body diode is conducting. Hence, Q2 turns

6 VOLUME 6, 2025
FIGURE 8. The experimental waveforms under full load. (a) Voltage and current of D1 , (b) Voltage and current of D2 , (c) Gate-source voltage of Q1 ,
gate-source voltage of Q2 , and input current, (d) Voltage and current of C1 , (e) Voltage and current of C2 , (f) Voltage and current of C3 , (g) Voltage and
current of Q1 , (h) Voltage and current of Q2 .

FIGURE 9. The experimental waveforms under light load. (a) Voltage and current of Q1 , (b) Voltage and current of Q2 , (c) Gate-source voltage of Q1,
gate-source voltage of Q2, and input current.

on under the ZVS circumstance at any time. Furthermore, diodes of switches are conducting. Hence, soft-switching per-
the ZVS condition at turning off is provided with the help formance is not lost at light loads.
of Cs2 . The efficiency of the proposed converter and other topolo-
To evaluate the performance of the converter under light gies is depicted in Fig. 10. To ensure a fair comparison,
load, the voltage and current of the main and auxiliary the converters are simulated after redesigning components
switches besides L1 current at 20% of output power are illus- to achieve optimized performance at the same output power.
trated in Fig. 9. When the voltage of switches reaches zero, What stands out from the illustration is that the proposed
the passing currents are negative, indicating that the body converter provides higher efficiency compared to others for all

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TABLE 2. Characteristics of the Implemented Prototype the power ranges studied. Moreover, the proposed converter
has a higher efficiency in the full load than in the light load.

VII. CONCLUSION
This study presents a novel soft-switched SEPIC-based high
step-up converter. By ensuring diodes turn off under ZCS
conditions, the converter eliminates reverse recovery losses.
Furthermore, achieving ZVS operation for both switches
in turn off/on eliminates switching and capacitive turn-on
losses. The proposed converter also benefits from the common
ground between the input source and the load, continuous
input current, and a high gain ratio to components count. Ad-
ditionally, the proposed converter provide significant voltage
gain while imposing minimal voltage stress on the semicon-
ductors.
Based on experimental results, the switches demonstrated
full soft-switching performance across a broad output power
range, from light to full loads. Moreover, the diodes turned
off under ZCS conditions, validating theoretical predictions.
Besides the simple structure, all the mentioned features make
the proposed converter an excellent candidate for high step-up
TABLE 3. Loss Calculations applications.

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[12] A. Nafari and R. Beiranvand, “An extendable interleaved quasi Z-source REZA ASGARNIA received the B.Sc. degree in
high step-up DC-DC converter,” IEEE Trans. Power Electron., vol. 38, electrical engineering from the Isfahan University
no. 4, pp. 5065–5076, Apr. 2023. of Technology, Isfahan, Iran, in 2020, and the
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high step-up coupled-inductor boost converter,” IEEE Trans. Power Beheshti University, Tehran, Iran, in 2023. His
Electron., vol. 35, no. 1, pp. 535–545, Jan. 2020. research interests include the design and analysis
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han, Iran, in 1982. He received the B.S., M.S., and
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age multiplier cell techniques,” IEEE Trans. Ind. Electron., vol. 69,
Isfahan University of Technology, Isfahan, Iran, in
no. 1, pp. 323–335, Jan. 2022.
2003, 2006, and 2009, respectively. He is currently
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a Faculty Member with the Department of Electri-
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papers in journals and conference proceedings. His
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research interests include DC-DC converters and
converters with soft-switching capability and zero input current ripple,”
their applications, and soft-switching techniques.
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[20] M. Dezhbord, M. Babalou, P. Mohseni, M. R. Islam, L. E. Vafaei, and EBRAHIM AFJEI (Member, IEEE) received the
S. H. Hosseini, “An extendable soft-switched high step-up converter B.S. and M.S. degrees in electrical engineering
with near zero-ripple input current suitable for fuel cell-powered appli- from The University of Texas at Austin, Austin,
cations,” IET Renewable Power Gener., vol. 16, no. 15, pp. 3287–3298, TX, USA, in 1984 and 1986, respectively, and the
2022. Ph.D. degree in electrical engineering from New
[21] M. B. Meier, S. Avelino da Silva, A. A. Badin, E. F. R. Romaneli, Mexico State University, Las Cruces, NM, USA, in
and R. Gules, “Soft-switching high static gain DC-DC converter with- 1991. He is currently a Professor with the Depart-
out auxiliary switches,” IEEE Trans. Ind. Electron., vol. 65, no. 3, ment of Electrical Engineering, Shahid Beheshti
pp. 2335–2345, Mar. 2018. University, Tehran, Iran. His research interests in-
[22] L. Schmitz, D. C. Martins, and R. F. Coelho, “High step-up nonisolated clude switched reluctance motor drives and power
ZVS/ZCS DC-DC converter for photovoltaic thin-film module applica- electronics.
tions,” IEEE Trans. Emerg. Sel. Topics Power Electron., vol. 7, no. 1,
pp. 565–575, Mar. 2019.
[23] A. Kumar and P. Sensarma, “Ripple-free input current high voltage
gain DC-DC converters with coupled inductors,” IEEE Trans. Power
Electron., vol. 34, no. 4, pp. 3418–3428, Apr. 2019. HADI TARZAMNI (Student Member, IEEE) was
[24] S. Esmaeili, M. Shekari, M. Rasouli, S. Hasanpour, A. A. Khan, and born in Tabriz, Iran, in 1992. He received the
H. Hafezi, “High gain magnetically coupled single switch quadratic B.Sc. and M.Sc. degrees (Hons.) in power elec-
modified SEPIC DC-DC converter,” IEEE Trans. Ind. Appl., vol. 59, trical engineering from the Faculty of Electrical
no. 3, pp. 3593–3604, May/Jun. 2023. and Computer Engineering, University of Tabriz,
[25] S. Selvam, M. Sannasy, and M. Sridharan, “Analysis and design of Tabriz, Iran, in 2014 and 2016, respectively. He
two-switch enhanced gain SEPIC converter,” IEEE Trans. Ind. Appl., is currently working toward the dual Ph.D. degree
vol. 59, no. 3, pp. 3552–3561, May/Jun. 2023. program in power electronics engineering with the
[26] N. Elsayad, H. Moradisizkoohi, and O. Mohammed, “A new SEPIC- School of Electrical Engineering, Sharif University
based step-up DC-DC converter with wide conversion ratio for fuel of Technology, Tehran, Iran, and the Department
cell vehicles: Analysis and design,” IEEE Trans. Ind. Electron., vol. 68, of Electrical Engineering and Automation, Aalto
no. 8, pp. 6390–6400, Aug. 2021. University, Espoo, Finland. He has authored and coauthored more than 40
[27] S. A. Ansari and J. S. Moghani, “A novel high voltage gain noncoupled journal and conference papers. He also holds six patents in the area of
inductor SEPIC converter,” IEEE Trans. Ind. Electron., vol. 66, no. 9, power electronics. His research interests include power electronic converters
pp. 7099–7108, Sep. 2019. analysis and design, DC-DC and DC-AC converters, high step-up power
[28] F. I. Kravetz and R. Gules, “Soft-switching high static gain modified conversion, soft-switching and resonant converters, and reliability analysis.
SEPIC converter,” IEEE Trans. Emerg. Sel. Topics Power Electron., He was the recipient of the best paper award in 10th International Power
vol. 9, no. 6, pp. 6739–6747, Dec. 2021. Electronics, Drive Systems and Technologies Conference in 2019. He has
[29] S. Hasanpour, A. Baghramian, and H. Mojallali, “A modified SEPIC- been awarded a three-year Aalto ELEC Doctoral School grant, a Jenny and
based high step-up DC–DC converter with quasi-resonant operation for Antti Wihuri Foundation grant, two Walter Ahlström Foundation grants, an
renewable energy applications,” IEEE Trans. Ind. Electron., vol. 66, ABB Strömberg scholarship, and Finnish Foundation for Technology Promo-
no. 5, pp. 3539–3549, May 2019. tion grant in 2021 and 2024, respectively.

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