Digital Logic Circuits 1

C134: Computer Organisat

ion and Architecture

Unit 1-fundamentals of digital logic

and logic circuits

Dr. Anjaneyulu Pasala

Dr. Mohan Kumar S
Department of CSE(AI&ML)
MSRIT - Bangalore

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Digital Logic Circuits 2

Information in digital computers

• Information in digital computers is stored and proce
ssed by electronic networks called logic gates.
• Logic circuits operate on binary values called 0 and
1

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Digital Logic Circuits 3

LOGIC GATES
Digital Computers

- Imply that the computer deals with digital information, i.e., it deals
with the information that is represented by binary digits
- Why BINARY ? instead of Decimal or other number system ?

* Consider electronic signal

1 7
6
5 signal
4
3 range
2
0 1
0
binary octal

A logic gate is a device that performs a Boolean

function which is a logical operation performed
on one or more binary inputs that produces a
single binary output.
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Digital Logic Circuits 4

BASIC LOGIC GATE

Binary Binary
Digital Digital
. Gate Output
Input .
Signal . Signal

The logic gates are built using diodes or transistors acting as

electronic switches.

Today, MOSFETs (Metal-Oxide Semiconductor Field-Effect

Transistors)

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Digital Logic Circuits 5 Logic Gates

Logic Circuits
• A set of logic gates are cascaded to form a logic circuit such as
multiplexers, registers, arithmetic logic units (ALUs) and computer
memory. Of course microprocessor.

• Cascade of logic gates used in the construction of physical model

of all Boolean logic and therefore, all the algorithms and
mathematics.
Types of Basic Logic Blocks

- Combinational Logic Block

Logic Blocks whose output logic value
depends only on the input logic values

- Sequential Logic Block

Logic Blocks whose output logic value
depends on the input values and the
state (stored information) of the blocks

Functions of Gates can be described by

- Truth Table
- Boolean Function
- Karnaugh Map
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Digital Logic Circuits 6

COMBINATIONAL GATES
Name Symbol Function Truth Table
A B X
A X=A•B 0 0 0
AND X or 0
1
1
0
0
0
B X = AB
1 1 1
A B X
A 0 0 0
OR X X=A+B 0 1 1
B 1 0 1
1 1 1
A X
I A X X = A’ 0
1
1
0
A X
Buffer A X X=A 0 0
1 1
A B X
A 0 0 1
NAND X X = (AB)’ 0
1
1
0
1
1
B 1 1 0
A B X
A 0 0 1
NOR X X = (A + B)’ 0
1
1
0
0
0
B 1 1 0
A B X
A X=AB
XOR X or 0 0 0
Exclusive OR 0 1 1
B X = A’B + AB’ 1 0 1
1 1 0
A B X
A X = (A  B)’
XNOR X or
0
0
0
1
1
0
Exclusive NOR
or Equivalence B X = A’B’+ AB 1 0 0
1 1 1

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Digital Logic Circuits 7 Boolean Algebra

BOOLEAN ALGEBRA

Boolean Algebra

* Algebra with Binary(Boolean) Variable and Logic Operations

* Boolean Algebra is useful in Analysis and Synthesis of
Digital Logic Circuits

- Input and Output signals can be

represented by Boolean Variables, and
- Function of the Digital Logic Circuits can be represented by
Logic Operations, i.e., Boolean Function(s)
- From a Boolean function, a logic diagram
can be constructed using AND, OR, and I

Truth Table

* The most elementary specification of the function of a Digital Logic

Circuit is the Truth Table

- Table that describes the Output Values for all the combinations
of the Input Values, called MINTERMS
- n input variables → 2n minterms

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Digital Logic Circuits 8 Boolean Algebra

LOGIC CIRCUIT DESIGN

x y z F
0 0 0 0
Truth 0 0 1 1
Table 0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Boolean F = x + y’z
Function

x
F
Logic y
Diagram
z

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Digital Logic Circuits 9 Boolean Algebra

BASIC IDENTITIES OF BOOLEAN ALGEBRA

[1] x + 0 = x [2] x • 0 = 0
[3] x + 1 = 1 [4] x • 1 = x
[5] x + x = x [6] x • x = x
[7] x + x’ = 1 [8] x • X’ = 0
[9] x + y = y + x [10] xy = yx
[11] x + (y + z) = (x + y) + z [12] x(yz) = (xy)z
[13] x(y + z) = xy +xz [14] x + yz = (x + y)(x + z)
[15] (x + y)’ = x’y’ [16] (xy)’ = x’ + y’
[17] (x’)’ = x
[15] and [16] : De Morgan’s Theorem
Usefulness of this Table
- Simplification of the Boolean function
- Derivation of equivalent Boolean functions
to obtain logic diagrams utilizing different logic gates
-- Ordinarily ANDs, ORs, and Inverters
-- But a certain different form of Boolean function may be convenient
to obtain circuits with NANDs or NORs
→ Applications of De Morgans Theorem

x’y’ = (x + y)’ x’+ y’= (xy)’

I, AND → NOR I, OR → NAND

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Digital Logic Circuits 10 Boolean Algebra

EQUIVALENT CIRCUITS

Many different logic diagrams are possible for a given Function

F = ABC + ABC’ + A’C .......…… (1)
= AB(C + C’) + A’C [13] ..…. (2)
= AB • 1 + A’C [7]
= AB + A’C [4] ...…. (3)
A
B
(1) C
F

(2) A
B

C F

(3) A
B
F
C

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Digital Logic Circuits 11 Boolean Algebra
COMPLEMENT OF FUNCTIONS
A Boolean function of a digital logic circuit is represented by only using
logical variables and AND, OR, and Invert operators.

→ Complement of a Boolean function

- Replace all the variables and subexpressions in the parentheses

appearing in the function expression with their respective complements

A,B,...,Z,a,b,...,z  A’,B’,...,Z’,a’,b’,...,z’
(p + q)  (p + q)’

- Replace all the operators with their respective

complementary operators

AND  OR
OR  AND

- Basically, extensive applications of the De Morgan’s theorem

(x1 + x2 + ... + xn )’  x1’x2’... xn’

(x1x2 ... xn)'  x1' + x2' +...+ xn'

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Digital Logic Circuits 12 Map Simplification

SIMPLIFICATION

Truth Boolean
Table Function
Unique Many different expressions exist
Simplification from Boolean function

- Finding an equivalent expression that is least expensive to implement

- For a simple function, it is possible to obtain
a simple expression for low cost implementation
- But, with complex functions, it is a very difficult task

Karnaugh Map (K-map) is a simple procedure for

simplifying Boolean expressions.

Truth
Table
Simplified
Karnaugh Boolean
Map Function
Boolean
function

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Digital Logic Circuits 13 Map Simplification

KARNAUGH MAP

Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products

form of Boolean Function, or Truth Table) is
- Rectangle divided into 2n cells
- Each cell is associated with a Minterm
- An output(function) value for each input value associated with a
mintern is written in the cell representing the minterm
→ 1-cell, 0-cell

Each Minterm is identified by a decimal number whose binary representation

is identical to the binary interpretation of the input values of the minterm.
Karnaugh Map
x Identification x value
x
0
F
1 0 0 of the cell 0 0 of F

1 0 1 1 1 1
F(x) = (1)
1-cell
x y F
x0 1
0 0 0
y x0 1
0 1 1
0 0 1 y
0 0 1
1 0 1 1 2 3
1 1 1 1 1 0
F(x,y) =  (1,2)
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Digital Logic Circuits 14 Map Simplification

KARNAUGH MAP
Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products
form of Boolean Function, or Truth Table) is
- Rectangle divided into 2n cells
- Each cell is associated with a Minterm
- An output(function) value for each input value associated with a
mintern is written in the cell representing the minterm
→ 1-cell, 0-cell

Each Minterm is identified by a decimal number whose binary representation

is identical to the binary interpretation of the input values of the minterm.
Karnaugh Map
x Identification x value
x
0
F
1 0 0 of the cell 0 0 of F

1 0 1 1 1 1
F(x) = (1)
1-cell
x y F
x0 1
0 0 0
y x0 1
0 1 1
0 0 1 y
0 0 1
1 0 1 1 2 3
1 1 1 1 1 0
F(x,y) =  (1,2)
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Digital Logic Circuits 15 Map Simplification

KARNAUGH MAP
x y z F
0 0 0 0
yz y yz
0 0 1 1
0 1 0 1 x 00 01 11 10 x 00 01 11 10
0 1 1 0 0 0 1 3 2 0 0 1 0 1
1 0 0 1 x 1 4 5 7 6
1 0 1 0 1 1 0 0 0
1 1 0 0 z
1 1 1 0 F(x,y,z) =  (1,2,4)

wx w
u v w x F
0 0 0 0 0 uv 00 01 11 10
0 0 0 1 1 00 0 1 3 2 v
0 0 1 0 0
0 0 1 1 1 01 4 5 7 6
0 1 0 0 0
u 11
12 13 15 14
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0 10 8 9 11 10
1
1
0
0
0
0
0
1
1
1
x
1 0 1 0 0 wx
1 0 1 1 1 uv 00 01 11 10
1 1 0 0 0 00 0 1 1 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0 01 0 0 0 1
11 0 0 0 1
10 1 1 1 0
F(u,v,w,x) =  (1,3,6,8,9,11,14)
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Digital Logic Circuits 16 Map Simplification

MAP SIMPLIFICATION - 2 ADJACENT CELLS -

Rule: xy’ +xy = x(y+y’) = x

Adjacent cells

- binary identifications are different in one bit

→ minterms associated with the adjacent
cells have one variable complemented each other

Cells (1,0) and (1,1) are adjacent

Minterms for (1,0) and (1,1) are
x • y’ --> x=1, y=0
x • y --> x=1, y=1

F = xy’+ xy can be reduced to F = x

From the map y
x 0 1
0 0 0 2 adjacent cells xy’ and xy
1 1 1 → merge them to a larger cell x

F(x,y) =  (2,3)
= xy’+ xy
=x

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Digital Logic Circuits 17 Map Simplification

MAP SIMPLIFICATION - MORE THAN 2 CELLS -

wx u’v’ wx u’x’
u’v’w’x’ + u’v’w’x + u’v’wx + u’v’wx’ w w
= u’v’w’(x’+x) + u’v’w(x+x’) uv uv
= u’v’w’ + u’v’w 1 1 1 1 1 1 1 1
= u’v’(w’+w) vw’ 1 1 1 1
v v
= u’v’ 1 1 1 1
u u
1 1 1 1
uw x
x v’x

u’v’w’x’+u’v’w’x+u’vw’x’+u’vw’x+uvw’x’+uvw’x+uv’w’x’+uv’w’x
= u’v’w’(x’+x) + u’vw’(x’+x) + uvw’(x’+x) + uv’w’(x’+x)
= u’(v’+v)w’ + u(v’+v)w’
= (u’+u)w’ = w’
wx
uv w uv w V’
1 1 1 1 1 1
w’
1 1
v v
1 1
u u 1 1 1 1 u
1 1 1 1 1 1
x x

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Digital Logic Circuits 18 Map Simplification

MAP SIMPLIFICATION
wx
uv 00 01 11 10 w
00 1 1 0 1 1 1 0 1
01 0 0 0 0 0 0 0 0
v
11 0 1 1 0 0 1 1 0
10 0 1 0 0 u
0 1 0 0
x
F(u,v,w,x) =  (0,1,2,9,13,15)
(0,1), (0,2), (0,4), (0,8) Merge (0,1) and (0,2)
Adjacent Cells of 1 --> u’v’w’ + u’v’x’
Adjacent Cells of 0 Merge (1,9)
(1,0), (1,3), (1,5), (1,9) --> v’w’x
... Merge (9,13)
... --> uw’x
Adjacent Cells of 15 Merge (13,15)
(15,7), (15,11), (15,13), (15,14) --> uvx

F = u’v’w’ + u’v’x’ + v’w’x + uw’x + uvx

But (9,13) is covered by (1,9) and (13,15)
F = u’v’w’ + u’v’x’ + v’w’x + uvx

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Digital Logic Circuits 19 Map Simplification

IMPLEMENTATION OF K-MAPS - Sum-of-Products Form -

Logic function represented by a Karnaugh map

can be implemented in the form of I-AND-OR

A cell or a collection of the adjacent 1-cells can

be realized by an AND gate, with some inversion of the input variables.
y
x’
1 y
x’ 1 z’
y’ x’
z’ x 1  y
x z’ 1 1
z y z’
z’ 1
F(x,y,z) =  (0,2,6)

x’
y’ x
z’
x’  z
y F F
z’ y
x
y z
z’
I AND OR

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Digital Logic Circuits 20 Map Simplification

IMPLEMENTATION OF K-MAPS - Product-of-Sums Form -

Logic function represented by a Karnaugh map

can be implemented in the form of I-OR-AND

If we implement a Karnaugh map using 0-cells,

the complement of F, i.e., F’, can be obtained.
Thus, by complementing F’ using DeMorgan’s
theorem F can be obtained

F(x,y,z) = (0,2,6) y
F’ = xy’ + z
1 0 0 1 z
x 0 0 0 1 F = (xy’)z’
= (x’ + y)z’
x z
y’

x
y
F
z

I OR AND

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Digital Logic Circuits 21 Map Simplification
IMPLEMENTATION OF K-MAPS
- Don’t-Care Conditions -
In some logic circuits, the output responses
for some input conditions are don’t care
whether they are 1 or 0.

In K-maps, don’t-care conditions are represented

by d’s in the corresponding cells.

Don’t-care conditions are useful in minimizing

the logic functions using K-map.
- Can be considered either 1 or 0
- Thus increases the chances of merging cells into the larger cells
--> Reduce the number of variables in the product terms
y x’
1 d d 1
x d 1
z yz’

x
F
y
z
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Digital Logic Circuits 22 Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

y y
Half Adder x y c s x
0 0 0 0 0 0 0 1 c
y
0 1 0 1 x 0 1 x 1 0
1 0 0 1 c = xy s = xy’ + x’y s
1 1 1 0 =x  y
Full Adder
y y
x y cn-1 cn s
0 0 0 0 0 0 0 0 1
0 0 1 0 1 0 1 c 1 0 c
n-1 n-1
0 1 0 0 1 x 1 1 x 0 1
0 1 1 1 0 0 1 1 0
1 0 0 0 1 cn s
1 0 1 1 0
1 1 0 1 0 cn = xy + xcn-1+ ycn-1
1 1 1 1 1 = xy + (x  y)cn-1
s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
= x  y  cn-1 = (x  y)  cn-1
x
y S
cn-1
cn

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Digital Logic Circuits 23 Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

Other Combinational Circuits

Multiplexer
Encoder
Decoder
Parity Checker
Parity Generator
etc

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Digital Logic Circuits 24

To establish a correspondence between

voltage and logic values or states,
a concept called threshold is used.

In practical situations, the voltage at any

point in an electronic circuit undergoes small
random variations for variety of reasons.
It is called noise

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Digital Logic Circuits 25

Not Gate

S -Close V-out = 0
S - Open V-out =1

Vin Switch(T) V out

0(0) Open Vsupply 1
Vsupply(1) Close 0 0

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Digital Logic Circuits 26

NOR Gate

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Digital Logic Circuits 27

NAND Gate

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Digital Logic Circuits 28

CMOS Circuits

Metal-Oxide Semiconductor (MOS) transistors

• Two types of CMOS transistors – NMOS and PMOS

• NMOS uses n-channel transistor and
PMOS uses p-channel transistor
• The naming convention is due to the type of current flows
through these transistors.

CMOS – Complementary MOS

Both T1 and T2 operate in complementary

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Digital Logic Circuits 29

CMOS Circuits

• The key feature of CMOS circuits is that transistors T1 a

nd T2 operate in complementary fashion;
– when one is on, the other is off. Hence there is always a closed path f
rom the output point f to either Vsupply or ground.
– There is no closed path between Vsupply and ground at any point of ti
me except during transition period when the transistors are changing t
heir states.
– This means that the circuit does not dissipate appreciable power when
it is in a steady state.
– It dissipates power only when it is switching from one logic to another.
– Therefore, power dissipation in this circuit is dependent on the rate at
which state changes take place.

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Digital Logic Circuits 30

CMOS NAND and NOR gates

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Digital Logic Circuits 31

Voltage transfer characteristic for the CMOS inverter

Vt is a threshold voltage

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Digital Logic Circuits 32

Propagation delay and transition time

• Logic circuits do not switch instantaneously from one state to another
• When a state change takes place at the input, a delay is encountered before th
e corresponding change at the output. This is called a propagation delay..
• Another important parameter is transition time, which is normally measured bet
ween the 10% and 90% points of the signal swing.

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Digital Logic Circuits 33

Fan-in and Fan-out constraints

• Fan-in is the number of inputs that a logic gate can handle.
– For example, if a logic gate can take 2 inputs, its fan-in is 2. Larg
er fan_in means that the gate can accept more signals as inputs.
– Fan-in determines how complex the gate can be in terms of proce
ssing multiple inputs.
• Fan-out: This is the number of outputs a logic gate can drive or feed i
nto. In other words, it refers to how many subsequent gates can be co
nnected to the output of a given gate.
– A high fan-out means that the output of the gate can be connecte
d to more gates without signal degradation.
– Fan-out is critical because exceeding a gate's fan-out capacity ca
n result in signal integrity issues, such as slower signal propagatio
n or weakened signals.
• Each transistor is a CMOS gate contributes a certain amount of capaci
tance. As the capacitance increases, the circuit becomes slower and it
s signal levels and noise levels become worse.
• Cascading is the solution for larger fan-in and using more gates is sol
ution for larger fan-out.

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Digital Logic Circuits 34

IC Circuits

Small scale integrated circuits

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Digital Logic Circuits 35

Flip-flops
• Flip-flops are fundamental building blocks in digital electronic circuits, prim
arily used for storing and transferring binary data (1s and 0s). They are a typ
e of bistable multivibrator, which means they have two stable states: they ca
n store either a "0" or a "1.
• The circuit can "flip" from one state (0) to another (1) and "flop" back to the
original state. This alternating between two stable states when triggered by
a clock or input signal gives rise to the term "flip-flop."

0-State 1-State

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Digital Logic Circuits 36 Flip Flops

SR FLIP- FLOP
In order to be used in the computer circuits, state of the flip flop should have input terminals and
output terminals so that it can be set to a certain state, and its state can be read externally.

If S is set to 1 with R equal to 0, Q and Q’ will become 1 and 0 respectively, and remain in this state
after S is returned to 0. Hence, this circuit constitutes a memory element. Or a latch.
Q is considered as output and Q’ is not used in practice. S and R are called set and reset.

R S R Q(t+1)
Q 0 0 Q(t)
0 1 0
1 0 1
S Q’ 1 1 indeterminate
Basic Latch
(forbidden) implemented with
NOR gates

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Digital Logic Circuits 37 Flip Flops

Gated SR FLIP- FLOP

Many applications require that the time at which a latch is set or reset be controlled from an input other
than R and S. This input is termed a clock input. The circuit is called a gated latch.
• When the clk is equal to 1, points S’ and R’ follow the inputs S and R respectively.
• On the other hand, when clk = 0, the S’ and R’ points are equal to 0 and no change in the state
of the latch can take place.

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Digital Logic Circuits 38 Flip Flops

D-LATCH

D-Latch
Forbidden input values are forced not to occur
by using an inverter between the inputs

D Q
D Q(t+1)
0 0
1 1 Cl Q’

• D flip-flop samples the D input at the time the clock is high and stores the
information until subsequent clock pulse arrives

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Digital Logic Circuits 39 Flip Flops

RS-LATCH WITH PRESET AND CLEAR INPUTS

P(preset)
R Q
c
(clock)
S Q’

clr(clear)

S P Q S P Q
c c
R clr Q’ R clr Q’

S P Q S P Q
c c
R clr Q’ R clr Q’

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Digital Logic Circuits 40 Flip Flops

EDGE-TRIGGERED FLIP FLOPS

Characteristics
- State transition occurs at the rising edge or
falling edge of the clock pulse

Latches

respond to the input only during these periods

Edge-triggered Flip Flops (positive)

respond to the input only at this time

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Digital Logic Circuits 41

Master Slave Flip-flops

• In previously studied flip-flops, we assume that while clk=1, S and R do not change. However, the
outputs will respond immediately to any change in S or R input during time.
• Similarly, for D latch Q=D while clk =1.
• In such circuits, immediate propagation of logic conditions from inputs (S,R and D) to the latch
outputs may lead to incorrect operations.
• This is undesirable for counters and shift-registers.

• Two gated latches can be connected to form the master-slave organization eliminates this problem.
• The first, the master is connected to the inputs and its output is connected to slave. When Clock =1, a
1to0 transition of the clock isolates the master from the input and transfers the contents of the master
stage to the slave stage.
• The function of the slave is to hold the value at the output of the flipflop while master stage is being
set up to the next state value determined by the input.
• The new state is transferred from master to the slave after the 1 to 0 transition on Clock.
• At this stage the master is isolated from the inputs so that further changes in the latch input will not
affect this transfer.

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Digital Logic Circuits 42

Negative edge triggered D flip flop

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Digital Logic Circuits 43

T Flip-flop

Changes its state every clock cycle.

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Digital Logic Circuits 44

JK Flip-flop
• JK flip-flop combines the behavior of SR and T flip-flops
• The first 3 entries in the truth table defines the same behavior as SR flip-flop
• When J=K=1, the next state is defined as the complement of the present state of the flip-flop. i.e.
when J=K=1 the flip-flop toggles, reversing its present state.
• JK flip-flop is versatile, it can be used to store data like RS flip-flop. It can also be used to built
counters and shift registers, because it behaves like T flip-flop when its inputs are connected
together.

• JK flip-flop can be implemented using two D flip-flops

connected as D = JQ’ + J’Q = JQ’ AND J’Q

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Digital Logic Circuits 45

Registers and Shift Registers

• Individual flip-flops can be used to store one bit.
• In machines in which data stored are handled in words consisting of many bits (2,4,8,16,32,64 etc.
• It is convenient to arrange a number of flip-flops into a common structure called register.
• The data are written (loaded) into or read from al flip-flops of a register at a same time, hence, the
operation of all flip-flops in a register is synchronized by a common clock.
• Processing of digital data often requires the capability to (1) shift and (2) rotate the data.
• A simple mechanism for realizing both these operations is a register whose contents may be
shifted to the right or left one bit position at a time
• It is called a shift register

A simple shift register

• It consists of D flip-flops connected so that each clock pulse will cause the transfer of the
state of Fi to Fi+1, effecting a “right Shift”.
• Data is shifted serially into and out of the register
• The rotation of the data can be implemented by connecting Out to In

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Digital Logic Circuits 46

Parallel/Serial Shift register

• Shift register operations require that its contents be shifted exactly one position for each
clock pulse.
• D flip-flops and gated flip-flops, the D input quickly propagates to the output. It will continue
to propagate across all flip-flops.
• There is no control over the number of shifts that will take place during a single clock pulse.
The number of shifts depends on the propagation delays and duration of the clock pulse
• Hence the solution is use either master-slave or edge triggered flip-flops
• One useful form of shift register is one that can be loaded and read parallel, called parallel
shift register which can be accomplished with some additional gating.

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Digital Logic Circuits 47

Parallel/Serial Shift register

• . Here is a 4 bit register constructed with D flip-flops.
• It can be loaded either serially or in parallel
• When register is clacked, a shift takes place if shift’/Load=0:
• Otherwise, a parallel load is performed.

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Digital Logic Circuits 48

Counters
• Another application of flip-flops is implementation of counter circuits
• Counters are also used to generate control and timing signals.
• A 3 bit counter with T flip-flops is shown here
• When T input is 1, the flip-
flop toggles, i.e. for each
successive pulse Q0 to
change from 1 state to 0
state and back to 1 state.
• i.e. the output waveform of
Q0 has half frequency of
the clock.
• Q1 has the half frequency
of Q0, Similarly, Q2 has
half frequency of Q1
• Hence it is also called a
ripple counter, because
the effect of an input clock
pulse ripples through the
counter.

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Digital Logic Circuits 49 Combinational Logic Circuits

ENCODER/DECODER

Octal-to-Binary Encoder
D1 A0
D2
D3 A1
D4
D5 A2
D6
D7

2-to-4 Decoder
D0

E A1 A0 D0 D1 D2 D3 A0 D1
0 0 0 0 1 1 1
0 0 1 1 0 1 1 D2
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 d d 1 1 1 1 A1 D3
E

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Digital Logic Circuits 50

Decoders

A decoder driving 7 segment display

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Digital Logic Circuits 51 Combinational Logic Circuits

MULTIPLEXER

4-to-1 Multiplexer
Select Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

I0

I1
Y
I2

I3

S0
S1

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Digital Logic Circuits 52

Sequential Circuits

• A combinational circuit is the one whose output is determined entirely by its present inputs.
• Examples: Multiplexers and decoders
• Sequential circuits output depends on both the present inputs and on the sequence of previous
inputs.

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Digital Logic Circuits 53 Flip Flops

CLOCK PERIOD
Clock period determines how fast the digital circuit operates.
How can we determine the clock period ?

Usually, digital circuits are sequential circuits which has some flip flops

FF FF ... FF
C
Combinational .
.
. Logic .
. Circuit .

Combinational
FF Logic FF
Circuit
FF Setup Time
FF Delay Combinational logic Delay FF Hold Time
td
ts,th
clock period T = td + ts + th
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Digital Logic Circuits 54 Sequential Circuits

DESIGN EXAMPLE
Design Procedure:
Specification  State Diagram  State Table 
Excitation Table  Karnaugh Map  Circuit Diagram
Example: 2-bit Counter -> 2 FF's
x=0 current next
state input state FF inputs
00 A B x A B Ja Ka Jb Kb
x=1 x=1 0 0 0 0 0 0 d 0 d
0 0 1 0 1 0 d 1 d
x=0 01 11 x=0 0 1 0 0 1 0 d d 0
0 1 1 1 0 1 d d 1
x=1 1 0 0 1 0 d 0 0 d
x=1 1 0 1 1 1 d 0 1 d
10 1 1 0 1 1 d 0 d 0
x=0 1 1 1 0 0 d 1 d 1

B B B B
d d d d
1 d d x 1 d x d 1 x
x x
d d 1
A A A 1 d A
d 1 J Q A J Q B
d d d d C C
Ja Ka Jb Kb K Q' K Q'
clock
Ja = Bx Ka = Bx Jb = x Kb = x

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Digital Logic Circuits 55 Sequential Circuits

SEQUENTIAL CIRCUITS - Registers

A0 A1 A2 A3
Q Q Q Q
D C D C D C D C

Clock
I0 I1 I2 I3
Shift Registers
Serial Serial
D Q D Q D Q D Q Output
Input C C C C
Clock

Bidirectional Shift Register with Parallel Load

A0 A1 A2 A3

Q Q Q Q
D C D C D C D C

4x1 4x1 4x1 4x1

MUX MUX MUX MUX

Clock S0S1 SeriaI I0 I1 I2 Serial I3

Input Input
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Digital Logic Circuits 56 Sequential Circuits

SEQUENTIUAL CIRCUITS - Counters

A0 A1 A2 A3

Q Q Q Q
J K J K J K J K
Clock

Counter
Enable

Output
Carry

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Digital Logic Circuits 57 Memory Components

MEMORY COMPONENTS
0
Logical Organization

words
(byte, or n bytes)

N-1
Random Access Memory

- Each word has a unique address

- Access to a word requires the same time
independent of the location of the word
- Organization
n data input lines

k address lines
2k Words
Read (n bits/word)

Write

n data output lines

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Digital Logic Circuits 58 Memory Components

READ ONLY MEMORY(ROM)

Characteristics
- Perform read operation only, write operation is not possible
- Information stored in a ROM is made permanent
during production, and cannot be changed
- Organization k address input lines

m x n ROM
(m=2k)

n data output lines

Information on the data output line depends only
on the information on the address input lines.
--> Combinational Logic Circuit address Output
X0=A’B’ + B’C ABC X0 X1 X2 X3 X4
X1=A’B’C + A’BC’ 000 1 0 0 0 0
X2=BC + AB’C’
X3=A’BC’ + AB’
001 1 1 0 0 0
X4=AB 010 0 1 0 1 0
011 0 0 1 0 0
X0=A’B’C’ + A’B’C + AB’C 100 0 0 1 1 0
X1=A’B’C + A’BC’ 101 1 0 0 1 0
X2=A’BC + AB’C’ + ABC 110 0 0 0 0 1
Canonical minterms X3=A’BC’ + AB’C’ + AB’C 111 0 0 1 0 1
X4=ABC’ + ABC
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Digital Logic Circuits 59 Memory Components

TYPES OF ROM

ROM
- Store information (function) during production
- Mask is used in the production process
- Unalterable
- Low cost for large quantity production --> used in the final products

PROM (Programmable ROM)

- Store info electrically using PROM programmer at the user’s site
- Unalterable
- Higher cost than ROM -> used in the system development phase
-> Can be used in small quantity system

EPROM (Erasable PROM)

- Store info electrically using PROM programmer at the user’s site
- Stored info is erasable (alterable) using UV light (electrically in
some devices) and rewriteable
- Higher cost than PROM but reusable --> used in the system
development phase. Not used in the system production
due to eras ability

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Digital Logic Circuits 60 Memory Components

INTEGRATED CIRCUITS

Classification by the Circuit Density

SSI - several (less than 10) independent gates
MSI - 10 to 200 gates; Perform elementary digital functions;
Decoder, adder, register, parity checker, etc
LSI - 200 to few thousand gates; Digital subsystem
Processor, memory, etc
VLSI - Thousands of gates; Digital system
Microprocessor, memory module
Classification by Technology
TTL - Transistor-Transistor Logic
Bipolar transistors
NAND
ECL - Emitter-coupled Logic
Bipolar transistor
NOR
MOS - Metal-Oxide Semiconductor
Unipolar transistor
High density
CMOS - Complementary MOS
Low power consumption

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