A D-band CMOS Power Amplifier for

Wireless Chip-to-Chip Communications with

22.3 dB Gain and 12.2 dBm P1dB in 65-nm CMOS Technology
H. S. Son, C. J. Lee, D. M. Kang, T. H. Jang, H. S. Lee, S. H. Kim, C. W. Byeon* and C. S. Park
School of Electrical Engineering, Korea Advanced Institute of Science and Technology,
Daejeon 34141, Republic of Korea
*
Department of Electronic Engineering, Wonkwang University, Iksan, 54538, Republic of Korea

Abstract — This paper presents a D-band linearized dependent on the layout structure including the extrinsic
power amplifier (PA) with on-chip current combining parasitic and passive components. Thus, the gain and
transformer using a standard 65nm CMOS process, which bandwidth performance is significantly reduced in the
covers 114 to 131 GHz. To mitigate the parasitic gate-drain
capacitance feedback, each stage consists of common source sub-THz. Another drawback of the CMOS process is that
(CS) amplifier with a neutralization using cross-coupled low supply and breakdown voltages of the MOS transistor
capacitor (Cc). The PA achieves a small-signal gain of 22.3 restrict the delivery output power. To overcome these
dB and 3-dB bandwidth (BW) of 17 GHz, a 1-dB compressed problems, a capacitive neutralization [4] have been
power (P1dB) of 12.2 dBm and a saturated output power
(PSAT) of 14.5 dBm with a peak PAE of 10.2%. The PA chip
employed to enhance the gain performance. The current-
area is 0.343mm2 including the pads and the core chip area is combining transformer [5] and direct combining [8] is
0.103mm2. used to improve the limited output power.
Index Terms — CMOS, D-band, linearization, neutraliza- In this paper, we demonstrate a high gain, a high output
tion, saturated output power, PAE, power amplifier. power and a wide bandwidth PA for wireless chip-to-chip
communication. The current combining transformer is
implemented to enhance the output power. Also, a cross-
I. INTRODUCTION
coupled capacitor (Cc) is employed to enhance the gain
Recently, the increasing demand for high data rates in and to mitigate feedback effect. To enhance the output
wireless communication systems according to consumer 1dB compression point (P1dB), the linearization using a
requirements has led to extensive research into the diode connected transistor is employed. Section II
millimeter wave (mm-Wave) capable of supporting high presents a D-band PA circuit design. Measurement results
data rates [1]-[2]. To realize higher data rate wireless and conclusion are given in Section III and IV,
communication beyond several tens of Gbps, high order respectively.
modulation schemes should be applied to wireless
communication systems. Alternatively, the sub-THz II. POWER AMPLIFIER DESIGN
system, which has a wide bandwidth characteristic can Fig. 1(a) presents the proposed D-band CMOS PA
achieve multi Gbps communication to satisfy the demand. schematic. The PA consists of three drive-stages for gain,
Systems operating at over 100 GHz and even in the THz one power stage for output power. A Cc for reducing
range are emerging, such as for very short-range wireless feedback effect is employed at each stage. Also, the diode
communication and chip-to-chip communication reaching linearization is employed at the power stage for
the level of 10 Gbps and beyond [3]. improvement the linearity. The each stage is composed of
In sub-THz system, power amplifiers (PAs) are a differential common source (CS) amplifier, which is
considered to be most challenging blocks on account of connected by a matching network using an on-chip
requirement of a high gain, output power and linearity as transformer. The current combining at the power stage is
well as wide bandwidth. The CMOS process that has employed for high output power, and has some
advantages of high integration and low cost, can be advantages compared to the voltage combining. Firstly,
pushed the operating frequency of the RF circuits towards the current handling capability requirement of secondary
sub-THz due to scaling down. Despite the advantage of coil in the current combining is lower than that of the
the CMOS process, implementation of the sub-THz PA is voltage combining because high current of secondary coil
challenging because of the limitation of the CMOS device results in high sensitivity to parasitic resistance. Secondly,
speed. And the performance of the actual device is highly the channel symmetry structure of the current combining

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 RF OUT ‫ڢ‬ ‫ڮ‬ ‫ڢ‬ 20
TF4 w/ Cc with PEX & EM
w/o Cc with PEX & EM
15 w/o Cc with ideal Tr.
GND
‫ڟڟڱ‬ TF4 ‫ڟڟڱ‬

Gmax (dB)
10
CC4 CC4

Vgs_Diode Vgs_Diode 5
Current combining transformer
Size: 1.2um x 40
0
Power stage

VDD TF3 VDD -5

50 100 150 200 250 300
CC3 CC3
Frequency (GHz)
Fig. 2. The simulated Gmax of the differential CS amplifier.
Vgs Vgs
Size: 0.8um x 40
Drive stage3 parasitic gate-to-drain capacitance (Cgd), which depends
VDD TF2 VDD
highly on frequency. This feedback leads to deteriorative
the stability and the gain, results in poor reverse isolation
CC2 CC2
between input and output of the PA [3]. To solve this
Vgs Vgs
problem which arises from parasitic Cgd, a Cc between the
Size: 0.8um x 20 0.5mm gate and the drain of the opposite side transistor in each
Drive stage2
stage is employed, as shown in Fig. 1(a). A Cc, which
VDD TF1 VDD works as a negative capacitor, cancels the feedback
CC1 CC1 generated from the parasitic Cgd. The simulated MAG of
the CS amplifier, which has a width of 48- m, is plotted in
0.49mm

0.66mm

Vgs Vgs Fig. 2. This result is obtained by using parasitic extraction

Size: 0.8um x 20
Drive stage1 tools and full EM simulation. The stability breakpoint
0.19mm between conditional and absolute stability for the CS
‫ڢ‬ ‫ڮ‬ ‫ڢ‬ amplifier without Cc is approximately 153GHz. At
RF IN
120GHz, the MAG of the CS amplifier with Cc provides
(a) (b) 8.5 dB gain. It is 1.5dB higher than that without Cc. Also,
Fig. 1. (a) Schematic of the proposed D-band CMOS PA and (b) unconditionally stable region of the CS amplifier with Cc
Chip photograph of the implemented PA. is from 90 GHz. Therefore, stability and reverse isolation
of the PA are simultaneously achieved with placing Ccs at
alleviates the deterioration of the transformer from each stage. Also, neutralization using a Cc increases the
amplitude and phase mis-matches [5]. A current combiner gain with no penalty in power consumption. The
transformer using the top metal and second metal layer for determined Cc value for unconditionally stable satisfies
the primary and secondary inductors, respectively, is the stability factor K>1, | |<1 of S-parameter. In addition,
designed as shown in Fig. 1(a). The line width and Cc value should be smaller than the parasitic Cgd of the
diameter of the output transformer are 4-ȝm and 27-ȝm, transistor, otherwise it can lead to oscillation. The selected
respectively, in order to optimize power matching cross-coupled capacitance of each stage is 5.8/12/13 fF for
impedance. Due to the large impedance difference CC1=CC2/CC3/CC4, respectively. In addition, a large signal
between the output impedance of the previous stage and analysis will be discussed later in the conference.
the input impedance of the later stage, an extra matching
network that consists of inductor line is supplemented at
TF1 and TF2 to obtain large impedance transform ratio. In III. MEASUREMENT RESULTS
matching networks, capacitors are not employed due to The proposed sub-THz four-stage PA with on-chip
low self-resonant-frequency. Also, the gain compression current combining transformer has been fabricated using a
is caused by the gate bias voltage drop as the input power 65-nm CMOS process. Fig. 1(b) shows a micro-
increase [6]. Thus, in order to improve the P1dB, a diode photograph of the PA, which occupies a total area of 0.66
connected linearization, which compensates for the gate μ0.52 mm2 and a core area of 0.49μ0.21 mm2. The S-
bias voltage deterioration as the input power increases is parameter measurement results were obtained from 110 to
employed at the power stage. By using the linearization, 170 GHz using a Millimeter-Wave Network Analyzer
the P1dB of simulation result is 0.8 dB higher than that of (base in PNA and frequency multiplier) and on-wafer
conventional bias structure. probing with WR-06 probe. Calibration was performed
In sub-THz systems, the CMOS PA design has another with a CS-5 calibration kit. The S-parameter measurement
problem that is low reverse isolation due to the high set-up is shown in Fig. 3(a). The PA is biased with

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 VDD=1.2 V, Vgs=0.75 V and Vgs_Diode=0.8 V. Fig. 4 TABLE I
demonstrates the simulated and measured S-parameters of COMPARISON WITH STATE-OF-THE-ART OF THE CMOS PAS
this PA. The peak gain of the PA was 22.3 dB at 119 GHz Reference [4] [7] [8] This Work
and a gain of more than 19.3 dB from 114 to 131 GHz Tech. 65nm 40nm 65nm 65nm
freq [GHz] 101-117 127-140 120-150 114-131
31$;
Fc [GHz] 108 133 135 118
Frequency Signal Power
3dB BW
Tripler generator Meter
16 13 30 17
WR-06
WR-06
[GHz]
probe
D-band probe
Commercial
Power
Sensor
Gain [dB] 14.1 15 15 22.3
RF input DUT RF output PA DUT
RF input RF output
port port port port PSAT/P1dB
WR-06 waveguides WR-06 waveguides 14.8/11.6 8.6/6.8 13.2/9.9 14.5/12.2
[dBm]
(a) (b) PAE [%] 9.4 7.4 14.6 10.2
Fig. 3. Measurement set-ups for the S-parameter (a) and large- 0.322 /
2
signal (b). Size [mm ] 0.3 0.38 0.34 / 0.103*
0.106*
FoM** 79.2 76.6 82.5 88.3
20 * Core only
** FoM=Psat[dBm]+Gain[dB]+20log(fc[GHz])+10log(PAEmax[%])
10
S-parameter (dB)

0 shown in Fig. 5(a). Psat and P1dB are better than 12.5 dBm
-10
and 9.13 dBm, respectively. The measured gain and PAE
versus output power of the PA at 118 GHz are plotted in
-20
S11 Fig. 5(b). The OP1dB of the PA is about 12.2 dBm. A
Hollow - simulation S21
-30
Filled - mearsurement
summary of the performance and comparison with state-
S22
110 120 130 140 150
of-the-art PAs in W-band and D-band frequencies is
Frequency (GHz) shown in Table I. Finally, the proposed PA achieves the
Fig. 4. Simulated and measured results of the PA S-parameters highest gain and figure of merit (FoM) among the
from 110-150GHz. published W-band and D-band CMOS PAs.

20 20 25 12

10 IV. CONCLUSION
Psat & P1dB (dBm)

15 15 20
8

A 114 to 131 GHz D-band CMOS PA with current

Gain (dB)

PAE (%)
PAE (%)

6
10 10 15
4 combining, Cc and linearization has been demonstrated in
65nm CMOS process. The PA achieves highest gain and
5 Psat 5 10 2
P1dB Gain
PAE PAE 0
0
110 115 120 125 130
0 5
8 10 12 14
FoM as well as good stability. The proposed PA has a
Frequency (GHz) Output Power (dBm)
measured small signal gain of 22.3 dB at 119 GHz and
(a) (b) achieves the P1dB of 12.2 dBm and a saturated output
Fig. 5. (a) Measured PA Psat, P1dB and PAE from 112 to power of 14.5 dBm with 10.2% PAE at 118 GHz.
130GHz, (b) Measured D-band PA gain and PAE vs. Output
power at 118 GHz.
ACKNOWLEDGEMENT
was achieved with a 3-dB bandwidth of about 17 GHz. This work was supported by the Institute for
The measured reverse isolation of the PA is -38 dB at 119 Information & communications Technology Promotion
GHz and is smaller than -32 dB until 150 GHz. The (IITP) grant funded by the Korea government (MSIP) (No.
extrinsic parasitic of the transistor models is obtained by 2017-0-00765, 200 Gbps MIMO RF Front-end for High
using parasitic extraction tools and full EM simulation is Rate Proximity Communication).
performed to get parasitic components of inter-connection
metals. The parasitic capacitance in the probe
pads is removed by the pad de-embedding method. The REFERENCES
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