A Comparative Review and Evaluation of Approximate

Adders

Honglan Jiang Jie Han Fabrizio Lombardi

Department of Electrical and Department of Electrical and Department of Electrical and
Computer Engineering Computer Engineering Computer Engineering
University of Alberta University of Alberta Northeastern University
Edmonton, Alberta, Canada Edmonton, Alberta, Canada Boston, MA 02115, USA
T6G 2V4 T6G 2V4 [email protected]
[email protected] [email protected]

ABSTRACT efficiency. Approximate computing has been advocated as

As an important arithmetic module, the adder plays a key a new approach to saving area and power dissipation, as
role in determining the speed and power consumption of well as increasing performance at a limited loss in accuracy
a digital signal processing (DSP) system. The demands of [3]. While computation errors are in general not desirable,
high speed and power efficiency as well as the fault tolerance applications such as multimedia (image, audio and video)
nature of some applications have promoted the development processing, wireless communications, recognition, and data
of approximate adders. This paper reviews current approx- mining are tolerant to some errors. Due to the statisti-
imate adder designs and provides a comparative evaluation cal/probabilistic nature of these applications, small errors
in terms of both error and circuit characteristics. Simula- in computation would not impose noticeable degradation in
tion results show that the equal segmentation adder (ESA) performance [22].
is the most hardware-efficient design, but it has the lowest Generally, there are two types of methodologies for im-
accuracy in terms of error rate (ER) and mean relative error proving speed and power efficiency by approximation. The
distance (MRED). The error-tolerant adder type II (ETAII), first methodology uses a voltage-over-scaling (VOS) tech-
the speculative carry select adder (SCSA) and the accuracy- nique for CMOS circuits to save power [4,15,19]. The second
configurable approximate adder (ACAA) are equally accu- methodology is based on redesigning a logic circuit into an
rate (provided that the same parameters are used), how- approximate version. While the VOS technique is applicable
ever ETATII incurs the lowest power-delay-product (PDP) to most circuits for error-tolerant applications, an approxi-
among them. The almost correct adder (ACA) is the most mate redesign pertains to the functionalities of different logic
power consuming scheme with a moderate accuracy. The circuits. Approximately redesigned adders (simply referred
lower-part-OR adder (LOA) is the slowest, but it is highly to as approximate adders) are reviewed and a comparative
efficient in power dissipation. evaluation is performed in this paper.

Categories and Subject Descriptors 2. REVIEW

B.2.0 [Arithmetic and Logic Structures]: General; B.6.1 Adders are utilized for calculating the addition (or sum)
[Logic Design]: Design Styles—combinational logic; B.7.1 of two binary numbers. Two common types of adders are
[Integrated Circuits]: Types and Design Styles—VLSI ; the ripple-carry adder (RCA) and the carry lookahead adder
B.8.0 [Performance and Reliability]: General (CLA) [9, 21]. In an n-bit RCA, n 1-bit full adders (FAs)
are cascaded; the carry of each FA is propagated to the next
Keywords FA, thus the delay of RCA grows in proportion to n (or
O(n)). An n-bit CLA consists of n SPGs, which operate in
Approximate Computing; Adder; Power; Accuracy. parallel to produce the sum, generate (gi = ai bi ) and prop-
agate (pi = ai + bi ) signals, and connected to a carry looka-
1. INTRODUCTION head generator. For CLA, all carries are generated directly
As the physical dimensions of CMOS scale down to a by the carry lookahead generator using only the generate
few tens of nanometers, it has been increasingly difficult and propagate signals, so the delay of CLA is logarithmic
to improve circuit performance and/or to enhance power in n (or O(log(n))), thus significantly shorter than that of
RCA. However, CLA requires larger circuit area and higher
power dissipation. The carry lookahead generator becomes
Permission to make digital or hard copies of all or part of this work for personal or
classroom use is granted without fee provided that copies are not made or distributed
very complex for large n. The area complexity of CLA is
for profit or commercial advantage and that copies bear this notice and the full cita- O(nlog(n)) when the fan-in and fan-out of the constituent
tion on the first page. Copyrights for components of this work owned by others than gates are fixed [16].
ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or re- Many approximation schemes have been proposed by re-
publish, to post on servers or to redistribute to lists, requires prior specific permission ducing the critical path and hardware complexity of the ac-
and/or a fee. Request permissions from [email protected].
curate adder. An early methodology is based on a specula-
Copyright ©
GLSVLSI’15, May 20–22, 2015, Pittsburgh, PA, USA.
2015 ACM 978-1-4503-3474-7/15/05 ...$15.00.
http://dx.doi.org/10.1145/2742060.2743760.
tive operation [16, 23]. In an n-bit speculative adder, each
sum bit is predicted by its previous k less significant bits

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(LSBs) (k < n). A speculative design makes an adder sig-
nificantly faster than the conventional design. Segmented
adders are proposed in [7,19,27]. An n-bit segmented adder
is implemented by several smaller adders operating in par-
allel. Hence, the carry propagation chain is truncated into
shorter segments. Segmentation is also utilized in [1,5,8,10,
12,25], but their carry inputs for each sub-adder are selected
differently. This type of adder is referred to as a carry se-
lect adder. Another method for reducing the critical path
delay and power dissipation of a conventional adder is by
approximating the full adder [2, 17, 20, 24]; the approximate
adder is usually applied to the LSBs of an accurate adder.
In the sequel, the approximate adders are divided into four Figure 1: The almost correct adder (ACA). : the carry
categories. propagation path of the sum bit.

2.1 Speculative Adders

As the carry chain is significantly shorter than n in most
practical cases, [23] has proposed an almost correct adder
(ACA) based on the speculative adder design of [16]. In an
n-bit ACA, k LSBs are used to predict the carry for each
sum bit (n > k), as shown in Fig. 1. Therefore, the critical
path delay is reduced to O(log(k)) (for a parallel implemen-
tation such as CLA, the same below). As an example, four Figure 2: The equal segmentation adder (ESA). k: the max-
LSBs are used to calculate each carry bit in Fig. 1. As imum carry chain length; l: the size of the first sub-adder
each carry bit needs a k-bit sub-carry generator in the de- (l ≤ k).
sign of [16], (n − k) k-bit sub-carry generators are required
in an n-bit adder and thus, the hardware overhead is rather
high. This issue is solved in [23] by sharing some compo-
nents among the sub-carry generators. Moreover, a variable
latency speculative adder (VLSA) is then proposed with an
error detection and recovery scheme [23]. VLSA achieves a
speedup of 1.5× on average compared to CLA.

2.2 Segmented adders

2.2.1 The Equal Segmentation Adder (ESA)
A dynamic segmentation with error compensation (DSEC) Figure 3: The error-tolerant adder type II (ETAII) [27]: the
is proposed in [19] to approximate an adder. This scheme carry propagates through the two shaded blocks.
divides an n-bit adder into a number of smaller sub-adders;
these sub-adders operate in parallel with fixed carry inputs.
In this paper, the error compensation technique is ignored 2.2.3 Accuracy-Configurable Approximate Adder
because the focus is on the approximate design, so the equal An accuracy-configurable approximate adder (ACAA) is
segmentation adder (ESA) (Fig. 2) is considered
⌈ ⌉ as a simple proposed in [7]. As accuracy can be configured at runtime
structure of the DSEC adder. In Fig. 2, nk sub-adders are by changing the circuit structure, a tradeoff of accuracy ver-
used, l is the size of the first sub-adder (l ≤ k), and k is sus performance
⌈ ⌉ and power can be achieved. In an n-bit
the size of the other sub-adders. Hence, the delay of ESA adder, nk − 1 2k-bit sub-adders are required. Each sub-
is O(log(k)) and the hardware overhead is significantly less adder adds 2k consecutive bits with an overlap of k bits, and
than ACA. all 2k-bit sub-adders operate in parallel to reduce the delay
to O(log(2k)). In each sub-adder, the half most significant
2.2.2 The Error-Tolerant Adder Type II (ETAII) sum bits are selected as the partial sum. An error detection
Another segmentation based approximate adder (ETAII) and correction (EDC) circuit is used to correct the errors
is proposed in [27]. Different from ESA, ETAII consists of generated by each sub-adder. The accuracy configuration is
carry generators and sum generators, as shown in Fig. 3 (n implemented by the approximate adder and its EDC with
is the adder size; k is the size of the carry and sum gener- a pipelined architecture. For the same k, the carry propa-
ators). The carry signal from the previous carry generator gation path is the same for each sum bit as in ACAA and
propagates to the next sum generator. Therefore, ETAII ETAII; hence they have the same error characteristics.
utilizes more information to predict the carry bit and thus,
it is more accurate compared with ESA for the same k. Be- 2.2.4 The Dithering Adder
cause the sub-adders in ESA produce both sum and carry, The dithering adder [18] starts by dividing a multiple-
the circuit complexity of ETAII is similar to ESA, however bit adder into two sub-adders. The higher sub-adder is an
its delay is larger (O(log(2k))). In addition to ETAII, sev- accurate adder and the lower sub-adder consists of a con-
eral other error tolerant adders (ETAs) have been proposed ditional upper bounding module and a conditional lower
by the same authors in [26, 28, 29]. bounding module. An additional “Dither Control” signal

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 ators (one with carry-0 and one with carry-1) and one carry
predictor in each block. The output of the ith carry pre-
dictor is used to select carry signals for the (i + 1)th sum
generator. l input bits (rather than k, l < k) in a block are
used in a carry predictor. Therefore, the hardware overhead
is reduced compared to SCSA.

2.3.5 The Consistent Carry Approximate Adder

The consistent carry approximate adder (CCA) [10] is also
Figure 4: The speculative carry selection adder (SCSA). based on SCSA. Likewise, each block of CCA comprises
adder0 with carry-0 and adder1 with carry-1. The select
signal of a multiplexer is determined by the propagate sig-
i−1
is used to configure an upper or lower bound of the lower nals, i.e., Si = (P i + P i−1 )SC + (P i + P i−1 )Cout , where
sum and carry into the higher accurate sub-adder, resulting Cout is the carry out of the (i − 1) adder0, and SC is a
i−1 th

in a smaller overall error variance. global speculative carry (referred to as a consistent carry).
In CCA, the carry prediction depends not only on its LSBs,
2.3 Carry Select Adders but also on the higher bits. The critical path delay and area
In the carry select adders, several signals are commonly complexity of CCA are similar to SCSA.
used: generate gj = aj bj , propagate pj = aj ⊕ bj , and P i =
∏ i
k−1 2.3.6 The Generate Signals Exploited Carry Specu-
pj . P i = 1 means that all k propagate signals in the ith lation Adder (GCSA)
j=0
block are true. In [5], the generate signals are used for carry speculation.
GSCA has a similar structure as CSA. The only difference
2.3.1 The Speculative Carry Select Adder (SCSA) between them is the carry selection; the carry-in for the
The SCSA (i + 1)th sub-adder is selected by its own propagate signals
⌈ ⌉ is proposed in [1]. An n-bit SCSA consists
of m = nk sub-adders (window adders). Each sub-adder rather than its previous block. The carry-in is the most
i
is made of two k-bit adders: adder0 and adder1, as shown significant generate signal gk−1 of the ith block if P i = 1, or
th
in Fig. 4. Adder0 has carry-in “0” while the carry-in of else it is the carry-out of the i sub-carry generator. The
adder1 is “1”; then the carry-out of adder0 is connected to critical path delay of GCSA is O(log(2k)) due to the carry
a multiplexer to select the addition result as a part of the propagation. This carry selection scheme effectively controls
final result. Thus, the critical path delay of SCSA is tadder + the maximal relative error.
tmux , where tadder is the delay of the sub-adder (O(log(k))),
and tmux is the delay of the multiplexer. SCSA and ETAII 2.4 Approximate Full Adders
achieve the same accuracy for the same parameter k, because
the same function is used to predict the carry for every sum 2.4.1 The Lower-Part-OR Adder (LOA)
bit. Compared with ETAII, SCSA uses an additional adder LOA [17] divides an n-bit adder into an (n − l)-bit more
and multiplexer in each block and thus, the circuit of SCSA significant sub-adder and an l-bit less significant sub-adder.
is more complex than ETAII. For the less significant sub-adder, its inputs are simply pro-
cessed by using OR gates (as a simple approximate full
2.3.2 The Carry Skip Adder (CSA) adder). The more significant (n − l)-bit sub-adder is an
Similar to ⌈SCSA,
⌉ an n-bit carry skip adder (CSA) [8] is accurate adder. An extra AND gate is used to generate the
divided into nk blocks, but each block consists of a sub- carry-in signal for the more significant sub-adder by AND-
carry generator and a sub-adder. The carry-in of the (i+1)th ing the most significant input bits of the less significant sub-
sub-adder is determined by the propagate signals of the ith adder. The critical path of LOA is from the AND gate
block: the carry-in is the carry-out of the (i − 1)th sub-carry to the most significant sum bit of the accurate adder, i.e.,
generator when all the propagate signals are true (P i = 1), approximately O(log(n − l)). LOA has been utilized in a
otherwise it is the carry-out of the ith sub-carry generator. recently-proposed approximate floating-point adder [14].
Therefore, the critical path delay of CSA is O(log(2k)). This
carry select scheme enhances the carry prediction accuracy. 2.4.2 Approximate Mirror Adders (AMAs)
In [2], five AMAs are proposed by reducing the number of
2.3.3 The Gracefully-Degrading Accuracy-Configurable transistors and the internal node capacitance of the mirror
Adder (GDA) adder (MA). The AMA adder cells are then used in the
An accuracy-configurable adder, referred to as the gracefully- LSBs of a multiple-bit adder. However, the critical paths of
degrading accuracy-configurable adder (GDA), is presented AMA1-4 are longer than LOA because the carry propagates
in [25]. Control signals are used to configure the accuracy through every bit. As for AMA5, the carry-out is one of the
of GDA by selecting the accurate or approximate carry-in inputs; thus, no carry propagation exists in the LSBs of an
using a multiplexer for each sub-adder. The delay of GDA is approximate multiple-bit adder.
determined by the carry propagation and thus by the control
signals to multiplexers. 2.4.3 Approximate Full Adders using Pass Transis-
tors
2.3.4 The Carry Speculative Adder Three approximate adders (AXAs) based on XOR/XNOR
Different from SCSA, the carry speculative adder (CSPA) gates and multiplexers (implemented by pass transistors)
in [12] contains one sum generator, two internal carry gener- have been presented in [24]. Several approximate comple-

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mentary pass transistor logic (CPL) adders have been pro- the smallest ER and MRED. ESA-3 is the least accurate
posed by reducing the number of transistors in the accurate design in terms of ER and MRED.
CPL adder [20]. Significant area and power savings have
been obtained for both types of approximate designs. 3.2 Circuit Characteristics
To assess circuit characteristics, the considered 16-bit ap-
proximate adders and the accurate CLA are implemented
3. COMPARATIVE EVALUATION in VHDL and synthesized using the Synopsys Design Com-
In the evaluation, SCSA is selected as a typical carry se- piler based on an STM 65-nm process; delay, area and power
lect adder and LOA is considered as a representative design are then obtained. Among ETAII, SCSA and ACAA (with
using approximate full adders. All adders and sub-adders the same error characteristics when the same parameter k
are implemented as CLA in this paper. is selected), SCSA incurs the largest power dissipation be-
cause two sub-adders and one multiplexer are utilized in
3.1 Error Characteristics each block, and ACAA is the slowest because of its critical
path (2k) is twice that of the other two adders. The block
To evaluate the accuracy of approximate adders, analyt-
of ETAII (a carry generator and a sum generator) is signif-
ical and simulation-based approaches have been proposed
icantly simpler than those of SCSA and ACAA. Therefore,
[6, 11, 13, 18, 22]. In this paper, Monte Carlo simulation is
ETAII has a shorter delay and consumes less power and area
performed. The error rate (ER, the probability of produc-
than SCSA and ACAA, thus ETAII is selected for circuit
ing an incorrect result), the normalized mean error distance
comparisons.
(NMED, the normalization of mean error distance (MED) by
A circuit with larger area is likely to consume more power,
the maximum output of the accurate adder) and the mean
so only power and delay are considered in the comparison.
relative error distance (MRED, the average value of all pos-
Fig. 6 shows the delay and power of the approximate adders
sible relative error distances (REDs)) are used to assess the
with ascending delay (Fig. 6(a)) and power (Fig. 6(b)) from
error characteristics of the approximate designs. Error dis-
left to right. Obviously, the accurate CLA has the longest
tance (ED) and RED are calculated as: ED = |M ′ −M | and
delay among all adders, but not the highest power dissipa-
RED = ED M
, where M ′ is the approximate result and M is
tion. LOA (shown in different patterns) is the slowest, but
the accurate result [11]. M ED is the mean of all possible
it is very power efficient compared with the other approxi-
EDs.
mate adders. With the same k, ESA is the fastest (when k
The functions of the approximate adders (16−bit) are im-
is 3 or 4) and most power efficient due to its simple segment
plemented in MATLAB and simulated with 108 random in-
structure. ETAII is the slowest (except for k = 3) excluding
put combinations. The error measures in ER, NMED and
LOA, and ACA incurs the largest power consumption due to
MRED are obtained. Fig. 5 shows the simulation results
its complex speculation circuit. Among all the approximate
where each adder’s name is followed by the value of its pa-
adders shown in Fig. 6, ESA-3 is the fastest, while LOA-8 is
rameter k. For ACA, ETAII and ESA, k is the size of the
the slowest. The delays of all ACAs are very close (less than
sub-adder, while k is the size of the less significant adder for
400 ps), and all the LOAs have a delay larger than 600 ps.
LOA (as implemented by OR gates).
For ESA and ETAII, a smaller k leads to a smaller delay and
The NMED and MRED values of the approximate adders
power dissipation, a larger k also shows significantly larger
with data sorted by the MRED are shown in Fig. 5(a). The
values of these metrics.
logarithms (base 10) of the NMED and MRED are plotted,
Since a smaller delay does not always imply lower power
and the vertical axis is labeled by negative numbers. In this
dissipation, the power-delay-product (PDP) is used as a
figure, ETAII-k represents ETAII-k, SCSA-k and ACAA-
joint metric to evaluate the circuit characteristics of the ap-
k because they have the same carry propagation chain for
proximate adders. Fig. 7 shows in ascending order the PDPs
each sum bit and hence, the same error characteristics (ER,
of the approximate adders from left to right. ESA-3 has
NMED and MRED). The NMED and MRED show the same
the smallest PDP, while the accurate CLA has the largest
trend, so we only consider MRED in the comparison. Fig.
value. LOA-10 and LOA-9 have moderate PDPs (due to
5(b) shows the comparison of ER and MRED of the approx-
large delay and low power dissipation). In terms of PDP,
imate adders with data sorted by ER.
the approximate adders can be classified into three classes:
Among these approximate adders, ETAII-6 has the small-
ESA-3, ESA-4 and ETAII-3 have the smallest PDP with less
est MRED, while ESA-3 has the largest. LOA (shown in
than 10 fJ, then ESA-5, LOA-10, ETAII-4 and ACA-3 with
different patterns in Fig. 5(b)) has a structure different
around 20 fJ, and the PDPs of the other approximate adders
from the other approximate adders. Its higher part is to-
are larger than 20 fJ and less than 45 fJ.
tally accurate, while the approximate part is less significant.
Therefore, the MRED of LOA is rather small but its ER is
very large. The information used to predict each carry in 4. DISCUSSION AND CONCLUSION
ESA is rather limited, so its MRED and ER are the largest In this paper, current approximate adders are reviewed;
(excluding LOA). Specifically, a lower ER usually indicates a their error and circuit characteristics are evaluated. Fig. 8
smaller MRED; a larger k normally means a lower ER and shows the MRED and PDP of the approximate adders in
MRED for all the approximate adders (except for LOA). a two-dimension (2-D) plot. ESA-3 and ESA-4 have rather
Compared with ETAII, SCSA and ACAA (represented by small PDP but a considerably large MRED; LOA-8, LOA-7
ETAII in Fig. 5), ACA gives slightly higher ER and MRED and ETAII-6 are the opposite, i.e., they have a small MRED
for the same k due to the shorter carry propagation chain but a large PDP. These approximate adders do not show the
(thus, less information is used for predicting the carry bits). best tradeoff, but they can be used for special applications
In summary, ETAII-6, SCSA-6 and ACAA-6 are the most where either hardware efficiency or high accuracy is required.
accurate adders among the compared designs since they have The best tradeoff is met by ETAII-3 with a small PDP and

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 (a) (b)

Figure 5: A comparison of error characteristics of approximate adders with data sorted on (a) MRED and (b) ER.

(a) (b)

Figure 6: A comparison of delay and power of approximate adders with data sorted on (a) delay and (b) power.

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