DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
(Accredited by NBA and ABET)
Course Title : Computer Organization and Architecture L T P C
Course Code : 22CS205 2 0 2 3
Academic Year: 2024-25 Semester :2
Module No : 01
Branch : II CSE Section : ALL
Name of the Lead Faculty: Dr.N.Nagendra Reddy No. of Questions: 10
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1. The outputs of four registers, R0, R1, R2, and R3, are connected through 4-to-1-line multiplexers to the
inputs of a fifth register, RS. Each register is eight bits long. Four timing variables dictate the required
transfers T0 through T3, as follows:
T0: R5 R0
T1: R5 R1
T2: R5 R2
T3: R5 R3
The timing variables are mutually exclusive, which means that only one timing variable is equal to 1 at
any given time, while the other three are equal to 0.
a) Write short notes on Register Transfer language. 3M BTL2 CO2
b) Suggest a block diagram for the hardware implementation for register transfers. 3M BTL4 CO2
c) Design the necessary connections from the four timing variables to the selection inputs of the
multiplexers and to the load input of register R5. 4M BTL-3 CO2
2. A typical digital computer has many registers, and paths must be provided to transfer information from
one register to another. The number of wires will be excessive if separate lines are used between each
register and all other registers in the system. A more efficient scheme for transferring information
between registers in a multiple-register configuration is a common bus system. A bus structure consists
of a set of common lines, one for each bit of a register, through which binary information is transferred
one at a time. Control signals determine which register is selected by the bus during each particular
register transfer.
a) Illustrate a System bus system with three-state buffers. 3M BTL1 CO1
b) Consider the bus system for four registers using multiplexers and each register has four bits,
numbered 0 through 3. 3M BTL3 CO1
c) Which scheme in the above bus system be able to transfer information from any register to any other
register? Implement the connections that must be included to provide a path from the outputs of any
one register to the Inputs of the other register. 4M BTL4 CO1
3. a) How does a common bus system improve the performance of a computer system? 2M BTL1 CO1
b) Design a common bus with multiplexers for an 8-bit CPU with 4 registers. 4M BTL1 CO1
c) Design a common bus with decoders for a 4-bit CPU with 8 registers. 4M BTL1 CO1
4. For a fixed point integer with signed magnitude and complement of one register add 1 with the other
register
a) Give a brief note on the Hardware implementation and algorithm for Addition and Subtraction.
3M BTL2 CO1
b) Design an algorithm to multiply two unsigned hexadecimal numbers in the range of A1<N< F3.
3M BTL3 CO1
c) Justify the algorithm that suits best for performing the multiplication of signed numbers. Explore
the multiplication of two signed decimal numbers which are in the range of -32<N<31. 4M BTL3 CO1
5. a) Illustrate an algorithm to convert a Floating-point number to its equivalent Decimal number with
a suitable Flow chart. 3M BTL2 CO1
b) Verify the logic by taking two different sign Floating-point numbers with 23 bits mantissa each and
convert them to the equivalent Decimal numbers. 3M BTL2 CO1
c) With the obtained Decimal numbers construct a logic for the Addition and Subtraction operations
by designing 2’s complement module using the combinational circuit. 4M BTL2 CO1
6. a) State the importance of floating-point representation over fixed-point representation.
2M BTL1 CO1
b) Convert the following numbers into IEEE 754 single-precision floating-point format. 4M BTL3 CO1
i. −1.10001111001 × 2 1001101
ii. 1.1011110000101 × 2 −1010001
c) Convert the following numbers into IEEE 754 double-precision floating-point format. 4M BTL3 CO1
i. −1.10001111001 × 2 1001101
ii. 1.1011110000101 × 2 −1010001
7. a) Define and classify the microoperations with suitable illustrations. 2M BTL2 CO2
b) Perform the following arithmetic operations using 2’s complement and 10’s complement
methods. 4M BTL3 CO1
i. (-7) + (+5)
ii. (+4) + (-3).
c) Consider the instruction formats of the basic computer and the list of instructions supported by
basic computer. For each of the following 16-bit instructions, give the equivalent four-digit
hexadecimal code and explain in your own words what it is that the instruction is going to perform.
4M BTL3 CO1
i. 0001 0000 0010 0100
ii. 1011 0001 0010 0100
8. a) Differentiate Von Neumann and Harvard computer architectures. 2M BTL2 CO2
b) Derive a flow chart for a 4-bit CPU of a computer system to perform division.
4M BTL3 CO2
c) Design an ALU, for a 4-bit hypothetical CPU that performs the following operations.
4M BTL3 CO2
i. Addition with carry
ii. Ex-OR
iii. Logical Left shift
iv. Right shift of one bit with sign extension.
9. a) Mention the importance of MAR, PC, MDR and IR registers. 2M BTL2 CO1
b) How does the microprocessor differentiate between direct and indirect addressing modes from
binary representation of an instruction? 4M BTL4 CO2
c) Perform the AND logic, or logic and mask micro-operation on the following 8-bit binary
numbers and provide the result:
A = 11011011
B = 10101100 4M BTL3 CO2
10. a.Write a sequence of logic micro-operations to clear the least significant bit of a register without
altering the other bits. 3M BTL2 CO2
b. A 16-bit register contains the value 1010110011101110. Write the result after performing:
i. A logical left shift by 3 bits.
ii. A circular right shift by 4 bits. 3M BTL3 CO2
c. A signal processing unit rotates a binary number A circularly to the left by 3 bits and then applies
an XOR operation with another number B. If A=11011010 and B=01100111, determine the final
result. 4M BTL3 CO2
