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High-speed digital-to-analog converter concepts

Conference Paper in Proceedings of SPIE - The International Society for Optical Engineering · January 2017
DOI: 10.1117/12.2250359

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 High-Speed Digital-to-Analog Converter Concepts
Christian Schmidta,b , Christoph Kottkea,b , Volker Jungnickela , and Ronald Freunda
a
Photonic Networks and Systems Department, Fraunhofer Heinrich-Hertz-Institute,
Einsteinufer 37, 10587 Berlin, Germany
b
Electrical Engineering and Computer Science Department, Technische Universität Berlin,
Einsteinufer 25, 10587 Berlin, Germany

ABSTRACT
In todays fiber-optic communication systems, the bandwidth of the photonic components, i.e. modulators and
photo diodes, is way greater than that of their electrical counterparts, i.e. digital-to-analog converters (DACs) and
analog-to-digital converters (ADCs). In order to increase the transmission capacity, the bandwidth limitations
need to be overcome. We review the progress and the recent results in the field of high-speed DACs, which
are desirable for software-defined transmitters. Furthermore, we evaluate interleaving concepts regarding their
ability to overcome the above mentioned limitations and demonstrate recent experimental results for a bandwidth
interleaved DAC with 40 GHz analog electrical bandwidth.
Keywords: Optical Communications, Digital-to-Analog Converter, Interleaving, Signal Processing

1. INTRODUCTION
The increasing need for high data rates requires the optical networks to advance.1 For todays communication
systems, transmitters based on DACs are desirable, since software-defined waveforms can be generated with both
varying constellation size and modulation bandwidth. Furthermore, pre-equalization of both transmitter (Tx)
impairments and chromatic dispersion of the fiber enhances the transmission performance.2 Current fabrication
technologies and materials, respectively, that can be used for high-speed DACs, are CMOS, silicon-germanium
(SiGe) and indium phosphide (InP). For these technologies there is a trade-off between energy-efficiency and
bandwidth, e.g. CMOS is highly energy efficient, but the maximum achievable bandwidth is not as high as with
SiGe or InP and vice versa.
Next to these trade-offs concerning the fabrication technologies, the bandwidth of the photonic components
of todays fiber-optic communication systems, i.e. modulators and photo diodes, is way greater than that of their
electrical counterparts, i.e. DACs and ADCs. In order to increase the transmission capacity, the bandwidth
limitations need to be overcome. Hence, new concepts have been introduced into the system design in order to
combine multiple data converters with analog circuitry to a system having a greater sample rate and bandwidth
than a single data converter. Three concepts are viable: The earliest is the time interleaving DAC (TI-DAC)
concept, whereby the outputs of multiple DACs are added passively in order to generate a higher overall sampling
rate. Recently, two other interesting concepts have been introduced: firstly, multiplexing the output of multiple
DACs with an analog multiplexer yielding a multiplexing DAC (MUX-DAC) and secondly, combining multiple
signals in the frequency domain using an analog processing system consisting of mixers and filters, i.e. an analog
bandwidth interleaving DAC (ABI-DAC).
In the following, we present the current status of commercially available high-speed DACs and arbitrary
waveform generators (AWGs), respectively, and recent research results in this field. Furthermore, we evaluate
the interleaving concepts mentioned above regarding their ability to enhance the DAC performance as well as
their limitations. Moreover, the experimental results of an ABI-DAC, consisting of two DACs generating an
80 GBd signal with 40 GHz electrical bandwidth, are presented.
E-Mail: [email protected]
 Table 1. Overview of commercially available high-speed DACs and AWGs, respectively (sorted by sample rate).

Micram Keysight Anritsu SHF Tektronix

7 8, 9 10 11
DAC4 M8196A G0374A 613A AWG70001A12
Sample rate (GS/s) 100 92 64 60 50
3 dB Bandwidth (GHz) 40 32 n/a 36 15
Resolution (bit) 6 8 2 3 10
ENOB (bit) 4.6 (@48 GHz) 5.3 (@31.9 GHz) n/a n/a 4.6 (@14.99 GHz)
Amplitude (mVpp, SE) 500 1 000 900 730 500
Technology BiCMOS 28 nm CMOS n/a n/a n/a

2. HIGH-SPEED DACs
High-speed DACs are essential for both flexible and high-capacity optical networks as mentioned in Sec. 1. Es-
pecially, the bandwidth of state-of-the-art DACs is lower than that of state-of-the-art electro-optical modulators.
A recent research result by Haffner3 demonstrated a plasmonic-based Mach-Zehnder modulator (MZM) inte-
grated into a silicon waveguide of 10 µm length with a bandwidth exceeding 70 GHz. Commercially available are
modulators with 30-40 GHz bandwidth, e.g. Thorlabs’ intensity modulator LN05S-FC with 35 GHz bandwidth4
or Fujitsu’s in-phase and quadrature (I/Q) modulator FTM7992HMA with 35 GHz bandwidth,5 both based on
LiNbO3 . EOSPACE offers ultra-broadband LiNbO3 modulators on request up to 110 GHz.6
In Tab. 1 commercially available DACs and AWGs, respectively, are listed. Sorted by sample rate, the
bandwidth, the vertical resolution, the effective number of bits (ENOB), the single-ended (SE) output amplitude
and the manufacturing technology are given. The highest bandwidth reported so far, is provided by Micram’s
DAC4, which has 40 GHz bandwidth, but lacks a real-time interface. Keysight’s AWG provides two more bit
vertical resolution, though the bandwidth is 20% lower.
Recent research results in the field of DAC integrated circuits (ICs) are listed in Tab. 2. One can observe
that there is virtually no difference concerning the performance between the results of research and industry.
This underlines the importance of advances in this area, as they would be adapted by the industry immediately.
Note, that with interleaving concepts the performance of DACs could be seriously enhanced. Recently, multiple
publications originated in that area, which are presented in the following section.

Table 2. Overview of recent research results in the field of high-speed DAC ICs (sorted by sample rate).

University
NTT14 III-V Labs15
Stuttgart13
Sample rate (GS/s) 100 90 84
3 dB Bandwidth (GHz) 13 >40 n/a
Resolution (bit) 8 6 3
ENOB (bit) 3.2 (@ 24.9 GHz) n/a n/a
Amplitude (mVpp, SE) ca. 400 500 ca. 4000
Technology 28 nm CMOS InP HBT InP DHBT
Concept time-interleaved non-interleaved non-interleaved
 (a) (b)
NRZ RZ
DAC 1
3

DAC2 DAC1
2
1
0
3
2
CLK 1
0
3
180° 2

Σ
1
0
0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4
DAC 2 t·fs t·fs

Figure 1. TI-DAC consisting of two DACs: a) block diagram; b) the operation of two TI techniques: NRZ and RZ pulses.

3. INTERLEAVING CONCEPTS FOR DACs

In recent years, multiple concepts have been introduced in order to increase the performance of DACs by com-
bining multiple DACs to a single converter, including TI-DAC, MUX-DAC and ABI-DAC. In the following
these concepts are introduced and evaluated regarding there ability to increase both the sample rate and the
bandwidth of DACs. Moreover, recent research results are presented and the limitations of the concepts are
highlighted.

3.1 Time Interleaving DAC (TI-DAC)

The time interleaving (TI) concept is based on summing the output signals of multiple DACs, referred to as
sub-signals, in the time domain, sucht that a higher overall sampling rate is achieved. A block diagram of the
concept is shown in Fig. 1 a) exemplary for two DACs. Both DACs are operated with the same clock frequency,
thus having the same sample rate fs . The clock signals are exposed to a phase shift relative to each other in order
to ensure a correct summation of the DAC output signals. The output signals could be either added passively,
e.g. with a power combiner or actively, e.g. with a summing amplifier.
There are two basic techniques in order to add the sub-signals as shown in Fig. 1 b): Firstly non-return-to-
zero (NRZ) signals can be utilized. However, they require a digital pre-distortion algorithm in order to calculate
the sub-signals, which need to add up correctly in order to form the combined output signal. This variant is
also referred to as pseudo-interleaving and is used e.g. in in the Fraunhofer HHI AWG with 70 GS/s, 18 GHz
bandwidth and 6 bit resolution16 and in the Tektronix AWG 70000 with 50 GS/s, 15 GHz bandwidth and 10 bit
resolution.12
Secondly, return-to-zero (RZ) signals can be used. They do not require a pre-distortion algorithm, since
the sub-signals are orthogonal in the time domain. Thus, this variant is also referred to as true interleaving.
However, the requirements on the DACs’ switching speed and thus, on the bandwidth, are increased by using
RZ pulses compared to NRZ pulses. Both techniques, NRZ and RZ, have been combined by Huang13 in order
to design an 8 bit 100 GS/s CMOS DAC consisting of two 50 GS/s NRZ-sub-DACs, which each consist of two
25 GS/s RZ-sub-DACs. However, the total bandwidth is limited to 13 GHz, thus preventing the use of the DAC
at high symbol rates.
Both techniques increase the sample rate by a factor equal to the number of DACs used. Hence, the usable
bandwidth is increased by this factor as well according to the Nyquist-Shannon sampling theorem. The sample
rate enhancement can be either used in order to cancel images above the first Nyquist zone of a single converter17
or to generate signals with bandwidths exceeding the first Nyquist zone. Though, the usable bandwidth is
extended, the analog bandwidth remains constant, since adding is a linear operation. Thus, the increased
sampling rate could not be used for higher symbol rates per se.
 (a) (b)
DAC 1 3

DAC2 DAC1
2
1
0
3
2
1
CLK x2 2:1 0
3

MUX
2
180° 1
0
0 0.5 1 1.5 2 2.5 3 3.5 4
DAC 2 t·fs

Figure 2. MUX-DAC consisting of two DACs: a) block diagram; b) operation of the ideal multiplexer (denoted as dashed
black line).

3.2 Multiplexing (MUX-DAC)

The other concept in the time domain makes use of a high-speed analog multiplexer (MUX) in order to switch
between the output signals of multiple DACs. A block diagram is shown in Fig. 2 a) exemplary for two DACs:
both DACs operate with the same clock frequency, thus having the same sample rate. The clock signals are
delayed to each other such that the sub-signals are switched through by the MUX in the center of each symbol
period. The MUX is usually operated at twice the clock rate.
In Fig. 2 b) the ideal MUX operation is shown for the case of two DACs. The output signal is generated by
the MUX switching between the sub-signals. Thereby, the MUX ”samples” the sub-signals in the center of each
symbol, denoted by the black dotted line.
The concept has been introduced in 2011 by Ferenci,18 where an InP MUX was shown operating up to
50 GHz. Recently, a 2:1-MUX with a bandwidth exceeding 50 GHz has been presented.19 With this module an
80 GBd PAM-4 signal has been generated by multiplexing the output of two DACs, each having a bandwidth
of about 20 GHz.20 The DACs were running at a sample rate of 60 GS/s generating two sub-signals each with
40 GBd, which were combined by the multiplexer with a clock frequency of 43.3 GHz. Later, the MUX was used
with discrete multi-tone (DMT) modulation achieving 300 Gb/s with a halved clock frequency of 37.5 GHz and
digital pre-processing.21
Note, that the MUX does not necessarily be a single MUX - a multi-stage approach consisting of several MUXs
is possible as well. The sample rate is increased by a factor equal to the number of DACs as for TI. However, the
analog bandwidth is increased, since multiplexing is a non-linear operation and thus, the bandwidth limitations
of the DACs can be circumvented. The total bandwidth of the MUX-DAC is mainly determined by the analog
bandwidth of the MUX. Critical for this concept is the precise synchronization of the MUX with the DACs.
Therefore, feedback signals are required for synchronization. Furthermore, digital signal processing (DSP) might
be necessary to undo the frequency responses of the DACs and the MUX.

3.3 Analog Bandwidth Interleaving DAC (ABI-DAC)

Analog bandwidth interleaving (ABI) uses multiple DACs in parallel to perform the digital-to-analog (D/A)
conversion for a digital signal, whereby each DAC performs the D/A conversion for a spectral fraction, i.e. a
sub-spectrum, of the digital signal. The sub-signals, corresponding to the sub-spectra, are then combined with
an analog processing system consisting of mixers and filters. The concept of bandwidth interleaving has been
introduced by LeCroy22 for their ADCs in 2005 as digital bandwidth interleaving (DBI). In accordance with
this concept, where the sub-signals are de-interleaved in the analog domain and interleaved digitally, the scheme
for DACs need to be called analog bandwidth interleaving, since the de-interleaving is performed digitally and
the interleaving is performed in the analog domain. The concept for DACs was introduced into the research
community by Laperle,23 but had been previously patented by LeCroy.24
 Digital Bandwidth Analog Bandwidth Interleaving
De-Interleaving
a) analog e)
digital h)
I
n d) I II
0 fs/2 f
b) FFT DAC 0 fs/2 fs f

DSP
0 fs/2 fs f DAC
Splitting h) t
c)
1:x CLK
f) g)
I II
II * II II *
0 fs/2 fs f fs/2 f f
0 0 fs/2 fs

Figure 3. Block diagram of an ABI-DAC consisting of two DACs: The digital signal (a) is passed through an FFT (b),
split in the frequency domain (c) and each spectral sub-band is both individually processed (d) and D/A converted (e),(f).
The second sub-signal is low-pass filtered and up-converted to its native frequency position (g). A diplexer combines and
filters both sub-signals in order to form the analog representation (h) of the digital signal (a).

A conceptual block diagram of an ABI-DAC is presented in Fig. 3 with two DACs each running at a sample
rate of fs . The signal is processed both in the digital domain, called digital bandwidth de-interleaving, and
in the analog domain, called analog bandwidth interleaving (ABI). For the digital bandwidth de-interleaving,
the digital signal (a) is passed through a Fourier transform and the spectrum is shown schematically in (b).
The spectrum is split into two sub-spectra (c) in order to feed the corresponding sub-signals to the DACs. The
splitting is done in accordance with the specifications of the analog components, i.e. both the DACs’ sample
rate and bandwidth, the filters’ bandwidth, the mixers’ bandwidth etc. After splitting, the frequency domain
samples of each sub-spectrum are selected and placed into the base band, whereby a digital down-conversion and
filtering is achieved implicitly.
For the analog bandwidth interleaving, the first sub-signal is generated in base band with oversampling (e),
which is denoted with lighter colors, in order to be able to remove DAC aliases with an analog filter. The
second sub-signal is generated at an intermediate frequency (f) due to digital up-conversion. This way, both
DAC aliases and the unwanted mixer sideband can be removed with analog filters. Furthermore, the signal is
generated in reversed frequency position, denoted by the superscript *, since the lower side band (LSB) of the
radio frequency (RF) mixer is utilized. Note, that the uppper side band could be used as well as described in25
and shown experimentally in,26 where two mixers were used. After the low pass filter removing DAC aliases, the
second sub-signal is up-converted to its native frequency location (g). Both sub-signals are then combined with
a diplexer: the first sub-signal is thereby filtered with a low-pass characteristic in order to suppress DAC aliases
and the second sub-signal is thereby filtered with a band-pass characteristic in order to suppress the unwanted
mixer side band. The resulting signal (h) is the analog representation of the digital signal (a).
Recently, this concept has been investigated in multiple publications. We27 provided a thorough theoretical
description of the ABI-DAC concept and experimentally verified it by interleaving two frequency bands generated
by two DACs with sampling rates in the MHz range. Hereby, a specially designed DSP algorithm was used in
order to operate the DACs without oversampling, while still being able to cancel image components. A first
high-bandwidth experiment was shown by Chen26 with a 240 GS/s sample rate 100 GHz bandwidth ABI-DAC
based on three DACs each running at 80 GS/s. With a triplexer, three frequency bands, which were generated
with oversampling and digital up-conversion, respectively, were combined in order to form the electrical 100 GHz
spectrum. An optical binary phase shift keying (BPSK) signal with 140 GBd could be generated, and was
transmitted in a back-to-back experiment with a high implementation penalty. Sichma28 showed the effects
and the abilities of frequency domain equalization for an ABI-DAC. A similar concept, whereby the electrical
frequency bands were processed individually, was shown in.29 A combined DMT and orthogonal frequency
 a)
DACs 10dB
fc=22.5 GHz
1 b)
Real-Time 0

Magnitude (dB)
-10
88 GS/s
DSP
-20

8 bit Scope -30

-40
-50

fc=43 GHz 160 GS/s -60

-70
2 62 GHz -80
0 10 20 30 40 50 60 70 80
Frequency (GHz)
fc=26.5 GHz 80 GBd
2.75 GHz c)
PAM2 PAM4 d)

Magnitude (dB)
1
1:16 0
Frequency -1

Generator -2
-3
0 10 20 0 10 20
0 10 20 30 40
44 GHz Time (ps) Time (ps)
Frequency (GHz)

Figure 4. a) Experimental setup for the ABI-DAC consisting of two DACs; b) Output spectrum of the ABI-DAC; c)
PAM2 and PAM4 eye diagram at 80 GBd; d) Frequency response of the compensated ABI-DAC.

division multiplexing (OFDM) signal could be transmitted over a short optical intensity modulation and direct
detection (IM/DD) link with 178 Gb/s.
The ABI concept offers very high bandwidths and doesn’t require technological advances in the component
design since broad bandwidth mixers and filters are available as of today; the concept rather relies on DSP
algorithms in the frequency domain in order to equalize the asymmetrical analog paths. In principle, the concept
is scalable to an arbitrary amount of DACs. However, the individual sub-signals are subject to high peak-to-
average power ratio (PAPR) values, since their properties are similar to OFDM signals. Though, a very high
bandwidth could be achieved, the necessity for pre-equalization reduces the resolution of the combined ABI-DAC.
For permanent self-calibration of the analog processing system, an ADC is required in the DAC. Furthermore,
there are inherent interdependencies between multiple system parameters such as the data block length, the
sample rate of the DACs, and the frequencies of the local oscillators (LOs) as we showed in.25 The dependence
on the analog bandwidth of filters and mixers limits the flexibility of the concept.

4. ABI-DAC - EXPERIMENTAL RESULTS

In order to demonstrate the concept of ABI, we set up an ABI-DAC with a combined sampling rate of 176 GS/s
consisting of two DACs, each having a 3 dB bandwidth of 20 GHz and running at a sample rate of 88 GS/s. We
generate an 80 GBd signal with an electrical bandwidth of 40 GHz.
The experimental setup is visualized in Fig. 4 a). The digital signal is processed in a DSP unit. First, the
digital signal is pulse-shaped with a raised-cosine filter with a roll-off-factor of 0.05 and then split split into
two sub-bands.25 Contrary to the splitting visualized in Fig. 3, the signal is split with two overlapping raised
cosine characteristics, each with a roll-off-factor of 0.0625, in order to reduce the PAPR of both sub-signals.
The sub-signals are then individually pre-equalized with a zero-forcing (ZF)-frequency domain equalizer (FDE),
which cancels amplitude and phase mismatches between the two asymmetrical analog paths. The delay between
the two sub-signals is compensated in a bulk manner by shifting one of the sub-signals by an integer sample
number.
For the concept, it is important, that the LO and the DAC clock are phase locked. Contrary to Chen,26
where the LOs were generated by a DAC, we generate the LO with a frequency generator. The 44 GHz LO signal
of the frequency generator is further split and divided by 16 in order to generate the 2.75 GHz clock signal for
the DACs. For a practical realization, our approach has advantages in terms of cost, however, the phase locked
loop (PLL) in the DAC chip imposes additional jitter constraints.
Two DACs, each running at 88 GS/s, are used to generate the two sub-signals. The first sub-signal contains
frequency components from DC to 22.4 GHz and the second sub-signal contains frequency components from DC
to 21.6 GHz. The first sub-signal (blue) is attenuated by 10 dB in order to ensure an equal attenuation in both
 (a) (c)
0 30

Magn. (dB)

SNR (dB)
25
-10 20
-20 15
-30 10
5
-40 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
(b) Frequency (GHz) (d)
10 30
Phase (rad)

SNR (dB)
5 25
20
0 15
-5 10
5
-10 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Frequency (GHz) Frequency (GHz)

Figure 5. a), b) ABI-DAC frequency response (blue: DAC1→output, red: DAC2→output); c),d) SNR for the uncom-
pensated and the compensated case.

analog paths. The second sub-signal (red) is filtered with a low-pass filter with a 3 dB bandwidth of 26.5 GHz
in order to suppress DAC aliases. This sub-signal is further up-converted with an RF mixer to 44 GHz. Both
signals are combined in the diplexer, which has a crossover frequency of 22.5 GHz. The low-pass characteristic
suppresses the DAC aliases of the first sub-signal. After the diplexer a low-pass filter with a 3 dB bandwidth
of 43 GHz suppresses both the LO, which has been feed through by the RF mixer and the upper side-band
generated by the RF mixer. The combined signal is acquired with a 160 GS/s real-time oscilloscope with 62 GHz
analog bandwidth.
The flat output spectrum of the ABI-DAC is shown in Fig. 4 b). The strong LO at 44 GHz can be observed,
which couldn’t be suppressed sufficiently by the low pass filter. The resulting eye diagrams for both a PAM-2
and a PAM-4 signal, each at 80 GBd, are visualized in Fig. 4 c). A clear eye opening for the PAM-2 signal and a
degraded eye for the PAM-4 signal can be seen with an eye amplitude of 30 mV. Note, that the LO was digitally
filtered prior to plotting the eye diagrams. The residual DAC frequency response is shown in Fig. 4 d). In the
range from DC to 22 GHz the magnitude looks fairly flat. At higher frequencies, there is a strong ripple in the
magnitude. Hence, the compensation cannot compensate all effects. The drop-off at 38 GHz can be attributed
to the raised-cosine pulse shaping.
In Fig. 5 a),b) both the magnitude and phase of the ABI-DAC frequency response are shown. We obtained
the frequency response from the impulse response, which was estimated with a least squares (LS) 2 × 1 multiple-
input multiple-output (MIMO) channel estimation in the time domain. We observe a 9 dB drop for the path
from the first DAC to the output (blue) and some ripple on the path from the second DAC to the output (red).
The phase has a fairly linear characteristic in the frequency ranges, where substantial magnitude components
are present.
In Fig. 5 c), d) the signal-to-noise ratio (SNR) is plotted with respect to the frequency for the uncompensated
and the compensated ABI-DAC. It was obtained from an error vector magnitude (EVM) estimation based on
a DMT modulation with 10248 sub-carriers, each modulated with 4-quadrature amplitude modulation (QAM).
In c) the SNR for the uncompensated channel is shown, which is in the range of 17 to 30 dB for the first
sub-signal and between 15 and 22 dB for the second sub-signal. There is a strong notch at 22.5 GHz equal
to the cross-over frequency of the diplexer. Furthermore, there is a strong ripple in the SNR, as observed for
the frequency response in a). This ripple is caused by either by the mixer’s non-linear behavior, the mixer’s
frequency response or by reflections in the setup. In Fig. 5 d) the SNR for the compensated ABI-DAC is shown.
The SNR characteristic is flattened, but the strong notch at 22.5 GHz is still visible.
 5. CONCLUSION
In this paper, we presented the current status of commercially available high-speed DACs and AWGs as well as
current research DAC ICs. Due to the high commercial interest, there is virtually no difference in performance
between research results and commercial available components.
Moreover, we evaluated multiple DAC interleaving concepts, including TI-DAC, MUX-DAC and ABI-DAC,
regarding their ability to increase the DAC’s performance in terms of sample rate and analog bandwidth. TI
increases only the sample rate, thereby extending the usable bandwidth; however the analog bandwidth remains
constant. With both MUX-DAC and ABI-DAC both the sample rate and the bandwidth can be extended.
The ABI-DAC requires advanced DSP algorithms in order to equalize the asymmetrical analog paths, and the
MUX-DAC needs a broad bandwidth analog MUXs. The ABI-DAC concept is further constraint due to the
interdependence of various system parameters, such as block length, i.e. number of data samples, sample rate,
symbol rate and the specifications of the employed analog components.
We experimentally verified the ABI-DAC concept with two DACs and generated both an electrical 80 GBd
PAM-2 and PAM-4 signal with 40 GHz electrical bandwidth. The results indicate that serious improvements
are necessary for a commercial application. There are strong degradations in the up-converted sub-signal, which
can be attributed to the mixer or to reflections in the setup. The LO’s suppression need to be improved, e.g.
by a better suited low pass filter following the diplexer, or a stronger LO feed through suppression in the mixer.
Furthermore, an amplifier could be placed after the mixer in order to compensate the mixer’s loss. The setup
will be further used in order to deeply analyze the observed impairments.

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