{ 2 )

Code : 105401/106401
to
{b}) The bus used to connect the monitor
the CPU is
B.Tech 4th Semester Exam., 2022
(i) PCI bus
{ New Course ) (ii) SCSI bus °

fiii) memory bus

COMPUTER ORGANIZATION AND
fiv} ram bus
ARCHITECTURE

alternate way of writing the

Time : 3 hours Full Marks : 70 (c) The
instruction, ADD #5, R1 is
Instructions :
f) ADD [SIRI
(i) The marks are indicated in the right-hand margin. fii) ADDI5,R1; +
fii) There are NINE questions in this paper. fii) ADDIME 5,[R1];
flit) Attempt FIVE questions in all. is no other way
(iv) There
jiv) Question No. 1 is compulsory.
{d) The instruction fetch phase ends with
1. Choose the correct answer of the following fi) placing the data from the address
(any seven) : 2x7=14 in MAR into MDR
(a) The 8-bit encoding format used to store (ii) placing the address of the data into
data in a computer is MAR
fi} ASCH fiti} completing the execution of the
data and placing its storage address
(ii) EBCDIC into MAR
(iii) ANCI (iv) decoding the data in MDR and
(iv) USCH “ placing it in IR

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 (3 ) ( 4)

the addresses
(e) For converting a virtual address into (A) Which table handle stores
sub-routines?
the physical address, the programs are of the interrupt handling
divided into
fi) Interrupt-vector table
(i) pages - table
ju) Vector
(it) frames (ui) Symbol link table

(tii) segments fiv) None of the above

(tv) blocks data of

(i) The situation wherein the
operands are not available is called
The transfer of large chunks of data data hazard -
fi)
with the involvement of the processor is
done by (ii) stock

(i) DMA controller ~ (iui) deadlock

fiv) structural hazard
(a) arbitrator

fii) user system programs 0) The DMA controller has registers.

ftu) None of the above (i) 4

(ii) 2
{g) The computer architecture aimed at fiit) 3
reducing the time of execution of
instructions is fiv) 1
ft) CISC
List and briefly define the main
fw RISC .- structural components of a computer. 7
(iti) ISA
(b) Discuss the design and logic of a.
fiv) ANNA microprogram sequence. 7

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 ( 5 ) ( 6 )

a Consider a hypothetical 32-bit micro- fa) Calculate (72530-13250) using ten’s

processor having 32-bit instructions complement arithmetic. Assume rules
composed of two fields—the first byte similar to those for two’s complement
contains the opcode and the remainder the arithmetic. 7
immediate operand or an operand address. {b) List and briefly explain five important
directly instruction set design issues. 7
ja} What is the maximum !
addressable memory capacity in
bytes)? The x86 architecture includes an instruc-
tion called decimal adjust after addition
{b} Discuss the impact on the system (DAA). DAA performs the following sequence
speed if the microproc essor bus has— of instructions :

fi} a 32-bit local address bus and a if((AL AND OFH)>9) OR (AF = 1) then
16-bit local data bus, or AL + AL +6;
fii) a 16-bit local address bus and a AF <1;
16-bit local data bus. else
AF <0;
{fc} How many bits are needed for the
endif;
program counter and the instruction
14 if (AL > 9FH) OR (CF = 1) then
register?
AL « AL+60H;
CF <—1;
else
fa) A set-associative cache has a block size
of four 16-bit words and a set size of 2. CF <0;
The cache can accommodate a total of endif.
4096 words. The main memory size
that is cacheab le is 64K 32 bits. Design “H” indicates hexadecimal. AL is an 8-bit
the cache structure and show how the register that holds the result of addition of
processor’s addresses are interpreted. two unsigned 8-bit integers. AF is a flag set
if there is a carry from bit 3 to bit 4 in the
(b) Explain two techniques for enhancing result of an addition. CF is a flag set if there
the performance of computers with is a carry from bit 7 to bit 8. Explain the
multiple execution pipelines. 7 function performed by the DAA instruction. 14

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yaa
 ( 7 ) ( 8 )

} A non-pipelined processor has a clock rate 9. Let a be the percentage of a program code
of 25GHz and an average CPI (cycles that can be executed simultaneously by n
instruction) of 4. An upgrade to the processors in a computer system. Assume
per
processor introduces a five-stage pipeline. that the remaining code must be executed
However, due to internal pipeline delays, sequentially by a single processor. Each
such as latch delay, the clock rate of the processor has an execution rate of x MIPS.
new processor has to be reduced to 2 GHz. ; ;
fa) Derive an expression for the effective

(a) What is the speedup achieved for a MIPS rate when using the system for
typical program? exclusive execution of this program, in
terms of n, a and x.

(b} What is the MIPS rate for each (b) If n=16 and x= 4 MIPS, determine
processor? 14 the value of that will yield a system
performance of 40 MIPS. 14

8. ja) Briefly explain the two basic kt hk

approaches used to minimize register-
memory operations on RISC machines. 7

{b) A computer has 16 registers, an ALU

with 32 operations, and a shifter with 8
operations, all connected to a common
bus sytem.

fi) Formulate a control word for

micro-operation.

ffi) Show the bits of the control word

that specify the micro-operatian
R4< R5+K6. 7

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