STF26NM60N

N-channel 600 V, 0.135 Ω typ., 20 A MDmesh™ II

Power MOSFET in a TO-220FP package
Datasheet - production data

Features
Order code VDS RDS(on) max ID
STF26NM60N 600 V 0.165 Ω 20 A

 100% avalanche tested

 Low input capacitance and gate charge
 Low gate input resistance

Applications
TO-220FP  Switching applications

Figure 1: Internal schematic diagram Description

This device is an N-channel Power MOSFET
developed using the second generation of
D(2) MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the
company’s strip layout to yield one of the world’s
lowest on-resistance and gate charge. It is
therefore suitable for the most demanding high
G(1) efficiency converters.

S(3)

AM01475v1_no Tab_noZen

Table 1: Device summary

Order code Marking Package Packaging
STF26NM60N 26NM60N TO-220FP Tube

December 2016 DocID030178 Rev 1 1/13

This is information on a product in full production. www.st.com
Contents STF26NM60N

Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 TO-220FP package information ...................................................... 10
5 Revision history ............................................................................ 12

2/13 DocID030178 Rev 1

STF26NM60N Electrical ratings

1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage 600 V
VGS Gate-source voltage ±30 V
ID(1) Drain current (continuous) at TC = 25 °C 20 A
ID(1) Drain current (continuous) at TC = 100 °C 12.6 A
(1)(2)
IDM Drain current (pulsed) 80 A
PTOT Total dissipation at TC = 25 °C 35 W
(3)
dv/dt Peak diode recovery voltage slope 15 V/ns
Insulation withstand voltage (RMS) from all three leads to external
VISO heat sink 2500 V
(t = 1 s; TC = 25 °C)
Tstg Storage temperature range
-55 to 150 °C
Tj Operating junction temperature range

Notes:
(1)Limited by package.
(2)Pulse width limited by safe operating area.
(3)I
SD ≤ 20 A, di/dt ≤ 400 A/µs, VDS(peak) ≤ V(BR)DSS, VDD ≤ 80% V(BR)DSS

Table 3: Thermal data

Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case 3.6 °C/W
Rthj-amb Thermal resistance junction-ambient 62.5 °C/W

Table 4: Avalanche characteristics

Symbol Parameter Value Unit
IAS Single pulse avalanche current (pulse width limited by Tjmax) 6 A
Single pulse avalanche energy
EAS 610 mJ
(starting TJ=25 °C, ID=IAR, VDD=50 V)

DocID030178 Rev 1 3/13

Electrical characteristics STF26NM60N

2 Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5: On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
Drain-source
V(BR)DSS ID = 1 mA, VGS = 0 V 600 V
breakdown voltage
VGS = 0 V, VDS = 600 V 1
Zero gate voltage drain
IDSS VGS = 0 V, VDS = 600 V, µA
current 100
TC= 125 °C (1)
IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±0.1 µA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V
Static drain-source on-
RDS(on) VGS = 10 V, ID = 10 A 0.135 0.165 Ω
resistance

Notes:
(1)Defined by design, not subject to production test.

Table 6: Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance - 1800 - pF
Coss Output capacitance VDS = 50 V, f = 1 MHz, - 115 - pF
Reverse transfer VGS = 0 V
Crss - 6 - pF
capacitance
Equivalent output
Coss eq. (1) VGS = 0 V, VDS = 0 to 480 V - 310 - pF
capacitance
Qg Total gate charge VDD = 480 V, ID = 20 A, - 60 - nC
Qgs Gate-source charge VGS = 10 V - 8.5 - nC
(see Figure 14: "Test circuit for
Qgd Gate-drain charge gate charge behavior") - 30 - nC
RG Gate input resistance f=1 MHz, ID=0 A - 2.8 - Ω

Notes:
(1)C is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS
oss eq.
increases from 0 to 80% VDS

Table 7: Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 300 V, ID = 10 A, - 13 - ns
RG = 4.7 Ω, VGS = 10 V
tr Rise time - 25 - ns
(see Figure 13: "Test circuit for
td(off) Turn-off delay time resistive load switching times" - 85 - ns
and Figure 18: "Switching time
tf Fall time waveform") - 50 - ns

4/13 DocID030178 Rev 1

STF26NM60N Electrical characteristics
Table 8: Source-drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD(1) Source-drain current - 20 A
Source-drain current
ISDM(2) - 80 A
(pulsed)
VSD(3) Forward on voltage ISD = 20 A, VGS = 0 V - 1.5 V
trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs - 370 ns
Qrr Reverse recovery charge VDD = 60 V - 5.8 µC
(see Figure 15: "Test circuit for
IRRM Reverse recovery current inductive load switching and - 31.6 A
diode recovery times")
trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs - 450 ns
Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C (see - 7.5 µC
Figure 15: "Test circuit for
IRRM Reverse recovery current inductive load switching and - 32.5 A
diode recovery times")

Notes:
(1)Pulse width limited by package.
(2)
Pulse width limited by safe operating area.
(3)Pulsed: pulse duration = 300 µs, duty cycle 1.5%

DocID030178 Rev 1 5/13

Electrical characteristics STF26NM60N
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance

Figure 4: Output characteristics Figure 5: Transfer characteristics

Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance

6/13 DocID030178 Rev 1

STF26NM60N Electrical characteristics
Figure 8: Capacitance variations Figure 9: Source-drain diode forward characteristics

Figure 10: Normalized gate threshold voltage vs Figure 11: Normalized on-resistance vs temperature
temperature

Figure 12: Normalized V(BR)DSS vs temperature

DocID030178 Rev 1 7/13

Test circuits STF26NM60N

3 Test circuits
Figure 13: Test circuit for resistive load Figure 14: Test circuit for gate charge
switching times behavior

Figure 15: Test circuit for inductive load Figure 16: Unclamped inductive load test
switching and diode recovery times circuit

Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform

8/13 DocID030178 Rev 1

STF26NM60N Package information

4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

DocID030178 Rev 1 9/13

Package information STF26NM60N
4.1 TO-220FP package information
Figure 19: TO-220FP package outline

10/13 DocID030178 Rev 1

STF26NM60N Package information
Table 9: TO-220FP package mechanical data
mm
Dim.
Min. Typ. Max.
A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1
F1 1.15 1.70
F2 1.15 1.70
G 4.95 5.2
G1 2.4 2.7
H 10 10.4
L2 16
L3 28.6 30.6
L4 9.8 10.6
L5 2.9 3.6
L6 15.9 16.4
L7 9 9.3
Dia 3 3.2

DocID030178 Rev 1 11/13

Revision history STF26NM60N

5 Revision history
Table 10: Document revision history
Date Revision Changes
13-Dec-2016 1 First release. Part number previously included in datasheet DocID15642

12/13 DocID030178 Rev 1

STF26NM60N

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DocID030178 Rev 1 13/13