Please click on paper title to view Visual Supplement.

ISSCC 2008 / SESSION 24 / ANALOG POWER TECHNIQUES / 24.5

24.5 A 0.9V 0.35µm Adaptively Biased CMOS LDO nant pole generated at VEA tracks with the GBW and the regulator
Regulator with Fast Transient Response remains stable as IOUT varies.

Figure 24.5.2 shows a conventional current mirror CM and the

Yat-Hei Lam, Wing-Hung Ki
SCM. The CM achieves a high current gain by using a large tran-
Hong Kong University of Science and Technology, Kowloon, China sistor aspect ratio. Speed is limited by the large time constant of
Cg/gmIN, where gmIN is the transconductance of the diode-connected
Portable applications often need multiple voltages controlled by a input transistor MIN, and Cg is the total equivalent gate capaci-
power management IC to power up many functional blocks [1]. A tance of both MIN and MOUT. The proposed SCM utilizes a low-volt-
switching pre-regulator is usually followed by a low dropout (LDO) age transient-enhancing circuit that provides extra transient cur-
regulator to provide a regulated power source for noise-sensitive rent to Cg to enhance the current mirroring speed. A very small on-
blocks. The LDO regulator has to be stable for all load conditions chip compensation resistor, RZ = 250Ω, is sufficient to stabilize the
and frequency compensation is usually needed to stabilize the reg- transient-enhancing circuit. In steady state, VG = VB2 and VBOOST
ulation loop [2, 3]. The output voltage droop due to rapid and large regulates MB1 such that IBOOST = IIN = IOUT/K. If there is a rapid
load changes could be minimized with a fast regulation loop, such increase of IIN, which would reduce the drain currents of MB5 and
that functional blocks powered by the same LDO regulator would MB6 quickly, MB3 and MB4 react with a delay by design. The sudden
have low crosstalk noise. mismatch in the drain currents of MB6 and MB4 pulls VBOOST up to
increase IBOOST. The node voltage VB2 is then pulled down first fol-
LDO regulators with fast load transient response were demon- lowed by VG due to the RC delay generated by RZ and Cg. The volt-
strated in [4] and [5]. In [4], the regulator was implemented in an age difference across RZ is amplified by MB3 through MB6 and pulls
advanced 90nm CMOS process and the fast feedback loop used a VBOOST further up to provide extra current such that IBOOST > IIN to
small 600pF filter capacitor for stability. The fast response compensate for the delay and to stabilize the transient-enhancing
required a large quiescent current of 6mA to deliver an output cur- loop. A similar mechanism applies to a rapid decrease of IIN.
rent of 100mA and the 10%P-P output voltage variations were rela-
tively large. In [5], the power PMOS pass transistor was driven by Figure 24.5.3 shows the frequency responses of the SCM and the
a dynamically biased super source-follower as a buffer for both sta- CM for comparison. At a light load of ILOAD = 1mA, the CM has a
bility and speed and the buffer had to operate at a voltage higher phase shift of 60° at 100kHz, but the SCM has the same phase
than is usually required by low-power digital circuits. The bias shift at a much higher frequency of 2MHz. The minor gain peaking
current of the error amplifier was fixed, and its speed and current at 2.5MHz is caused by the <90° phase margin of the transient-
consumption are difficult to be optimized simultaneously. The reg- enhancing loop. It occurs at a frequency much higher than the
ulator also used a 10pF capacitor for compensation, which used sil- GBW of the regulation loop and the overall stability of the regula-
icon area. tor is not affected. At a full load of ILOAD = 50mA, both the band-
widths of the SCM and the CM are larger due to the increase in
A low-voltage fast transient-response LDO regulator using an the bias currents. The CM has a phase shift of 60° at 2MHz, and
inexpensive 0.35μm CMOS process is presented in this paper. It the SCM has the same phase shift at 8MHz, which is high enough
features a current-efficient adaptively biased regulation scheme for the regulator to be stabilized with a 1µF filter capacitor.
using a low-voltage high-speed super current mirror and does not
require a compensation capacitor (Fig. 24.5.1). It is stabilized by a Figure 24.5.4 shows the measured load transient response. The
low-cost low-ESR ceramic filter capacitor of 1µF. The adaptively load current is switched between 0µA and 50mA with rise and fall
biased error amplifier EA (MA1 to MA8) drives a small transconduc- times of 10ns. No overshoot is observed for the switching from
tance cell, MA9, to modulate the output current IOUT through a 50mA to 0µA, as the regulation loop had a large bias current ini-
transient-enhanced super current-mirror (SCM). tially, giving a high unity gain frequency. For the switching from
0µA to 50mA, a minor undershoot occurs due to the low bias cur-
The PMOS differential input stage of the EA (MA1 and MA2) is driv- rent at IOUT = 0mA. However, the total output voltage variation is
en by NMOS level shifters (MA3 and MA4). The level shifters allow only 6.6mV (0.73%P-P) and is much smaller than those in [4] and
the EA to function properly at a VDD that is only 150mV higher [5].
than VOUT. The PMOS differential pair and the NMOS active loads
(MA5 and MA6) give a ground-referenced voltage, VEA, to drive MA9. Figure 24.5.5 shows the measured quiescent current IQ versus
The bias currents of the level shifters and the differential pair are IOUT. At a high ILOAD, IQ increases linearly, demonstrating a work-
proportional to IOUT. As IOUT increases, the outputs of the level ing adaptive-biasing scheme. At no load, the EA and the SCM are
shifters VREF, and VOUT, decrease, which compensates for the kept active by a total bias current of only 4.04µA. Figure 24.5.6
increase of the source-gate voltages of MA1 and MA2. Thus, the tabulates all the important parameters of the proposed regulator
source node of the differential pair, VS, remains constant as IOUT in comparison with those of [4] and [5]. The die micrograph is
varies, and MADB of the SCM that provides the bias current IADB to shown in Fig. 24.5.7. The regulation loop occupies only 24% of the
the EA will not be forced into the triode region at heavy loads. The total active area.
current densities of MA5 and MA6 are designed to be half that of MA9
References:
such that the adaptive-biasing loop has a gain <1 for stable and [1] C. Shi, B. C. Walker, E. Zeisel et al., “A Highly Integrated Power
robust operation. The current sources IB1 through IB4 are essential Management IC for Advanced Mobile Applications,” IEEE J. Solid-State
to keep the LDO regulator active even when IOUT is zero. Circuits, pp. 1723-1731, Aug. 2007.
[2] G. A. Rincon-Mora and P. E. Allen, “A Low-Voltage, Low Quiescent
For loop stability, the frequency responses of the EA and the SCM Current, Low Drop-out Regulator,” IEEE J. Solid-State Circuits, pp. 36-44,
Jan. 1998.
should have low phase shifts at frequencies lower than the unity [3] C. K. Chava and J. Silva-Martínez, “A Frequency Compensation Scheme
gain frequency. The gain bandwidth product GBW is for LDO Voltage Regulators,” IEEE T. CAS I, pp. 1041-1050, June 2004.
AOL/(2πROUTCOUT), where AOL and ROUT are the low-frequency open- [4] P. Hazucha, T. Karnik, B. A. Bloechel et al., “Area-Efficient Linear
loop gain and output resistance of the regulator (including RLOAD), Regulator With Ultra-Fast Load Regulation,” IEEE J. Solid-State Circuits,
respectively. With COUT = 1µF and AOL = 50dB, the GBW with a full pp. 933-940, Apr. 2005.
[5] M. Al-Shyoukh, H. Lee and R. Perez, “A Transient-Enhanced Low-
load of 50mA (RLOAD = 18Ω for VOUT = 0.9V) is a few MHz, while at Quiescent Current Low-Dropout Regulator With Buffer Impedance
light loads it could drop to a few tens of Hz. The large current gain Attenuation,” IEEE J. Solid-State Circuits, pp. 1732-1742, Aug. 2007.
of K = 1000 for the SCM allows the use of a small MA9 in minimiz-
ing the parasitic capacitance at VEA. Due to adaptive biasing, the
EA has low power consumption at light loads, and the non-domi-

442 • 2008 IEEE International Solid-State Circuits Conference 978-1-4244-2011-7/08/$25.00 ©2008 IEEE

Please click on paper title to view a Visual Supplement.

 Please click on paper title to view Visual Supplement.

ISSCC 2008 / February 6, 2008 / 10:30 AM

Figure 24.5.2: A conventional current mirror and the super current mirror with
Figure 24.5.1: LDO regulator. the low-voltage transient-enhancing circuit.

Figure 24.5.3: Frequency response of the super current mirror. Figure 24.5.4: Measured load transient response.

24

Figure 24.5.5: Measured IQ versus ILOAD and current efficiency (ILOAD/IQ) versus Figure 24.5.6: Performance summary and comparison with previously pub-
ILOAD. lished LDO regulators.

Continued on Page 626

DIGEST OF TECHNICAL PAPERS • 443

Please click on paper title to view a Visual Supplement.

 Please click on paper title to view Visual Supplement.

ISSCC 2008 PAPER CONTINUATIONS

Figure 24.5.7: Die micrograph.

626 • 2008 IEEE International Solid-State Circuits Conference 978-1-4244-2011-7/08/$25.00 ©2008 IEEE

Please click on paper title to view a Visual Supplement.