This article has been accepted for inclusion in a future issue of this journal.

Content is final as presented, with the exception of pagination.

IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

A 1.24 μA Quiescent Current NMOS Low Dropout

Regulator With Integrated Low-Power Oscillator-
Driven Charge-Pump and Switched-Capacitor
Pole Tracking Compensation
Raveesh Magod , Student Member, IEEE, Bertan Bakkaloglu, Fellow, IEEE, and Sanjeev Manandhar

Abstract— Supply regulation using low quiescent current linear capacitor stabilized low dropout (LDO) regulators powering
regulators helps in extending the battery life of power aware such applications must have low-power dissipation for better
applications with very long standby time. A 1.24 µA quies- efficiency during light load current (ILOAD ) condition while
cent current NMOS low dropout (LDO) that uses a hybrid
bias current generator (HBCG) which boosts the bias current maintaining good transient response to switching load current
dynamically and adaptively to improve the transient response is with minimum variation in their output voltage (VOUT ). The
presented in this paper. A bias-current scalable error amplifier undershoot/overshoot voltage (V O ) of an LDO with output
with an on-demand pull-up/pull-down buffer drives the NMOS capacitor (CLOAD ) is given by [3] as follows:
pass device. The error amplifier is powered with an integrated
dynamic frequency charge pump to ensure low dropout voltage. ILOAD ILOAD
A low-power relaxation oscillator (LPRO) generates the charge VO ≈ tR = (tBW + tSR ) (1)
CLOAD CLOAD
pump clocks. A novel switched-capacitor pole tracking (SCPT)
compensation scheme is proposed to ensure stability up to where t R is the recovery time to load current transients.
maximum load current of 150 mA with a low-ESR 1 µF output This recovery time is governed by the small-signal propagation
capacitor. Designed in a 0.25 µm CMOS process, the LDO has delay associated with the LDO loop bandwidth (tBW ) and the
an output voltage range of 1–3 V, a dropout voltage of 240 mV,
and a core area of 0.11 mm2 . large signal delay associated with the limited slew rate at the
parasitic gate capacitance of pass device (tSR ). Both tBW and
Index Terms— Adaptive biasing, dynamic biasing, hybrid bias- tSR can only be reduced at the expense of increased power
ing, low I Q low dropout (LDO), NMOS LDO, on-demand buffer,
relaxation oscillator, switched-capacitor tracking compensation. consumption.
In order to ensure low no-load quiescent current (I Q )
while achieving fast transient response, various current scal-
I. I NTRODUCTION ing schemes have been presented. Adaptive biasing schemes
scale the bias current proportional to ILOAD as presented
P ORTABLE devices, low-power micro-controller unit
system-on-chip (SoC) ICs, always-on Internet-of-things
(IoT) sensor systems, and biomedical devices rely on var-
in [4] and [5]. This approach gives the benefit of better slew
rate and better loop bandwidth at higher ILOAD. However,
ious power saving schemes to increase their battery life. due to low bias current at light load conditions, the recovery
Sleep/standby mode operation, dynamic supply voltage scal- time and undershoot for zero to full-load transition of low-
ing, and on/off supply schemes have been presented in [1] and I Q LDOs, cannot be minimized with this scheme as the
[2] for low-power operation where event-driven, on-demand, loop response is slow to begin with. Dynamic slew rate
fast wake-up schemes are used to ensure fast response time. enhancement schemes are presented in [6]–[11] where the
Due to these schemes, the standby power consumption of slew rate at the gate of the pass device is scaled only during
such systems is dominated by their supply regulators. Such the load transient event, thereby reducing undershoot voltage.
supply regulators need to have two critical features: very low- This technique alone is very effective in output capacitor-less
power consumption during standby mode and fast response LDOs where the parasitic gate capacitance tends to decide the
to transient load currents during fast wake-up. Thus, output dominant pole as well as the required slew rate. In general,
low I Q output capacitor-less LDOs offer limited maximum
Manuscript received August 28, 2017; revised January 5, 2018; accepted load current capability and suffer from large undershoot
March 19, 2018. This paper was approved by Associate Editor Pavan
Kumar Hanumolu. This work was supported by Texas Instruments, Tucson, voltage during zero to full-load current step. Lu et al. [12]
AZ 85711 USA. (Corresponding author: Raveesh Magod.) present a fully integrated NMOS LDO which generates a
R. Magod, and B. Bakkaloglu are with the School of Electrical and low-ripple regulated output voltage by efficiently managing
Computer Engineering, Arizona State University, Tempe, AZ 85287 USA
(e-mail: [email protected]; [email protected]). the available supply voltage for the error amplifier and the
S. Manandhar is with Texas Instruments Inc., Tucson, AZ 85711 USA switched-capacitor dc–dc converter output as the supply for
(e-mail: [email protected]). pass device. However, due to unavailability of a good output
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. storage capacitance in this fully integrated scheme, it suffers
Digital Object Identifier 10.1109/JSSC.2018.2820708 from large undershoot voltage for a relatively small load
0018-9200 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

with earlier presented current scaling techniques. Low dropout

voltage for this NMOS LDO is ensured by powering the
error amplifier with a charge-pump voltage doubler. Native
NMOS which offers negative or close to zero threshold voltage
may seem like a better pass device alternative to using a
charge-pump along with regular NMOS pass device. However,
additional mask cost, larger area due to higher minimum
length, and higher levels of drain to source leakage current
are major limitations of native NMOS which make the charge-
pump and regular NMOS a preferable choice especially in
such low-I Q LDOs. A dynamic frequency charge-pump is
employed for powering the hybrid-mode biased error amplifier,
which acts as a variable load. A very low-power relaxation
oscillator (LPRO) is proposed to generate the charge pump
clocks with clock frequency proportional to ILOAD . Switched-
capacitor pole tracking (SCPT) compensation scheme is pro-
posed for loop stability across load conditions. This LDO
Fig. 1. Block diagram of the proposed NMOS LDO. provides a maximum ILOAD of 150 mA while using a low-ESR
1 μF load capacitor (CLOAD). A low-power scaling amplifier
shifts the external reference voltage of 0.8 V to an internal
reference (V REF ) equal to the required output voltage (V OUT )
and the error amplifier is operated in unity gain configuration.
The rest of this paper is organized as follows. Analysis and
design details of the proposed HBCG circuit are presented in
Section II. Section III covers the design details of the bias-
current scalable error amplifier with buffer while Section IV
presents the design of the proposed low-power LPRO circuit.
Stability analysis and SCPT compensation scheme are pre-
sented in Section V. Section VI presents the measurement
results and Section VII draws the conclusion.

II. H YBRID B IAS -C URRENT G ENERATOR (HBCG)

Fig. 3 shows the design details of HBCG circuit. As noted
earlier, this circuit is responsible for both adaptive current
Fig. 2. Comparison of the proposed hybrid biasing scheme with previously
presented I Q scaling schemes. scaling and dynamic current scaling. Load-dependent adaptive
current is obtained by MN1, which mirrors a fraction (1:4000)
current transient. Recently, LDOs which employ dynamic slew of the pass device (MNP) current. In order to ensure accurate
enhancement along with adaptive biasing have been reported mirroring, the source voltage of MN1 needs to be equal to
in [13]–[16]. Although increased slew rate helps in reducing VOUT . This is achieved using the current mirrors MN2 and
tSR as shown in (1), high tBW due to limited loop bandwidth at MN3 along with MP1 and MP2. As ILOAD increases, drain–
light load currents can still limit the total recovery time t R source current in MN1 also increases and current mirror pair
for zero to full-load current transients, especially in output MN2 and MN3 ensures equal current flow in both branches,
capacitor stabilized LDOs. forcing MP1 and MP2 to have the same VGS . As the gate
This paper presents an NMOS pass-device LDO with a low terminal is common to both MP1 and MP2, the source voltage
I Q of 1.24 μA. The block diagram of this LDO is shown of MP2 which is VOUT is copied onto the source terminals of
in Fig. 1. Superior transient response, low output impedance MP1 and MN1. MN4 mirrors the final adaptive current (IADP ).
even at light load currents and lower gate parasitic capacitance At zero ILOAD, MN1 is in deep subthreshold region and does
due to smaller physical size are the three distinct advantages not conduct any current. Effectively, the entire adaptive scaling
which make NMOS a favorable choice for pass device in implementation has no contribution in the overall I Q of the
comparison to PMOS. A bias-current scalable, two-stage error LDO and serves as a major advantage in such low I Q LDOs.
amplifier with an on-demand pull-up (PU)/pull-down (PD) At startup, the gate voltage of MN2 and MN3 is pulled down to
buffer drives the pass device. A hybrid bias-current genera- ground by the diode connected MN2. However, the common-
tor (HBCG) that scales the bias current dynamically during gate voltage of both MP1 and MP2 is indeterministic at startup
load transients and adaptively with ILOAD is proposed for and if it is close to VDD , the entire adaptive scaling circuit
improved transient response. This HBCG scheme allows faster may fail to turn on even when ILOAD increases as MP1 and
I Q scaling which improves both loop bandwidth and slew rate MP2 will remain in OFF state. In order to avoid this faulty
of the error amplifier even at light ILOAD. Fig. 2 shows a case, their gate node is discharged to ground by MN5 using a
comparison of the bias-current profile of the HBCG scheme short pulse VSTUP at startup.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

MAGOD et al.: 1.24 μA QUIESCENT CURRENT NMOS LDO REGULATOR 3

Fig. 3. HBCG with on-demand output capacitor pull-down circuit circuit.

Fast dynamic current scaling is based on virtual ground error

voltage (V = VOUT −VREF ) which is obtained by monitoring
the input voltages of the error amplifier. Fast detection is
achieved by utilizing PMOS common-gate differential pair
with source terminals as inputs. As shown in the dynamic
scaling segment of Fig. 3, the input pair consists of highly
matched MP3 and MP4 transistors operating in subthreshold
region. When the LDO is in steady state, the error voltage
V ∼ = 0 and the 20 nA bias current is mirrored to generate
IDYN = 20 nA through MP3 and MP4 and MN7 and MN8 cur-
rent mirrors. However, during an output undershoot event
(V < 0) caused due sudden step-up of ILOAD , the under-
shoot in VOUT produces an increased gate drive (VSG )
for MP4 through diode connected MP3. Effectively, current
through MP4 which is biased in subthreshold region increases Fig. 4. Scaling amplifier with programmable resistor divider feedback.
exponentially and is mirrored by MN7 and MN8 resulting in
an exponential increase in IDYN . Due to the absence of high-
impedance paths, this scheme provides instantaneous current no unexpected leakage current through MN11 during steady-
scaling during load transients. state operation of the LDO. However, during VOUT overshoot,
The adaptive current (I ADP ) is added to dynamic higher gate drive (VSG ) increases the current through MP9.
current (IDYN ) and then mirrored by MP5–MP6, MP7 to This current overpowers the current source MN10 and pulls
generate the bias currents of the error amplifier (IHYB1 ) and the gate of MN11 high, thereby discharging CLOAD. This pull-
oscillator (IHYB2 ). In addition, a current-comparator-based, down circuit is triggered only when the V exceeds ∼35 mV.
on-demand pull-down circuit (PD) circuit is added to discharge Fig. 4 shows the scaling amplifier which generates the
the load capacitor (CLOAD ) during an overshoot event (V > scaled reference voltage VREF from the external reference VBG .
0) caused due to sudden step-down of ILOAD . A subthreshold It consists of simple two-stage design with a differential
biased PMOS pair MP8 and MP9, similar to that of dynamic amplifier as its first stage and a PMOS common source
scaling circuit with reversed input voltage terminals is used amplifier as its second stage driving a 2 pF output capaci-
as shown in the pull-down circuit segment of Fig. 3. In com- tance (CSA ). To keep the current branches to minimum, the
parison with MN9, a 4 times stronger current source MN10 is bias voltage (VNB ) for the tail current source (MN1) is derived
used to hold the gate of pull-down circuit device MN11 to less from MN0 of the HBCG circuit in Fig. 3 and both devices
than 15 mV which is much lower than the NMOS threshold are closely matched in layout to minimize mismatch. The
voltage of 550 mV. Such low gate voltage ensures that there is scaling amplifier is stabilized using Miller capacitance CC
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

4 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 5. Two-stage error amplifier with on-demand PU/PD buffer.

and resistor RC is used to cancel the right half-plane zero

associated with Miller compensation. Digitally programmable
resistor divider with fixed R2 and variable R1 is used to
generate VREF corresponding to the LDO output voltage range
of 1–3 V.

III. E RROR A MPLIFIER W ITH O N -D EMAND

P ULL -U P /P ULL -D OWN B UFFER
The regulation feedback loop consists of a two-stage error
amplifier which is shown in Fig. 5. The charge-pump voltage
doubler provides the supply voltage to this bias-current scal-
able error amplifier. Due to this 2 × VIN voltage supply which
can go as high as 6 V when VIN = 3.3 V, the error amplifier
Fig. 6. Small-signal equivalent circuits for determining output impedance
uses 7 V devices instead of 3.3 V devices. The pass device for active (a) PU loop and (b) PD loop of the proposed buffer.
also is a 7 V regular NMOS. The bias current (IHYB1 ) of the
error amplifier is generated by the HBCG circuit. The first
stage of the amplifier consists of a symmetrical operational on-demand fast PU as well as fast PD capability improving
transconductance amplifier (OTA). Small-signal analysis of the transient response to ILOAD step-up and step-down, respec-
this amplifier shows that the gain of the amplifier (G AMP ) tively.
and its 3 dB pole location (PAMP ) are given by At the core, the buffer consists of a PMOS source
follower (MP8). For simplicity, the PU and PD loops are
G AMP ∼
= gm MN2 ∗ (rds,MP4 ||rds,MN5) (2)
analyzed separately. Instead of a regular source follower biased
1
PAMP ∼= (3) with a fixed current source, dynamic fast PU is achieved
2π(rds,MP4 ||rds,MN5)CAMP through a negative feedback loop realized using common-gate
where CAMP is the effective load capacitance at the output stage (MN9 and MP7) and common source stage (MP9) which
of the first stage. With increase in IHYB1 , although out- constitute a cascoded flipped-voltage follower. This feedback
put impedance (rds,MP4 ||rds,MN5 ) drops, increase in gmMN2 loop not only provides the required on-demand sourcing
compensates for this drop, thereby maintaining a dc gain current to charge the gate of pass device during a load step-
higher than 50 dB for all possible IHYB1 values. However, its up but also reduces the small-signal output impedance of the
3 dB bandwidth increases proportionally with IHYB1 as PAMP buffer. The effective output impedance can be calculated using
moves to a higher frequency due to the reduction in output the small-signal equivalent diagram, as shown in Fig. 6(a) for
impedance. the PU loop. Small-signal test voltage v x is applied at the
A second-stage bias-current scalable dual-loop CMOS volt- output of the buffer with input v in shorted to ground. The
age buffer is placed in between the first stage and the pass effective output impedance is given by
device in order to increase the slew rate at the gate of the v x v x
pass device and improve the load transient response. Unlike, r0,PU = = . (4)
i x i 1 − i 2
the voltage buffer with only on-demand PU capability as
shown in [3] and super-source follower buffer with only The small-signal current +i 1 is translated to −i 1 onto
on-demand PD presented in [4], the proposed buffer achieves the CG stage MN9, drops across the equivalent impedance
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

MAGOD et al.: 1.24 μA QUIESCENT CURRENT NMOS LDO REGULATOR 5

of (rds,MP7 ||rds,MN9) and is converted to voltage v GP . This

v GP is coverted to i 2 using MP9 and is given by
i 2 = gmMP9 ∗ v GP ∼
= gmMP9 ∗ −i 1 ∗ (rds,MP7 ||). (5)
Using (4) and (5), we get
v x
r0,PU ∼
= . (6)
[1 + gmMP9 (rds,MP7 ||rds,MN9)]i 1
Substituting i 1 = gmMP8 ∗ v x , we get
1
r0,PU ∼
= . (7)
gmMP8 ∗ gmMP9 ∗ (rds,MP7 ||rds,MN9 )
Thus, the effective output impedance is reduced by a factor
of loop gain given by APU = gmMP9 ∗ (rds,MP7 ||rds,MN9) in
comparison to a simple source follower in which case it would
have been just (1/gmMP8 ), thereby pushing the parasitic pole
at the gate of pass device (PGATE ) to higher frequency. Similar
analysis can be done for the fast PD loop which is a super-
source follower formed by MP8, MN7, and MN10 as shown
in Fig. 6(b) where the effective output impedance is given by
v x v x
r0,PD = = . (8)
i x i 1 + i 2
Fig. 7. (a) Block diagram of typical relaxation oscillator. (b) Proposed LPRO
The small-signal current i 1 drops across the effective with current comparator and NMOS switch.
impedance (rds,MP8 ||rds,MN7) producing voltage v GN which
is translated to i 2 given by
PPU3 remain beyond the PU loop unity-gain bandwidth (UGB)
i 2 = gmMN10 ∗ v GN ∼
= gmMN10 ∗ i 1 ∗ (rds,MP8 ||rds,MN7 ). even at light bias-current condition providing a minimum
(9) phase margin of 45° across all load conditions. C2 (=1 pF)
Using (8) and (9) and substituting i 1 = gmMP8 ∗v x , we get acts as a glitch filter capacitor to keep the gate voltage of
MN9 constant during large signal variations at its drain and
1
r0,PD ∼
= (10) source nodes. The PD loop gain is weak compared to PU loop
gmMP8 ∗ gmMN10 ∗ (rds,MP8 ||rds,MN7) in normal operation and is dominant only during ILOAD step-
reducing the effective output impedance by a factor of loop down. It is naturally stabilized with the gate capacitance of
gain given by APD = gmMN10 ∗ (rds,MP8 ||rds,MN7). At steady MNP. As the variable biasing current IHYB1 increases with
state, gate voltage of MN10 is held at a threshold voltage lower ILOAD, the output impedance of the buffer is reduced further
than VBCG and it conducts approximately 20 nA of drain– and pushes PGATE to higher frequency.
source current as shown in Fig. 5. The entire two-stage error amplifier is powered by a cross-
The PU loop consists of three different poles coupled voltage doubler charge-pump in order to maintain a
low dropout voltage for the LDO. However, variable IHYB1
MN9 drain pole: PPU1 which biases the error amplifier, modulates the current drawn
∼ 1 from the charge pump with ILOAD and ultimately, changing
=
(rds,MP7 ||rds,MN9) ∗ C1 its 2× output voltage. In order to maintain a constant output
MNP gate pole: PGATE or PPU2 voltage of ≈ 2VIN , the charge pump clock frequency (FCLK ) is
∼ 1 modulated to counteract its load current variations. A current
=
(r0,PU ) ∗ C G,MNP tunable LPRO is proposed to generate the charge pump control
MP8 drain pole : PPU3 clocks.
∼ 1
= .
(rds,MP8 ||rds,MN7||1/gmMN9 ) ∗ Cpar
IV. L OW-P OWER R ELAXATION O SCILLATOR (LPRO)
Since r0,PU is reduced by using the cascoded flipped-voltage
follower approach, PPU2 is pushed to a higher frequency A typical relaxation oscillator architecture is shown in
even at light bias-current conditions. The effective impedance Fig. 7(a). A bias current (IBIAS ) charges the capacitor (C)
looking-in at the drain of MP8 is reduced due to the low until its voltage (VC ) exceeds a reference voltage (VREF ) at
impedance of MN9 (1/gmMN9 ). This accompanied with the which the comparator momentarily changes its output state to
low equivalent parasitic capacitance (Cpar ) at this node, ensure logic high to discharge the capacitor. As soon as the capacitor
that PPU3 is at a much higher frequency. Therefore, the entire is discharged, the comparator outputs a logic low and the same
PU loop is stabilized using C1 (=1 pF), which is connected sequence repeats periodically to produce an output clock. The
to the gate of MP9 making PPU1 the dominant pole. PPU2 and approximate output clock frequency (FCLK ) of this oscillator
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

6 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 8. Comparison of the transient profile of supply current and capacitor voltage for the proposed LPRO with other architectures.

is given by further, both VGS and VDS of MN3 reduces ensuring

IBIAS e(VGS/ηVt ) → 0 and (1 − e−(VDS/Vt ) ) → 0,
FCLK ∼
= (11) thereby exponentially reducing IDS,MN3 . The difference
2C ∗ VREF
current (IHYB2 − IDS,MN3 ) increases exponentially and
revealing that it is directly proportional to bias current.
charges the small parasitic input capacitance CPAR . Therefore,
Although a preferred option for low-power clock generation,
V D increases exponentially from zero and output of I1 changes
the major limitation for nanopower operation of this circuit
to logic low turning on MP2. However, I2 is designed to be
comes from the power consumption in comparator. This com-
weak so that its output transition to logic high happens after
parator typically consists of just a Schmitt trigger or an OTA
a small delay. During this momentary period, both MP1 and
followed by a Schmitt trigger. The long charging time of the
MP2 are on and quickly charge CPAR such that V D shoots
capacitor due to small IBIAS results in higher switching losses
up instantaneously and speed-up the switching activity even
and the OTA if used, consumes steady dc power. Denier [17]
for very low values of IHYB2 . I3 and I4 buffer the output
presents the use of current comparator instead of OTA. The
of I2 to discharge C S through switch MN4. As VC drops,
oscillator uses equal bias currents for generation of reference
MN3 turns on. MN3 and MN4 along with the regenerative
voltage and for capacitor charging and claims lower power
feedback of MN1 and MN2 discharges CPAR and V D is pulled
consumption due to reduced number of current-conducting
down to zero. This cycle repeats to produce a periodic clock
branches. In this paper, a nanopower relaxation oscillator that
whose output duty cycle error is corrected by using a clock
does not use an OTA or an additional reference generator is
divider FF1 to obtain the output clock. Instead of current
proposed for charge-pump clock generation. Instead it uses
mode, the entire comparator can be analyzed in voltage mode
the available external reference voltage and a fully digital
similar to a Schmitt trigger circuit and can be considered a
current comparator for ultralow-power operation. The response
voltage mode comparator with threshold voltage determined
time of this current comparator is proportional to the input
by the device sizing. The effective clock frequency of the
current [18] which directly benefits the frequency scalability
output clock is given by
of the oscillator with its bias current.
Fig. 7(b) shows the overall schematic of the proposed LPRO IHYB2
circuit. The second output from HBCG circuit (IHYB2 ) acts FCLK ∼
= . (13)
2C S ∗ (VBG − VTHN )
as the charging current. An NMOS switch MN3 is placed in
between current source IHYB2 and the capacitor (C S ) with its Since IHYB2 changes with ILOAD , the clock frequency also
gate controlled by VREF . A T-filter is placed in between the changes proportionally to generate a load current dependent
external reference voltage (VBG ) and VREF to avoid switching frequency as required by the dynamic frequency charge pump.
noise coupling onto VBG . Initially, the capacitor voltage VC Fig. 8 shows a comparison between the simulated transient
and therefore the drain voltage of MN3 (V D ) are at zero after capacitor voltage and supply current profiles for different types
the previous discharge cycle. At this state, output of inverter of oscillator. Even in case of an oscillator with Schmitt trigger,
I 1 in the current comparator is at logic high while the output of the effective area under the supply current curve is reduced
I 2 is at logic low due to which transistor MP1 and MN1 are when a switch is introduced in between the capacitor and
on and MP2 and MN2 are off. As IHYB2 charges C S , VC bias current. This is reduced further by introduction of the
increases linearly. This pushes MN3 into subthreshold region fast switching current comparator as in the case of LPRO.
where its drain–source current is given by The average I Q of the proposed LPRO is only 40 nA for an
    output frequency of 22 kHz which translates to an oscillator
VGS V
− VDS
IDS,MN3 ∝ e ηVt
1−e t (12) figure of merit (FOM) of only 2.7 nW/kHz for a supply voltage
case of 1.5 V. Monte Carlo simulation results with N = 100
where Vt = (kT /q) ≈ 26 mV at T = 27 °C samples for the output frequency and average I Q of the LPRO
and η is a process constant. As VC increases are captured in Fig. 9 at ILOAD = 0. A 3σ variation of ±10 nA
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

MAGOD et al.: 1.24 μA QUIESCENT CURRENT NMOS LDO REGULATOR 7

Fig. 11. LDO pole locations and their movement with increasing load current.

is kept low for the entire 3σ frequency variation range of

around ±8 kHz as shown in Fig. 9, both CCH and CST are
sized slightly higher to be 8 pF each.

V. S TABILITY A NALYSIS AND C OMPENSATION

The stability of this LDO is determined by the location of
three distinctive poles: the LDO output pole POUT , amplifier
output pole PAMP , and the pass device gate pole PGATE . Since
the NMOS pass device acts like a source follower, the output
impedance of the LDO is given by
1
ROUT ∼
= ||RLOAD (14)
gm,MNP
Fig. 9. Histogram of clock frequency and average I Q of the proposed LPRO
for Monte Carlo simulation (N = 100). where RLOAD is the load current equivalent resistance con-
nected at the output of the LDO. Thus, POUT is given by
1
POUT ∼
=   . (15)
2π 1
gm,MNP ||R LOAD C LOAD

PAMP is given in (3) and PGATE is obtained by using (7) and

parasitic pass device gate capacitance CGATE as
1
PGATE ∼
= . (16)
2π(gm MP8 ∗ gm MP9 )(rds,MP7 ||rds,MN9)CGATE
POUT changes with ILOAD and due to adaptive biasing,
PAMP , PGATE , and the loop UGB also change with ILOAD.
Fig. 11 shows the typical movement of these poles with
ILOAD. The proposed buffer design makes sure that PGATE is
always beyond the loop UGB and hence does not influence
the overall loop stability. At zero to light load currents
(ILOAD1 ), POUT is at a very low frequency (∼1 Hz) and is
Fig. 10. Clock frequency modulated charge-pump voltage doubler. very close to PAMP (∼10 Hz). As ILOAD increases to about
1 mA (ILOAD2 ), POUT drastically shifts to higher frequency,
however, due to very minor increment in bias current, PAMP
is a negligible variation when compared to the overall I Q of moves slightly. Hereafter, as the ILOAD increases, POUT shifts
the LDO. to higher frequency eventually moving outside the UGB for
Fig. 10 shows the employed cross-coupled voltage doubler close to maximum ILOAD conditions (ILOAD3 ). PAMP also
charge-pump [19]. It uses non-overlapping clock phases and shifts to higher frequency due to proportional increase in
two inverters (INV1 and INV2 ) to drive two charging capac- bias current thereby increasing the loop UGB. Closely spaced
itors (CCH ). Due to the combined effect of NMOS switches low-frequency poles at light ILOAD and constantly frequency
MN1 and MN2 along with the inverters, the node voltages shifting poles with increase in ILOAD result in challenging
V1 and V2 swing between VIN and 2 × VIN . This charge is considerations for the compensation scheme. Current buffer
then transferred onto storage capacitance CST in every clock compensation as presented in [4] is very effective in pole
phase and maintains the output voltage of the charge-pump splitting but in this case, since the two poles of interest are
close to 2 × VIN . In order to ensure that output voltage ripple at very low frequency, the required Miller capacitance for
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 12. Proposed SCPT compensation scheme. Fig. 13. LDO loop gain and phase response with the pole tracking SCPT
zero highlighted.

pole splitting results in huge area penalty for integration.

Tan et al. [20] present a weighted current feedback technique
along with Miller compensation but is suitable for load capac-
itance up to 10 nF. Pole tracking compensation is presented
in [21] and [22] where the movement of POUT is tracked and
used for compensation. However, the load current of [21] is
limited to 100 μA on the lower side instead of zero and
the zero implemented using MOS resistor in [22] can vary
significantly due to process variations.
In this paper, a POUT tracking zero is introduced to provide
a phase boost and ensure stability. A zero can be introduced
in the loop by using a resistor R Z as shown in Fig. 12.
However, with CAMP = 2.5 pF, in order to introduce a zero
at around UGB for no-load, the required resistance can be as
high as 100 M which results in large area penalty. Moreover,
R Z needs to track POUT and hence needs to be variable
resistor. This is achieved using a novel SCPT compensation
scheme where a switched-capacitor resistor (RSC ) is placed
Fig. 14. Die micrograph.
instead of R Z to introduce a zero (Z SC ). The same oscillator
clock is used to control RSC with its effective value given by
1 ±8 kHz in oscillator frequency might cause a minor change
RSC = (17) in the actual value of the phase margin but does not affect the
FCLK ∗ CSC
stability. This scheme ensures that the LDO is stable even
where CSC is the capacitance used to implement RSC and the for increments in load capacitance up to 47 μF. The zero
SCPT zero Z SC is given by introduced by SCPT compensation also increases the UGB of
FCLK ∗ CSC the loop thereby improving its transient response. It is to be
Z SC = . (18) noted that in this compensation scheme, the clock frequency is
2πCAMP
always at least 50 times the loop UGB (FCLK ≥ 50∗UGB) for
However, from (13), we know that FCLK ∝ IHYB1 and due
all load current conditions. Therefore, any pole (Ppar ) formed
to adaptive biasing we have IHYB1 ∝ ILOAD . Therefore,
due to RSC and net parasitic capacitance (Cpar ) attached to it,
from (18), we have
given by
Z SC ∝ ILOAD. (19) 1 FCLK × CSC
Ppar = = (20)
Thus, Z SC tracks POUT which is proportional to ILOAD and Rz ∗ Cpar Cpar
provides a phase boost for the entire range of load currents.
will always be much beyond the loop UGB and does not affect
A small capacitance CSC = 0.25 pF is used to implement RSC ,
the stability of the LDO.
providing an area-efficient solution. Non-overlapping clocks
control the switches used in this switched-capacitor resistor.
Fig. 13 shows the simulated gain and phase response of the VI. S IMULATION AND M EASUREMENT R ESULTS
LDO loop obtained using periodic steady state (PSS) followed This LDO is fabricated in a 0.25 μm single-poly four-metal
by periodic ac (PAC) simulation for different load current CMOS process. Fig. 14 shows the die micrograph. The core
values for a load capacitance of 1 μF. The impact of hybrid area is 400 μm × 260 μm excluding the test pads and the
biasing can be seen as the UGB shifts with load current. additional circuitry used for programming and testing. This
The phase margin is always above 30° and demonstrates the LDO uses an external voltage reference. Although bandgap
effectiveness of the SCPT compensation. The 3σ variation of reference is not integrated within the LDO, sample-and-hold
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

MAGOD et al.: 1.24 μA QUIESCENT CURRENT NMOS LDO REGULATOR 9

Fig. 16. Quiescent current and current efficiency of the LDO versus load
current.

Fig. 15. Simulated no-load I Q using Monte Carlo 100 samples at 25 °C

and 85 °C.

approaches presented in [23] can be used to reduce its current

consumption to few nano-Amperes and therefore its contribu- Fig. 17. Measured no-load I Q for five different chips along with the
undershoot voltage for a load transient of 0–150 mA.
tion to the overall I Q of the LDO can be made negligible.
The LDO has a digitally programmable output voltage range
of 1–3 V and a maximum output current capability of 150 mA TABLE I
at a dropout voltage of 240 mV. The load capacitance range S IMULATED B LOCK L EVEL N O -L OAD I Q B REAKDOWN
is from 1 to 47 μF. A single bond wire is used to bond
the output of the LDO to the package pin and impacts the
dc load regulation which is 25 mV as ILOAD increases from
0 to 150 mA.
Table I shows the simulated block level no-load I Q
consumption breakdown of the LDO. The major contribution
to the overall I Q is from the error amplifier and associated
charge-pump in order to ensure good transient response.
The programmable resistor divider which is critical for
output voltage programmability consumes 100 nA while
the internal constant-gm current reference branches takes
40 nA. Fig. 15 shows Monte Carlo simulation results for the
overall I Q of the LDO for 25 °C and 85 °C with process
variation and device mismatch. Fig. 16 captures the I Q
of the LDO and its current efficiency versus ILOAD. The
no-load I Q of the proposed LDO is only 1.24 μA. It stays current efficiency is above 95% even for ILOAD as low as
below 2 μA for ILOAD < 200 μA and is only about 5 μA 50 μA and is above 99% for 200 μA and above. The measured
even when ILOAD goes up to 1 mA thereby consuming I Q of 1.24 μA shows that the design is centered across the
very low supply current even at light load conditions. The the mean value as shown in the Monte Carlo simulation
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 18. Measured load transient response of the proposed LDO for different load steps and output capacitor values.

results in Fig. 15 and achieves a high current efficiency.

Fig. 17 shows the measured I Q of five different test chips
along with their output undershoot voltage for a 0 to 150 mA
load current step. The results show consistency in the both
I Q and undershoot voltage with less than 3% variation. The
measured load transient response for different load steps
and output capacitor combinations is shown in Fig. 18. For
CLOAD = 1 μF, the undershoot and overshoot voltage for
load step of 0–50 mA and vice-versa are 76 and 32 mV,
respectively, and are 135 and 65 mV, respectively, for a load
step of 0–150 mA. The output recovers to tolerable error
limit of ±1% within 10 μs. Reduction in both undershoot
and overshoot voltages is observed when CLOAD = 10 μF
and CLOAD = 47 μF which also confirms the stability of
the LDO at these load capacitance levels. Besides using
an NMOS pass device, low overshoot/undershoot, and fast
Fig. 19. Measured line transient response of the LDO at full-load current.
recovery performance of this low I Q LDO is only possible due
to the hybrid biasing working alongside the on-demand PU/PD
buffer and SCPT compensation. Although choice of NMOS the worst case voltage error is less than 3% in such cases and is
pass device results in additional requirement of charge-pump negligible.
and associated oscillator for ensuring LDO voltage, improved Fig. 19 shows the line transient response of the LDO at
transient response, and effective usage of the oscillator for maximum load condition (ILOAD = 150 mA) for output
SCPT compensation scheme overpowers this limitation. The voltage of 1.8 V. The initial step-up and step-down in the
impact of output capacitor PD circuit can be seen in the case supply voltage is 0.75 V and results in an undershoot of 35 mV
of 0–150 mA transition with CLOAD = 1 μF as the high and overshoot of 25 mV. This constitutes less than 2% error
output overshoot of 65 mV is quickly discharged and brought for an output voltage of 1.8 V. The power supply rejection
down to a tolerable error voltage. In all other cases when the (PSR) of the LDO is shown in Fig. 20 at ILOAD = 150 mA.
output voltage overshoot is less than 35 mV, the pull-down The UGB improvement achieved due to hybrid biasing enables
circuit does not kick-in for capacitor discharge. However, higher than 20 dB rejection for frequencies up to 20 kHz.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

MAGOD et al.: 1.24 μA QUIESCENT CURRENT NMOS LDO REGULATOR 11

TABLE II
P ERFORMANCE C OMPARISON OF THE P ROPOSED LDO W ITH P REVIOUSLY P UBLISHED O UTPUT C APACITOR S TABILIZED LDOs

a comparable no-load I Q , its maximum load current is limited

to 50 mA and it has a 2.5 times higher FOM.

VII. C ONCLUSION
This paper presents an NMOS LDO with a very low I Q
of 1.24 μA. Hybrid bias-current scaling scheme is presented
to improve the bandwidth and slew rate of the LDO for fast
response to load current transients. A charge-pump powered,
bias-current scalable two-stage error amplifier is implemented
for LDO regulation. The proposed on-demand PU/PD buffer
ensures high slew rate at the gate of the pass device. An LPRO
with load current controlled clock frequency is proposed to
generate the control clocks for the charge pump. This oscillator
consumes only 40 nA of I Q at light load currents. A novel
SCPT compensation scheme is employed for LDO stabil-
Fig. 20. Measured PSR of the LDO at full-load current. ity. This technique uses the already available variable clock
frequency to achieve stability for a load capacitance range
of 1–47 μF without the requirement of an ESR zero. Measure-
Table II provides a comprehensive comparison of the pro- ment results show that the LDO has a recovery time of less
posed LDO with previously published work highlighting its than 10 μs for zero to full-load current step-up and achieves
major advantages. In comparison, this LDO has the lowest I Q higher than 95% current efficiency even for small load current
which is critical for low power consumption during standby of 50 μA. The competitive transient FOM makes this LDO
and light load conditions. The SCPT compensation not only highly favorable for supply regulation of battery powered, long
ensures stability of the LDO from zero to entire range of standby time, and short wake-up time applications.
load current, but also for a capacitance range of 1–47 μF
without depending on an external ESR zero thereby provid- ACKNOWLEDGMENT
ing the widest output capacitor range. The FOM defined as The authors would like to thank the Linear Power Group,
FOM = TR ∗ (I Q /ILOAD,MAX) is incorporated from [4] for Texas Instruments Inc., Tuscon, AZ, USA, for their support in
a proper baseline comparison where TR is the recovery time chip fabrication.
given by TR = (CLOAD ∗ V /ILOAD,MAX ), where V is the
undershoot voltage. A lower FOM suggests an overall better R EFERENCES
performing LDO. The proposed LDO achieves atleast 66%
[1] K. Yadav, I. Kymissis, and P. R. Kinget, “A 4.4-μW wake-up receiver
reduction in FOM when compared to LDOs with maximum using ultrasound data,” IEEE J. Solid-State Circuits, vol. 48, no. 3,
load current capability of 100 mA or above. Although [16] has pp. 649–660, Mar. 2013.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

12 IEEE JOURNAL OF SOLID-STATE CIRCUITS

[2] J. Choi, J. Shin, D. Kang, and D.-S. Park, “Always-on CMOS image [24] H.-C. Lin, H.-H. Wu, and T.-Y. Chang, “An active-frequency compensa-
sensor for mobile and wearable devices,” IEEE J. Solid-State Circuits, tion scheme for CMOS low-dropout regulators with transient-response
vol. 51, no. 1, pp. 130–140, Jan. 2016. improvement,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 9,
[3] G. A. Rincon-Mora, Analog IC Design with Low-Dropout Regulators, pp. 853–857, Sep. 2008.
2nd ed. New York, NY, USA: McGraw-Hill, 2014. [25] C.-H. Lin, K.-H. Chen, and H.-W. Huang, “Low-dropout regulators
[4] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced low- with adaptive reference control and dynamic push–pull techniques for
quiescent current low-dropout regulator with buffer impedance atten- enhancing transient performance,” IEEE Trans. Power Electron., vol. 24,
uation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732–1742, no. 4, pp. 1016–1022, Apr. 2009.
Aug. 2007. [26] M. Ho, K. N. Leung, and K.-L. Mak, “A low-power fast-transient
[5] Y.-H. Lam and W.-H. Ki, “A 0.9 V 0.35 μm adaptively biased CMOS 90-nm low-dropout regulator with multiple small-gain stages,” IEEE
LDO regulator with fast transient response,” in ISSCC Dig. Tech. Papers, J. Solid-State Circuits, vol. 45, no. 11, pp. 2466–2475, Nov. 2010.
Feb. 2008, pp. 442–626. [27] M. Ho et al., “A CMOS low-dropout regulator with dominant-
[6] T. Y. Man, P. K. T. Mok, and M. Chan, “A high slew-rate push–pull pole substitution,” IEEE Trans. Power Electron., vol. 31, no. 9,
output amplifier for low-quiescent current low-dropout regulators with pp. 6362–6371, Sep. 2016.
transient-response improvement,” IEEE Trans. Circuits Syst. II, Exp.
Briefs, vol. 54, no. 9, pp. 755–759, Sep. 2007.
[7] P. Y. Or and K. N. Leung, “An output-capacitorless low-dropout regu-
lator with direct voltage-spike detection,” IEEE J. Solid-State Circuits,
vol. 45, no. 2, pp. 458–466, Feb. 2010. Raveesh Magod (S’14) received the M.S. degree in
[8] J. Guo and K. N. Leung, “A 6-μW chip-area-efficient output- electrical engineering from Arizona State University,
capacitorless LDO in 90-nm CMOS technology,” IEEE J. Solid-State Tempe, AZ, USA, in 2014, where he is currently
Circuits, vol. 45, no. 9, pp. 1896–1905, Sep. 2010. pursuing the Ph.D. degree.
[9] K. N. Leung and Y. S. Ng, “A CMOS low-dropout regulator with In 2017, he joined Kilby Labs, Texas Instruments,
a momentarily current-boosting voltage buffer,” IEEE Trans. Circuits Dallas, TX, USA, where he is involved in design
Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2312–2319, Sep. 2010. of nanopower power management circuits. From
[10] H. Marco and K. N. Leung, “Dynamic bias-current boosting technique 2015 to 2016, he was an analog design intern at
for ultralow-power low-dropout regulator in biomedical applications,” Texas Instruments, Tucson, AZ, USA, where he was
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 3, pp. 174–178, involved in design of low-power voltage supervisors
Mar. 2011. and low quiescent current LDOs. From 2010 to
[11] C.-J. Park, M. Onabajo, and J. Silva-Martinez, “External capacitor-less 2012, he was a Design Engineer at Sankalp Semiconductor Pvt. Ltd., Hubli,
low drop-out regulator with 25 dB superior power supply rejection in India, where he focused on low-power CMOS interface solutions. His current
the 0.4–4 MHz range,” IEEE J. Solid-State Circuits, vol. 49, no. 2, research interests include ultralow-power analog and mixed-signal design
pp. 486–501, Feb. 2014. techniques for power management ICs.
[12] Y. Lu, W.-H. Ki, and C. P. Yue, “An NMOS-LDO regulated switched-
capacitor DC-DC converter with fast-response adaptive-phase digital
control,” IEEE Trans. Power Electron., vol. 31, no. 2, pp. 1294–1303,
Feb. 2016.
[13] C. Zhan and W.-H. Ki, “An output-capacitor-free adaptively biased Bertan Bakkaloglu (M’94–SM’08–F’17) received
low-dropout regulator with subthreshold undershoot-reduction for SoC,” the Ph.D. degree from Oregon State University,
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 5, pp. 1119–1131, Corvallis, OR, USA, in 1995.
May 2012. He was with the Mixed Signal Wireless Design
[14] A. Maity and A. Patra, “Dynamic slew enhancement technique for Group, Texas Instruments Inc., Dallas, TX, USA,
improving transient response in an adaptively biased low-dropout reg- where he was involved in analog, RF, and mixed-
ulator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 62, no. 7, signal front ends for wireless and wireline commu-
pp. 626–630, Jul. 2015. nication ICs. As a Design Leader, he was involved in
[15] A. Maity and A. Patra, “Analysis, design, and performance evalua- system-on-chip designs with integrated battery man-
tion of a dynamically slew enhanced adaptively biased capacitor-less agement and analog baseband functionality. In 2004,
low dropout regulator,” IEEE Trans. Power Electron., vol. 31, no. 3, he joined the Electrical Engineering Department,
pp. 7016–7028, Oct. 2016. Arizona State University, Tempe, AZ, USA, as an Associate Professor, where
[16] A. Maity and A. Patra, “A hybrid-mode operational transconductance he is currently a Professor. His current research interests include RF and PA
amplifier for an adaptively biased low dropout regulator,” IEEE Trans. supply regulators, RF synthesizers, biomedical and instrumentation circuits
Power Electron., vol. 32, no. 2, pp. 1245–1254, Feb. 2017. and systems, high-speed RF data converters and RF built-in-self-test circuits
[17] U. Denier, “Analysis and design of an ultralow-power CMOS relaxation for communication ICs.
oscillator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, Dr. Bakkaloglu has been a Technical Program Chair and a General Chair
pp. 1973–1982, Aug. 2010. of the IEEE RFIC conference and an Associate Editor of the IEEE T RANS -
[18] D. Banks and C. Toumazou, “Low-power high-speed current comparator ACTIONS ON C IRCUITS AND S YSTEMS and the IEEE T RANSACTIONS ON
design,” Electron. Lett., vol. 44, no. 3, pp. 171–172, Jan. 2008. M ICROWAVE T HEORY AND T ECHNIQUES . He is the Founding Member of the
[19] T. Ying, W.-H. Ki, and M. Chan, “Area-efficient CMOS charge pumps IEEE Solid State Circuits Society Phoenix Chapter and a Microwave Theory
for LCD drivers,” IEEE J. Solid-State Circuits, vol. 38, no. 10, and Techniques Society RFIC (TC-23) Subcommittee Chair.
pp. 1721–1725, Oct. 2003.
[20] X. L. Tan, S. S. Chong, P. K. Chan, and U. Dasgupta, “A LDO regulator
with weighted current feedback technique for 0.47 nF–10 nF capacitive
load,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2658–2672,
Nov. 2014. Sanjeev Manandhar received the B.S. degree in
[21] Y. H. Lin, K. L. Zheng, and K. H. Chen, “Smooth pole tracking computer engineering and the M.S. degree in elec-
technique by power MOSFET array in low-dropout regulators,” IEEE trical engineering from the University of Maine,
Trans. Power Electron., vol. 23, no. 5, pp. 2421–2427, Sep. 2008. Orono, ME, USA, in 2004 and 2006, respectively.
[22] K. C. Kwok and P. K. T. Mok, “Pole-zero tracking frequency com- Since 2006, he has been with Texas Instruments
pensation for low dropout regulator,” in Proc. IEEE Int. Symp. Circuits Inc., Tucson, AZ, USA, where he has focused on
Syst. (ISCAS), May 2002, pp. IV-735–IV-738. high-performance low dropout voltage regulators,
[23] R. Magod, N. Suda, V. Ivanov, R. Balasingam, and B. Bakkaloglu, supply voltage supervisors, and low-power designs.
“A low-noise output capacitorless low-dropout regulator with a switched- He currently manages the LDO Design Team, focus-
RC bandgap reference,” IEEE Trans. Power Electron., vol. 32, no. 4, ing on families of high-performance and low-power
pp. 2856–2864, Apr. 2017. LDOs.