CD54HC273, CD74HC273

CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022

CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

1 Features 2 Description
• Common clock and asynchronous controller reset The ’HC273 and ’HCT273 high speed octal D-Type
• Positive edge triggering flip-flops with a direct clear input are manufactured
• Buffered inputs with silicon-gate CMOS technology. They possess the
• Fanout (over temperature range) low power consumption of standard CMOS integrated
– Standard outputs: 10 LSTTL loads circuits.
– Bus driver outputs: 15 LSTTL loads Information at the D input is transferred to the Q
• Wide operating temperature range: –55℃ to 125℃ outputs on the positive-going edge of the clock pulse.
• Balanced propagation delay and transition times All eight flip-flops are controlled by a common clock
• Significant power reduction compared to LSTTL (CLK) and a common reset (CLR). Resetting is
Logic ICs accomplished by a low voltage level independent of
• HC types: the clock. All eight Q outputs are reset to a logic 0.
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of Device Information
(1)
VCC at VCC = 5V PART NUMBER PACKAGE BODY SIZE (NOM)
• HCT types: CD54HC273F CDIP (20) 26.92 mm × 6.92 mm
– 4.5 V to 5.5 V operation CD74HC273M SOIC (20) 12.80 mm × 7.50 mm
– Direct LSTTL input logic compatibility, VIL = 0.8 CD74HC273E PDIP (20) 25.40 mm × 6.35 mm
V (max), VIH = 2 V (min) CD74HCT273M SOIC (20) 12.80 mm × 7.50 mm
– CMOS input compatibility, II ≤ 1 μA at VOL,VOH
CD74HCT273 PDIP (20) 25.40 mm × 6.35 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Shared Control Logic

CLR

CLK

R
xD D Q xQ

One of Eight D-Type Flip-Flops

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com

Table of Contents
1 Features............................................................................1 6.3 Device Functional Modes............................................8
2 Description.......................................................................1 7 Parameter Measurement Information............................ 9
3 Revision History.............................................................. 2 8 Power Supply Recommendations................................11
4 Pin Configuration and Functions...................................3 9 Layout............................................................................. 11
5 Specifications.................................................................. 4 9.1 Layout Guidelines..................................................... 11
5.1 Absolute Maximum Ratings........................................ 4 10 Device and Documentation Support..........................12
5.2 Recommended Operating Conditions.........................4 10.1 Receiving Notification of Documentation Updates..12
5.3 Thermal Information....................................................4 10.2 Support Resources................................................. 12
5.4 Electrical Characteristics.............................................5 10.3 Trademarks............................................................. 12
5.5 Prerequisite for Switching Characteristics.................. 6 10.4 Electrostatic Discharge Caution..............................12
5.6 Switching Characteristics............................................7 10.5 Glossary..................................................................12
6 Detailed Description........................................................8 11 Mechanical, Packaging, and Orderable
6.1 Overview..................................................................... 8 Information.................................................................... 12
6.2 Functional Block Diagram........................................... 8

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2003) to Revision C (January 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-refrences throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
• Updated pin names to match current TI naming conventions. MR is now CLR, Q0 is now 1Q, D0 is now 1D,
D1 is now 2D, Q1 is now 2Q, Q2 is now 3Q, D2 is now 3Q, D3 is now 4D, Q3 is now 4Q, CP is now CLK, Q4
is now 5Q, D4 is now 5D, D5 is now D6, Q5 is now 6Q, Q6 is now 7Q, D6 is now 7D, D7 is now 8D, Q7 is
now 8Q............................................................................................................................................................... 1

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273

 CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
www.ti.com SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022

4 Pin Configuration and Functions

CLR 1 20 VCC
1Q 2 19 8Q
1D 3 18 8D
2D 4 17 7D
2Q 5 16 7Q
3Q 6 15 6Q
3D 7 14 6D
4Q 8 13 5D
4D 9 12 5Q
GND 10 11 CLK

J, DW or N package
20-Pin CDIP, PDIP or SOIC
Top View

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273
CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com

5 Specifications
5.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage – 0.5 7 V
IIK Input clamp diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA
IOK Output clamp diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA
IO Drain current, per output For –0.5 V < VO < VCC + 0.5 V ±25 mA
IO Output source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA
Continuous current through VCC or ground current ±50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature range – 65 150 °C
Lead temperature (Soldering 10s) (SOIC - Lead Tips Only) 300 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 Recommended Operating Conditions

MIN MAX UNIT
TA Temperature range –55 125 ℃
HC types 2 6
VCC Supply voltage range V
HCT types 4.5 5.5
VI, VO DC input or output voltage 0 VCC V
2V 1000
tt Input rise and fall time 4.5 V 500 ns
6V 400

5.3 Thermal Information

DW (SOIC) N (PDIP)
THERMAL METRIC 20 PINS 20 PINS UNIT
(1)
RθJA Junction-to-ambient thermal resistance 58 69 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273

 CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
www.ti.com SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022

5.4 Electrical Characteristics

TEST 25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER (2) VCC (V) UNIT
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 1.5 1.5 1.5
High level input
VIH 4.5 3.15 3.15 3.15 V
voltage
6 4.2 4.2 4.2
2 0.5 0.5 0.5
Low level input
VIL 4.5 1.35 1.35 1.35 V
voltage
6 1.8 1.8 1.8
High level output IOH = – 20 μA 2 1.9 1.9 1.9
voltage IOH = – 20 μA 4.5 4.4 4.4 4.4 V
CMOS loads IOH = – 20 μA 6 5.9 5.9 5.9
VOH
High level output IOH = – 4 mA 4.5 3.98 3.84 3.7
voltage V
IOH = – 5.2 mA 6 5.48 5.34 5.2
TTL loads

Low level output IOL = 20 μA 2 0.1 0.1 0.1

voltage IOL = 20 μA 4.5 0.1 - 0.1 - 0.1 V
CMOS loads IOL = 20 μA 6 0.1 0.1 0.1
VOL
Low level output IOL = 4 mA 4.5 0.26 0.33 0.4
voltage V
IOL = 5.2 mA 6 0.26 0.33 0.4
TTL loads
Input leakage
II VI = VCC or GND 6 ±0.1 ±1 ±1 mA
current
Quiescent device
ICC VI = VCC or GND 6 8 80 160 mA
current
HCT TYPES
High level input 4.5 to
VIH 2 2 2 V
voltage 5.5
Low level input 4.5 to
VIL 0.8 0.8 0.8 V
voltage 5.5
High level output
voltage IOH = – 20 μA 4.5 4.4 4.4 4.4
CMOS loads
VOH V
High level output
voltage IOH = – 4 mA 4.5 3.98 3.84 3.7
TTL loads

Low level output

voltage IOL = 20 μA 4.5 0.1 0.1 0.1
CMOS loads
VOL V
Low level output
voltage IOL = 4 mA 4.5 0.26 0.33 0.4
TTL loads
Input leakage
II VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA
current
Quiescent device
ICC VI = VCC or GND 5.5 8 80 160 μA
current

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273
CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com

5.4 Electrical Characteristics (continued)

TEST 25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER (2) VCC (V) UNIT
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
CLR input held at 4.5 to
100 540 675 735 μA
VCC –2.1 5.5
Additional quiescent
Data inputs held at 4.5 to
ΔICC (1) device current per 100 144 180 196 μA
VCC –2.1 5.5
input pin
CLK inputs held at 4.5 to
100 540 675 735 μA
VCC –2.1 5.5

(1) For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8mA.
(2) VI = VIH or VIL, unless otherwise noted.

5.5 Prerequisite for Switching Characteristics

See Parameter Measurement Information
25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER VCC (V) UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 6 5 4
fMAX Maximum clock frequency 4.5 30 25 20 MHz
6 35 29 23
2 60 75 90
tW CLR pulse width 4.5 12 15 18 ns
6 10 13 15
2 80 100 120
tW Clock pulse width 4.5 16 20 24 ns
6 14 17 20
2 60 75 70
tSU Set-up time data to clock 4.5 12 15 18 ns
6 10 13 15
2 3 3 3
tH Hold time, data to clock 4.5 3 3 3 ns
6 3 3 3
2 50 65 75
tREM Removal time, CLR to clock 4.5 10 13 15 ns
6 9 11 13
HCT TYPES
fMAX Maximum clock frequency 4.5 25 20 16 MHz

tw CLR pulse width 4.5 12 15 18 ns

tw Clock pulse width 4.5 20 25 30 ns

tSU Set-up time data to clock 4.5 12 15 18 ns

tH Hold time, data to clock 4.5 3 3 3 ns

tREM Removal time, CLR to clock 4.5 10 13 15 ns

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273

 CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
www.ti.com SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022

5.6 Switching Characteristics

Input tr, tf = 6 ns (See Parameter Measurement Information)
TEST 25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER VCC(V) UNIT
CONDITIONS TYP MAX MAX MAX
HC TYPES
2 150 190 225
Propagation delay CL = 50 pF 4.5 30 38 45
tPLH, tPHL ns
Clock to output 6 26 30 38
CL = 15 pF 5 12
2 150 190 225
Propagation delay
tPHL CL = 50 pF 4.5 30 38 45 ns
CLR to output
6 26 30 38
2 75 95 110
tTLH, tTHL Output transition time CL = 50 pF 4.5 15 19 22 ns
6 13 16 19
CIN Input capacitance 10 10 10 pF
fMAX Maximum clock frequency CL = 15 pF 5 60 MHz
CPD Power dissipation capacitance(1) (2) 5 25 pF
HCT TYPES
Propagation delay, CL = 50 pF 4.5 30 38 45
tPLH, tPHL ns
Clock to output CL = 15 pF 5 12
Propagation delay,
tPHL CL = 50 pF 4.5 32 40 48 ns
CLR to output
tTLH, tTHL Output transition time CL = 50 pF 4.5 15 19 22 ns
CIN Input capacitance 10 10 10 pF
fMAX Maximum clock frequency CL = 15 pF 5 50 MHz
CPD Power dissipation capacitance(1) (2) 5 25 pF

(1) CPD is used to determine the dynamic power consumption, per flip-flop.
(2) PD = CPD VCC 2 fi + Σ (CL VCC 2 + fO) where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply
voltage.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273
CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com

6 Detailed Description
6.1 Overview
The ’HC273 and ’HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with
silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits.
Information at the D input is transferred to the Q outputs on the positive-going edge of the clock pulse. All eight
flip-flops are controlled by a common clock (CLK) and a common reset (CLR). Resetting is accomplished by a
low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.
6.2 Functional Block Diagram

Shared Control Logic

CLR

CLK

R
xD D Q xQ

One of Eight D-Type Flip-Flops

6.3 Device Functional Modes

Table 6-1. Truth Table(1)
INPUTS OUTPUT
RESET (CLR) CLOCK CLK DATA Dn Q
L X X L
H ↑ H H
H ↑ L L
H L X Q0

(1) H = high voltage level, L = low voltage level, X = don’t care, ↑ =

transition from low to high level, Q0 = level before the indicated
steady-state input conditions were established

8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273

 CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
www.ti.com SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022

7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

Test
Point

From Output
Under Test
CL(1)

(1) CL includes probe and test-fixture capacitance.

Figure 7-1. Load Circuit for Push-Pull Outputs

tw VCC
VCC Clock
50%
Input
Input 50% 50% 0V
0V
tsu th
Figure 7-2. Voltage Waveforms, Standard CMOS VCC
Inputs Pulse Duration Data
50% 50%
Input
0V
Figure 7-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
VCC VCC
90% 90%
Input 50% 50% Input
10% 10%
0V 0V
(1) (1)
tr(1) tf(1)
tPLH tPHL
VOH VOH
90% 90%
Output 50% 50% Output
10% 10%
VOL VOL
(1) (1)
tr(1) tf(1)
tPHL tPLH
(1) The greater between tr and tf is the same as tt.
VOH
Figure 7-5. Voltage Waveforms, Input and Output
Output 50% 50% Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273
CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com

tw 3V
3V Clock
1.3V
Input
Input 1.3V 1.3V 0V
0V
tsu th
Figure 7-6. Voltage Waveforms, TTL-Compatible 3V
CMOS Inputs Pulse Duration Data
1.3V 1.3V
Input
0V
Figure 7-7. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
3V
Input 1.3V 1.3V
0V
tPLH(1) tPHL(1)
VOH
Output
50% 50%
Waveform 1
VOL
tPHL(1) tPLH(1)
VOH
Output
50% 50%
Waveform 2
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-8. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs

10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273

 CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
www.ti.com SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022

8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273
CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273

 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8772501RA ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8772501RA Samples
& Green CD54HCT273F3A
CD54HC273F ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC273F Samples
& Green
CD54HC273F3A ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409901RA Samples
& Green CD54HC273F3A
CD54HCT273F ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HCT273F Samples
& Green
CD54HCT273F3A ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8772501RA Samples
& Green CD54HCT273F3A
CD74HC273E ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC273E Samples

CD74HC273M OBSOLETE SOIC DW 20 TBD Call TI Call TI -55 to 125 HC273M

CD74HC273M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC273M Samples

CD74HC273M96E4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC273M Samples

CD74HCT273E ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT273E Samples

CD74HCT273EE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT273E Samples

CD74HCT273M OBSOLETE SOIC DW 20 TBD Call TI Call TI -55 to 125 HCT273M

CD74HCT273M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT273M Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC273, CD54HCT273, CD74HC273, CD74HCT273 :

• Catalog : CD74HC273, CD74HCT273

• Military : CD54HC273, CD54HCT273

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC273M96 SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
CD74HC273M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
CD74HCT273M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
CD74HCT273M96 SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC273M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HC273M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HCT273M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HCT273M96 SOIC DW 20 2000 356.0 356.0 41.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Jun-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC273E N PDIP 20 20 506 13.97 11230 4.32
CD74HCT273E N PDIP 20 20 506 13.97 11230 4.32
CD74HCT273EE4 N PDIP 20 20 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated