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Amba Apb Protocol

The document provides an overview of the AMBA APB (Advanced Peripheral Bus) protocol, which is designed for low-power, low-latency communication between low-speed peripherals and high-performance system components. It explains the architecture of the AMBA bus, detailing the read and write transactions with timing diagrams, and outlines the various modules involved in a project implementation using UVM verification. The document serves as a practical guide for understanding and implementing AMBA APB verification in a simplified manner.

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14 views16 pages

Amba Apb Protocol

The document provides an overview of the AMBA APB (Advanced Peripheral Bus) protocol, which is designed for low-power, low-latency communication between low-speed peripherals and high-performance system components. It explains the architecture of the AMBA bus, detailing the read and write transactions with timing diagrams, and outlines the various modules involved in a project implementation using UVM verification. The document serves as a practical guide for understanding and implementing AMBA APB verification in a simplified manner.

Uploaded by

mumrbs2010
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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AMBA APB

VERIFICATION IN UVM
SIMPLIFIED AND PRACTICAL

AMBA APB CONCEPTS


PROJECT IMPLEMENTATION
UVM VERIFICATION

Prasanthi Chanda
1. What is AMBA Protocol ?
AMBA APB (Advanced Peripheral Bus) is a low-power, low-
latency bus protocol used in the AMBA (Advanced
Microcontroller Bus Architecture) system.
It is primarily designed for connecting low-speed peripherals
such as timers, UARTs, and GPIOs to the high-performance
system bus.
APB is simpler compared to AXI and AHB, supporting single-
cycle transfers with minimal power consumption.

2. AMBA BUS ARCHITECTURE

Fig.1 AMBA Bus Architecture

AMBA (Advanced Microcontroller Bus Architecture) is a bus


protocol developed by ARM for communication between
various components in a system-on-chip (SoC).
The architecture consists of high-speed and low-speed buses
to connect different system components efficiently.
The high-speed AHB or ASB bus connects high-performance
components such as the ARM processor, on-chip RAM, and
memory interfaces.
A high-bandwidth memory interface is connected to the AHB
or ASB bus for efficient data transfer.
A high-performance ARM processor acts as the main
processing unit, handling complex computations and system
control.
On-chip RAM provides fast storage and retrieval of data
required by the processor.
A DMA (Direct Memory Access) bus master enables data
transfer between memory and peripherals without CPU
intervention.
The AHB or ASB bus connects to an APB bridge, which
converts high-speed transactions to low-speed peripheral bus
(APB) transactions.
The APB (Advanced Peripheral Bus) connects low-bandwidth
peripherals such as UART, timer, keypad, and PIO (Parallel
Input/Output).
UART provides serial communication capabilities for the
system.
A timer peripheral manages timing functions such as delays
and scheduling.
The keypad interface allows user input interaction with the
system.
PIO (Parallel Input/Output) handles general-purpose digital I/O
operations.
The APB bridge ensures seamless communication between
high-speed and low-speed components by protocol conversion.
3. Explain the read and write transaction in AMBA APB using
the waveforms.
READ TRANSACTION

Fig.2 Timing Diagram for READ Transaction

1. T0-T1 (SETUP PHASE):


The address Addr 1 is placed on PADDR.
PWRITE is low, indicating a read operation.
PSEL is asserted to select the peripheral.
PENABLE is low, indicating setup phase.
2. T1-T2 (ACCESS PHASE BEGINS):
PENABLE is asserted, indicating the transition to the access
phase.
PREADY is low, meaning the peripheral is not yet ready.
3. T2-T3 (DATA TRANSFER):
PREADY goes high, indicating the peripheral is ready.
The read data Data 1 is placed on PRDATA.
At the rising edge of PCLK, the master reads the data.
4. T3-T4 (TRANSACTION COMPLETION):
PSEL and PENABLE are deasserted, completing the read
transaction.
WRITE TRANSACTION

Fig.3 Timing Diagram for WRITE Transaction

1. T0-T1 (SETUP PHASE):


The address Addr 1 is placed on PADDR.
PWRITE is high, indicating a write operation.
PSEL is asserted to select the peripheral.
PENABLE is low, indicating the setup phase.
2. T1-T2 (ACCESS PHASE BEGINS):
PENABLE is asserted, indicating the transition to the access
phase.
The write data Data 1 is placed on PWDATA.
PREADY is low, meaning the peripheral is not yet ready.
3. T2-T3 (DATA TRANSFER):
PREADY goes high, indicating the peripheral is ready to accept
the data.
The data Data 1 is written into the peripheral.
4. T3-T4 (TRANSACTION COMPLETION):
PSEL and PENABLE are deasserted, completing the write
transaction.
4. Give the operating states of the APB interface.

Fig.4 State diagram for APB Interface


PROJECT IMPLEMENTATION

DESIGN MODULE

APB_IF MODULE
APB_SLAVE MODULE
MODULE FOR APB_MANAGER

MODULE FOR APB_SEQUENCER


MODULE FOR APB_DRIVER
MODULE FOR APB_MONITOR
APB_SEQUENCE MODULE
APB_TEST MODULE

APB_TRANSACTION MODULE
APB_ENV MODULE

APB_SCOREBOARD
TESTBENCH MODULE

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