SHRI RAM GROUP OF COLLEGES

DEPARTMENT OF CSE
B.TECH-3rdSEM.
SUBJECT: DIGITAL ELECTRONICS
IMPORTANT QUESTIONS UNIT-1

1. State De-Morgan’s theorem and mention its use.

2. Express the function BC AY in canonical POS.

3. Convert the given decimal numbers to their binary equivalent 108.364, 268.025.

4. Why totem pole outputs cannot be connected together?

5. Simplify the following Boolean expression into one literal. W’X(Z’+YZ) + X(W+Y’Z).

6. Convert (115)10 and (235)10 into hexadecimal numbers.

7. Define ‘Minterm’ and ‘ Maxterm’.

8. Draw an active high tri-state Gate & write its truth table.

9. Show how to connect NAND gates to get an AND gate and OR gate?

10. State Distributive law and Duality principle.

11. What is meant by Prime Implicant and Essential prime implicants?

12. Find the minimized Boolean expression of this function F=XY+X(Y+Z) +Y(Y+Z).

13. Implement the given function using NAND gates only. F(X, Y, Z) = m(0,6).

14. Find the canonical POS form of Y= A+B’C

15. If A & B are Boolean variables and if A=1 & BA =0, determine B?

16. Apply De-Morgan’s theorem to simplify BC .

17. Implement Y= (1,4,5,6,7) in SOP form using AOI logic.

18. Determine the Boolean expression for the output of the system shown in figure.
19. Interpret the truth table of EX- OR gate.

20. Simplify: ABCABC using Boolean theorems.

21.(i)Find the Minimized logic function using K-Maps and Realize using NAND and NOR gate. F (A, B,
C, D) = d(2,13) m(1,3,5,8,9,11,15)

(ii)Show that if all the gate in a two-level OR-AND gate network are replaced by NOR gate, the
output function does not change.

22. (i) Illustrate the MSOP representation for F(A,B,C,D,E) = m(1,4,6,10,20,22,24,26)+d(0,11,16,27)

using K-map method. Draw the circuit of the minimal expression using only NAND gates.

(ii) Write about Excess 3 and Gray Code with an example.

23. (i) Develop the given function Y (M, N, O, P, Q)= m(0,2,4,6,9,13,21,23,25,29,31) . Draw the K-
map and Implement the simplified expression using basic gates.

(ii) Implement F= A’B’D’+ B’C’+E’ using NAND gates.

24. Evaluate the following Boolean expression using Boolean Algebra and draw the logic diagram.
(i)T(X, Y, Z) = X Z . (5) XY  ZY XY)(X (ii) XY (4) XYZ XYZ (iii) YZ (4) XZ XYZ .

25. (i) Using K-map method, Simplify the following Boolean function =∑m(0,2,3,6,7) + d(8,10,11,15)
and obtain (a) minimal SOP (6) (b) minimal POS expression & realize using only NAND and NOR
gates.

26. (i) Explain the implement of the following function using NAND and inverter gates
F=AB+A’B’+B’C.

(ii) Construct the expression Y (A, B, C) = M(0,2,4,5,6) using Only NOR-NOR logic

27. Design the given function using Prime implicant method and Verify your result using K map F=
m(0,1,2,4,5,6,8,9,12,13,14)

28. Implement the following function using Quine McCluskey method F=

m(0,1,2,8,9,15,17,21,24,25,27,31) +d(3,4,11)

29. Develop the simplified Boolean expression for

f(A,B,C,D,E)=  m(0,5,6,8,9,10,11,16,20,24,25,26,27,29,31)

30. i. Convert (725.25)8 to its decimal, binary and Hexadecimal equivalent.

ii.Find 1’s and 2’s Complement of 8 digit binary numbers 10101101

 SHRI RAM GROUP OF COLLEGES
DEPARTMENT OF CSE
B.TECH-3rdSEM.
SUBJECT: DIGITAL ELECTRONICS
IMPORTANT QUESTIONS UNIT-2

1. Define Half adder and Full adder circuit.

2. Construct 4-bit parallel adder/subtractor using Full adders and EXOR gates.

3. Relate carry generate, carry propagate, sum and carry-out of a carry look ahead adder.

4. Write about the design procedure for combinational circuits.

5. Identify the basic principle used in order to check or generate the proper parity bit in a given code
word.

6. Distinguish between demultiplexer and decoder .

7. Convert a two-to-four line decoder with enable input to 1:4 demultiplexer.

8. Write about the design procedure for combinational circuits.

9. Sketch the logic diagram and truth table for Full adder circuit.

10. Compare the function of decoder and encoder.

11. Evaluate the logic circuit of a 2 bit comparator.

12. Design the logic circuit of Half subtractor using truth table.

13. State the function of select inputs of a MUX.

14. Develop the following function using suitable multiplexer F= Σm(0,2,5,7).

15. How would you design the logic diagram of a 2 bit multiplier?

16. Draw the logic diagram of a serial adder.

17. Explain a 3 bit even parity generator.

18. Describe code converter? List their types.

19. Examine a single bit magnitude comparator to compare two words A and B.

20. Convert gray code 101011 into its binary equivalent.

21. (i) How will you design a full adder using two half adders and an OR gate.

(ii) Analyze the principle and design of Parallel multiplier with diagrams.

22. (i) Design a 4-bit decimal adder using 4-bit binary adders.

(ii) Simplify the function using multiplexer F= (0,1,3,4,8,9,15) .

23. (i) Construct full subtractor using Demultiplexer.

(ii) Write short note on BCD adder.

24. (i) Analyze the design of 8 x 1 multiplexer using only 2 x 1 multiplexer.

(ii) Formulate the following Boolean function using 4 x 1 multiplexers. F(A,B,C,D) =

m(1,2,3,6,7,8,11,12,14)

25. (i) Draw the logic diagram of a 2-bit by 2-bit binary multiplier and explain its operation.

(ii) Realize F(w, x, y, z)= Σ (1,4,6,7,8,9,10,11,15) using 8 to 1 Multiplexer.

26. (i) Realize a circuit to carryout both addition and subtraction.

(ii) Deduce the design of a 1:8 demultiplexer circuit.

27. How would you design (i) Full adder using demultiplexer.

(ii) Serial binary adder.

28. Illustrate BCD to excess 3 code converter using minimum number of NAND gates.

29. (i)Explain the working and draw the logic diagram of Binary to Octal decoder.

(ii)How would you design BCD to Gray code converter. Use don’t care.

30. (i) Demonstrate 4-bit magnitude comparator with three outputs: A>B, A=B and A<B.

31.With necessary diagrams, explain in detail about the working of a 4-bit look ahead carry adder.
Also mention its advantages over conventional adder.

32. Implement the following Boolean function using an 8:1 multiplexer considering D as the input
and A,B,C as selection lines : F( A, B, C, D) = AB’+BD+B’CD’

33. Construct 4-bit binary multiplier and divider and explain its operation with suitable example.

34. (i). Design an even parity generator that generates an even parity bit for every input string of 3
bits.

(ii). Explain the need of Parity Checker circuit with necessary diagrams.