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MindShare Fundamentals DRAM DDRX LPDDRX Outline

The document provides information about the 'Fundamentals of DRAM (DDRx/LPDDRx) Architecture' course offered by MindShare, designed for both newcomers and experienced professionals in the DRAM field. The one-day course covers essential topics such as DRAM cell addressing, device architecture, and controller basics, making it suitable for hardware and software engineers involved in DRAM design and validation. Participants will receive presentation materials and are recommended to have a basic understanding of digital logic.

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673 views2 pages

MindShare Fundamentals DRAM DDRX LPDDRX Outline

The document provides information about the 'Fundamentals of DRAM (DDRx/LPDDRx) Architecture' course offered by MindShare, designed for both newcomers and experienced professionals in the DRAM field. The one-day course covers essential topics such as DRAM cell addressing, device architecture, and controller basics, making it suitable for hardware and software engineers involved in DRAM design and validation. Participants will receive presentation materials and are recommended to have a basic understanding of digital logic.

Uploaded by

anidggbdnb
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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800-633-1440 1-800-633-1440

[email protected]
www.mindshare.com

Fundamentals of DRAM (DDRx/LPDDRx) Architecture Course Info


Let MindShare Bring “DRAM (DDRx/LPDDRx) Architecture” to Life for You

Whether you are new to DRAM or an industry veteran seeking the latest and greatest standards, you will
learn more than you expect from MindShare's DRAM courses. You may be well-versed on modern serial
protocols but learning parallel-bus protocols of DDR DRAM will be valuable. You might have worked
extensively with mainstream PC DRAMs and now you need to learn low-power LP DRAM designs. Any time
your work requires you to design, develop, validate, verify, test, debug or support DRAM interfaces, you
should seriously consider taking MindShare's classes.

You Will Learn:


• Where JEDEC expects DRAM to appear in a system
• How a DRAM cell is addressed by the controller
• Difference between Banks, Bank Groups and Ranks
• Why the DRAM controller is so complicated
• Activation, Precharge and Refresh
• DDR4/DDR5/LPDDR4/LPDDR5 device architecture overview
• Prefetch Width
• Types of DIMMs
• Fly-By Routing

Course Length: 1 Day

Who Should Attend?


This course is hardware-centric and also describes initialization and training of DRAM devices and
controllers. It is suitable for hardware engineers and software/firmware engineers will also benefit. The
course is ideal for DRAM controller designers, chipset designers, system board-level design and validation
engineers.

Fundamentals of DRAM introduces current DRAM technologies, concentrating on DDR4 to teach concepts
that are common to all DRAMs.

Course Contents:

• System Architecture
o PC Platform Architecture
o NUMA Architecture
o SoC Architecture
• Back to the Future DRAM Intro
o It's more similar than it is different
• DRAM Cell Architecture
o Problems of Activation, Precharge and Refresh
• DRAM Device Architecture
o SDRAM through DDR5
o DDR4/DDR5 Bank Groups
o LPDDR4, LPDDR5
o LPDDR5 Bank Groups
• Packaging
o Monolithic
800-633-1440 1-800-633-1440
[email protected]
www.mindshare.com

o Stacked Die
o 3DS, Hybrid Memory Cube, High Bandwidth Memory (HBM)
o Package-on-Package
o Dual LPDDR4 Channels
• DRAM Controller Basics
o Functional Blocks
o Address Translation/Address Mapping Examples
• Device and Dual In-line Memory Module (DIMM) Pin Descriptions
o DDR4
o DIMM
• Introduction to DIMM Architecture
o UDIMM
o RDIMM
o LRDIMM
o Fly-by Routing
• Bank State Machines, Commands, Waveforms
o DDR4
• Refresh
o Auto Refresh
o Self Refresh
o Auto Self Refresh

Recommended Prerequisites:
A basic understanding of digital logic.

Course Material:
Students will be provided a softcopy of the presentation materials used in class.

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