CURRICULAM VITAE

Name: Mudragada Srinivas

Experience ● 4+ Years of experience in Synthesis, Physical Design and STA.

Summary ● Successfully implemented block level designs from floor
planning to GDSII in 3nm, 7nm and 28nm technologies.
● Good knowledge on floorplanning, placement blockages,
optimization, routing congestion and timing optimization
during post CTS & post routing stages.
● Experience in Manual timing ECO implementation.
● Expertise in timing analysis.
● Responsible for timing closure on various blocks in ECO
cycle
● Have experience in interacting with all signoff teams and
management to achieve smooth closure of projects.
● Good Analytical, design and problem-solving skills

Skills

Tools Synthesis, Floorplan and PNR Implementation, STA – INNOVUS, DC :

Compiler, PrimeTime.
Domain Specific Synthesis, Floorplanning, Placement, CTS, Routing, STA timing
closure
Process Technology 3nm, 7nm and 28nm technologies

Career Profile
Project # 1
Client QUALCOMM
Technology 3nm / 15 metal layers
Duration 8 Months
Tools Innovus
Instance Count: 1.5M
Project Description Macro: 24 Macros
Clocks & Frequency: 12 Clocks / 312.5MHz
Responsibilities ● Floorplan, Placement and Routing.
● CI Checker clean up
● PMUX cloning according to block.
Page | 1
 ● PV/PDN fixes.
● CLP fixes
● Timing DRC fixes.
● Manual ECO implementation
● Signoff
Design Challenges: ● Place stage issues with congestion and setup timing
violation.
● CLP issues.
● CDC synchronization.
● Double Switching.
● CrossTalk
● After Route OPT stage issues with shorts and Timing.
● Secondary PG opens during ECO stage.

Project # 2 STA Engineer

Client BROADCOM
Technology 7nm / 13 metal layers
Duration 12 Months
Tools PrimeTime
Instance Count: 1.2M
Project Description Macro: 134 Macros
Clocks & Frequency: 5 Clocks / 800MHz
Scenarios: 20(10 Func + 10 Test)
Responsibilities ● Block-Level Timing Analysis and Timing closure.

Design Challenges: ● Analysed "link_design" report and resolved linking (LNK-

005, LNK-006) issues by updating link_path var with
proper libs.
● Identified missing clocks with help of "check_timing -
no_clock" report. Discussed with the SDC owner/RTLer
and got updated constraints.
● Involved in Timing budgeting. Discussed with the top-level
owner and budgeted timing. Initially started with 50%
timing budget. Also, discussed about IO environment
(input tran and output load) values, updated IO constraints.
● For setup-hold critical paths, identified divergent pins and
fixed hold violations by adding buffers at divergent pins
and setup by optimizing paths.
● Max Tran violation due to bad routing of certain logic.
● Timing Enclosure, Analysis of various reports and fixes.

Page | 2
 Project # 3 Synth & STA Engineer
Client Broadcom
Technology 7nm/ 13 metal layers
Duration 9 Months
Tools DC Compiler, PrimeTime
Project Description Instance Count: 1.1M
Macro: 45 macros
Clocks & Frequency: 5 Clocks /1GHz
Responsibilities ● Synthesis and Timing analysis at block level

Design Challenges: ● Timing not meeting at Synthesis Stage.

● Apply path_group, boundary optimization techniques to
improve timing.
● Validated timing constraints with the help of check_timing
and update_timing reports.
● Analysed clock qor report, provided feedback on bad clock
skew and latency issues.
● Timing Enclosure, Analysis of various reports and fixes.
● Analyzed timing reports, identified missing timing
exceptions. Discussed with SDC team and got updated
constraints.
● From timing reports, analyzed setup, hold and other
checks, provided feedback on bad optimization.
● Analyzed clock qor report, provided feedback on bad clock
skew and latency issues.
● Performed clock_network check to identify non-clock cells
on clock paths.

Project # 4 PD & STA Engineer

Client Marvell
Technology 7nm/ 13 metal layers
Duration 6 Months
Tools Innovus, PrimeTime
Project Description Instance Count: 1.2M
Macro: 28 Macros
Clocks & Frequency: 4 Clocks / 800MHz
Responsibilities Floorplanning, PNR, STA
Done Block Level Timing closure and fixed short violations.
Timing DRC fixes
Manual ECO Implementation
Design Challenges: ● Place stage issues with congestion.

Page | 3
 ● Violations related to EndCaps
● Macro channel congestion issues and communicated with
top level team for better floorplan estimation.
● Routing with shorts and Timing closure.
● For setup violations, analysed timing reports, identified
unique start points, end points, clock skew and bottle neck
cells. Asked PD owner to improve optimization using
path_group creation or by increasing uncertainty.
● For hold violations, analysed timing reports, identified
unique start points, end points, clock skew and hold
uncertainty. Discussed with Methodology team regarding
the reduction of hold uncertainty.
● Loaded critical corners (both Func and Test) into the
DMSA, generated ecos for max_tran, setup and hold
violations, respectively.

Project # 5 STA Engineer

Client Broadcomm
Design Tools PrimeTime
Technology 28nm / 9 Layers.
Duration 6 Months
Project Description Instance Count: 1M
Macro: 40 Macros
Layer : 13
Clocks & Frequency: 6 Clocks / 1 GHz
Responsibilities Responsible for Block Level timing closure and Timing
analysis.

Design Challenges:
● Validated given timing constraints with the help of
check_timing and update_timing reports and provided
feedback to the SDC owner.
● Discussed with the PD owner regarding bad placement
and bad routing of certain logic which led to max-tran
violations.
● Verified report_constraint report for the timing DRCs and
provided feedback to the PD owner.
● Analyzed other timing checks, setup, hold, clock-gating
setup/hold and MPW reports and also generated ecos and
provided to the PD owner.

Page | 4
Education

B.Tech (ECE) KAKIANDA INSTITUTE OF SCIENCE AND TECHNOLOGY, KORANGI.

Page | 5