Doc Title Wireless Smart Audio Module-A98 Datasheet
Pin description:
Pin No. Pin Name Type
1, 3, 5,
16, 23,
25, 27,
28, 34,
46, 50, GND Supply
53, 54,
58, 63,
64, 74,
75
Power
2,4,6 VDD_5V
I
7 GPIOZ_7 I/O
17 I2C1_SCL I/O
19 I2C1_SDA I/O
21 GPIOZ_3 I/O
29 GPIOZ_6 I/O
31 PWM_B O
33 PWM_D O
35 PWMAO_C O
37 PWMAO_D O
39 UART0_RXD I
41 UART0_TXD O
Document No.: WMB20180504
Doc Title Wireless Smart Audio Module-A98 Datasheet
43 GPIOAO_7 I/O
45 GPIOAO_6 I/O
47 PWMAO_A O
49 I2C0_SDA I/O
51 I2C0_SCL I/O
55 GPIOA_19 I/O
57 ADC_CH0 I
59 MCLK_C O
61 GPIOAO_13 I/O
65 GPIOA_20 I/O
67 USB_DM I/O
69 USB_DP I/O
71 USB_VBUS I
73 USB_ID I
18 GPIOZ_5 I/O
20 GPIOZ_1 I/O
22 GPIOZ_0 I/O
24 PWM_C I/O
26 GPIOZ_2 I/O
30 UART1_RXD I
32 UART1_TXD O
36 PDM_DIN3 I
38 PDM_DIN1 I
40 PDM_DIN2 I
42 PDM_DCLK O
44 PDM_DIN0 I
48 TDMB_DIO1 I/O
52 TDMB_SCLK I/O
56 TDMB_DIO0 I/O
60 TDMB_FS I/O
62 TDMC_DIO1 I/O
66 TDMC_DIO0 I/O
68 TDMC_FS I/O
70 TDMC_SCLK I/O
72 MCLK_B O
Table 2-1 Linkplay A98 module pin description
Notes:
1 I:Input
2 O:Output
3 P:Power
4 PU:Internal Pull Up
Document No.: WMB20180504
Number WMB20180504
Version 0.1
Figure 2-1 A98 interface pins
Function0 Function1
Digital ground
Power supply input > 500mA
General purpose input output
I2C bus1 clock
I2C bus1 data
General purpose input output
General purpose input output
Pulse Width Modulation B
Pulse Width Modulation C
Pulse Width Modulation AO_C
Pulse Width Modulation AO_D
UART0 receive
UART0 transmit
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Number WMB20180504
Version 0.1
General purpose input output
General purpose input output
Pulse Width Modulation AO_A
I2C0 bus data
I2C0 bus clock
General purpose input output
ADC input
Master clock C
General purpose input output
General purpose input output
USB data minus
USB data plus
USB voltage detection
USB ID
General purpose input output
General purpose input output
General purpose input output
Pulse Width Modulation C
General purpose input output
UART1 receive
UART1 transmit
PDM input data 3 signal
PDM input data 1 signal
PDM input data 2 signal
PDM output clock
PDM input data 0 signal
TDM B input and output data1
TDM B bit clock
TDM B input and output data0
TDM B L/R clock
TDM C input and output data1
TDM C input and output data0
TDM C L/R clock
TDM C bit clock
Master clock B
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