UNIT-IV

TRANSISTORBIASINGANDSTABILIZATION

NEEDFORTRANSISTORBIASING
If the o/p signal must be a faithful reproduction of the i/p signal, the transistor must be
operated in active region. That means an operating point has to be established in this region . To
establish an operating point (proper values of collector current I c and collector to emitter voltage V CE)
appropriate supply voltages and resistances must be suitably chosen in the ckt. This process ofselecting
proper supply voltages and resistance for obtaining desired operating point or Q point is called as
biasing and the ckt used for transistor biasing is called as biasing ckt.

Therearefourconditionstobemetbyatransistorsothatitactsasafaithfulampr:

1) Emitter base junction must be forward biased (VBE=0.7Vfor Si, 0.2V for Ge) and collector
basejunction must be reverse biased for all levels of i/p signal.
2) Vce voltageshould not fall below VCE(sat) (0.3V for Si, 0.1V for Ge) for any part of the i/p signal. For
VCE less than VCE(sat) the collector base junction is not probably reverse biased.
3) The value ofthesignal Icwhen no signalis appliedshouldbe at least equaltothemax. collector
current t due to signal alone.
4) Max. rating of the transistor Ic(max), VCE(max) and PD(max) should not be exceeded at any value ofi/p
signal.

Consider the fig shown in fig1. If operating point is selected at A, A represents a condition when no
bias is applied to the transistor i.e, I c=0, VCE =0. It does not satisfy the above said conditions necessary
for faithful amplification.

Point Cistoo closetoPD(max)curve of thetransistor.Thereforethe o/p voltage swinginthepositive

direction is limited.

Point B is located in the middle of active region .It will allow both positive and negativehalf cycles in
the o/p signal. It also provides linear gain and larger possible o/p voltages and currents

Henceoperatingpointforatransistoramplifierisselectedtobeinthemiddleofactive region.
 IC(max)

PD(max)

Vce(sat)

Fig4.1CEOutput Characteristics

DCLOADLINE
Referringtothebiasingcircuitoffig4.2a,thevaluesofVCCandRCarefixedandIcandVCEare dependent on RB.

ApplyingKirchhoff’svoltagelawtothecollectorcircuitinfig.4.2a,weget

Fig4.2aCEAmplifier circuit (b)Load line

 The straight line represented by AB in fig4.2b is called the dc load line. The coordinates of the end

point A are obtained by substituting V CE =0 in the above equation. Then . Therefore The

coordinates of A areVCE =0 and .

The coordinates of B are obtained by substituting Ic=0 in the above equation. Then Vce = Vcc.
Therefore the coordinates of B are VCE =Vcc and Ic=0. Thus the dc load line AB can be drawn if the
values of Rc and Vcc are known.

As shown in the fig4.2b, the optimum POINT IS LOCATED AT THE MID POINT OF THE MIDWAY
BETWEEN a AND b. In order to get faithful amplification, the Q point must be well within the active
region of the transistor.

Even though the Q point is fixed properly, it is very important to ensure that the operating point
remains stable where it is originally fixed. If the Q point shifts nearer to either A or B, the output
voltage and current get clipped, thereby o/p signal is distorted.

In practice, the Q-point tends to shift its position due to any or all of the following three main
factors.

1) Reversesaturationcurrent,Ico,whichdoublesforevery10oCraiseintemperature
2) BaseemitterVoltage,VBE,whichdecreasesby2.5mVperoC
3) Transistorcurrentgain,hFEorβwhichincreaseswithtemperature.

If base current IB is kept constant since IB is approximately equal to Vcc/RB. If the transistor is
replaced by another one of the same type, one cannot ensure that the new transistor will have
identical parameters as that of the first one. Parameters such as β vary over a range. This results in the
variation of collector current Ic for a given I B. Hence , in the o/p characteristics, the spacing between
the curves might increase or decrease which leads to the shifting of the Q-point to a location which
might be completely unsatisfactory.

ACLOADLINE
After drawing the dc load line, theoperatingpoint Q isproperly located at thecenter of the dc
load line. This operating point is chosen under zero input signal condition of the circuit. Hence the ac
load line should also pas through the operating point Q. The effective ac load resistance R ac, is a

combination of RC parallel to RL i.e. || . So the slope of the ac load line CQD will be .
Todrawtheacloadline,twoendpoints,I.e.VCE(max)andIC(max)whenthesignalisappliedarerequired.

,which locatespointDontheVce axis.

,which locatesthepointConthe ICaxis.

Byjoiningpointscand D,acloadline CDisconstructed.AsRC> Rac,Thedcloadlineislesssteepthan ac load line.

STABILITYFACTOR(S):
The rise of temperature results in increase in the value of transistor gain β and the leakage
current Ico. So, IC also increases which results in a shift in operating point. Therefore, The biasing
network should be provided with thermal stability. Maintenance of the operating point is specifiedby S,
which indicates the degree of change in operating point due to change in temperature.

Theextenttowhich ICisstabilizedwithvarying ICismeasuredbyastabilityfactorS

For CE configuration

Differentiatetheaboveequationw.r.tIC,Weget

Sshouldbesmalltohavebetterthermalstability.

StabilityfactorS’and S’’:

S’isdefinedastherateofchange ofICwithVBE,keepingICandVBEconstant.

S’’isdefinedastherateof changeofIC withβ,keepingICOand VBEconstant.

METHODSOFTRANSISTORBIASING

1) Fixedbias(basebias)

Fig4.3FixedBiasingCircuit

Thisformofbiasingisalsocalled basebias.Inthefig4.3shown,thesinglepowersource(forexample, battery) is

used for both collector and base of a transistor, although separate batteries can also be used.

Inthegivencircuit,

Vcc= IBRB+ Vbe

Therefore,IB=(Vcc -Vbe)/RB

SincetheequationisindependentofcurrentICR,dIB//dICR=0andthestabilityfactorisgivenbythe equation…..
reduces to

S=1+β

Sinceβisalargequantity,thisisverypoorbiasingcircuit.Thereforeinpracticethecircuitisnotusedfo biasing.

For agiventransistor,Vbedoesnot varysignificantlyduringuse.AsVccisoffixedvalue,on selectionofR the base

current IB is fixed. Therefore this type is called fixed bias type of circuit.

Alsofor givencircuit,Vcc= ICRC+ Vce

 Therefore,Vce =Vcc -ICRC

Merits:

 Itissimpletoshifttheoperatingpointanywhereintheactiveregionbymerelychanging the
base resistor (RB).
 Averysmallnumberofcomponentsare required.

Demerits:

 Thecollectorcurrentdoesnotremainconstantwithvariationintemperatureorpower
supply voltage. Therefore the operating point is unstable.
 ChangesinVbewillchangeIBandthuscauseREtochange.Thisinturnwillalterthegain of the
stage.
 Whenthetransistorisreplacedwithanotherone,considerablechangeinthevalueofβ can be
expected. Due to this change the operating point will shift.

2) EMITTER-FEEDBACKBIAS:

The emitter feedback bias circuit is shown in the fig 4.4. The fixed bias circuit is modified by
attachinganexternalresistortotheemitter.Thisresistorintroducesnegativefeedbackthatstabilizes the Q-
point. From Kirchhoff's voltage law, the voltage across the base resistor is

VRb=VCC-IeRe -Vbe.

Fig4.4SelfBiasingCircuit

FromOhm'slaw,thebasecurrentis
 Ib =VRb/Rb.

The way feedback controls the bias point is as follows. If Vbe is held constant and temperature
increases, emitter current increases.However, alarger Ie increasestheemittervoltage Ve= IeRe, which
inturnreducesthevoltageVRbacrossthebaseresistor.Alowerbase-resistorvoltagedropreducesthe base
current, which results in less collector current because Ic = ß IB. Collector current and emitter current
are related by Ic = α Ie with α ≈ 1, so increase in emitter current with temperature is opposed, and
operating point is kept stable.

Similarly,ifthetransistorisreplacedbyanother,theremaybeachangeinIC(correspondingto change
in β-value, for example). By similar process as above, the change is negated and operating point kept
stable.

Forthegivencircuit,

IB=(VCC-Vbe)/(RB+(β+1)RE).

Merits:

Thecircuithasthetendencytostabilizeoperatingpointagainstchangesintemperatureandβ-
value.

Demerits:

 Inthiscircuit,tokeepICindependentofβthefollowingconditionmustbemet:

whichisapproximatelythecase if (β+1 )RE>>RB.

 Asβ-valueisfixedforagiventransistor,thisrelationcanbesatisfiedeitherbykeeping RE very
large, or making RB very low.

 IfREisoflargevalue,highVCCisnecessary.Thisincreasescostaswellasprecautions
necessary while handling.
 IfRBislow,aseparatelowvoltagesupplyshouldbeusedinthebasecircuit.Usingtwo supplies
of different voltages is impractical.

 Inadditiontotheabove,REcausesacfeedbackwhichreducesthevoltagegainof the
amplifier.

3) COLLECTORTOBASEBIASORCOLLECTORFEED-BACK BIAS:
 Fig4.5CollectortoBaseBiasingCircuit

This configuration shown in fig 4.5 employs negative feedbackto prevent thermal runaway and
stabilize the operating point. In this form of biasing, the base resistor RBis connected to the collector
insteadofconnectingittotheDCsource Vcc.Soanythermalrunawaywillinduceavoltagedropacross the
RCresistor that will throttle the transistor's base current.

FromKirchhoff'svoltagelaw,thevoltage acrossthebaseresistorRbis

BytheEbers–Mollmodel, Ic=βIb,andso

FromOhm'slaw,thebasecurrent ,and so

Hence,thebasecurrentIbis

IfVbeisheldconstantandtemperatureincreases,thenthecollectorcurrentIcincreases.
However,alargerIccausesthevoltagedropacrossresistor Rctoincrease,whichinturnreducesthe
voltage acrossthebaseresistorRb.Alowerbase-resistorvoltagedropreducesthebasecurrent Ib, which
results in less collector current Ic. Because an increase in collector current with temperature is
opposed, the operating point is kept stable.

Merits:

 Circuitstabilizestheoperatingpointagainstvariationsintemperatureandβ(i.e.
replacement of transistor)

Demerits:

 Inthiscircuit,tokeepIcindependentofβ,thefollowingconditionmustbemet:

whichisthecasewhen

 As β-value is fixed(and generally unknown) for a giventransistor, this relation can

besatisfied either by keeping Rcfairly large or making Rbvery low.

 IfRcislarge,ahighVccisnecessary,whichincreasescostaswellasprecautionsnecessary while
handling.
 If Rbis low, the reverse bias of the collector–base region is small, which limits the range
of collector voltage swing that leaves the transistor in active mode.

 The resistor Rbcauses an AC feedback, reducing the voltage gainof the amplifier.
Thisundesirable effect is a trade-off for greater Q-pointstability.

Usage: The feedback also decreases the input impedance of the amplifier as seen from the
base, which can be advantageous. Due to the gain reduction from feedback, this biasing form is used
only when the trade-off for stability is warranted.
 4) COLLECTOR–EMITTERFEEDBACKBIAS:

Fig4.6Collector-EmitterBiasing Circuit

The above fig4.6 shows the collector –emitter feedback bias circuit that can be obtained by
applying both the collector feedback and emitter feedback. Here the collector feedback is provided by
connecting a resistance RB from the collector to the base and emitter feedback is provided by
connecting an emitter Re from emitter to ground. Both feed backs are usedto control collector
currentand base current IB in the opposite direction to increase the stability as compared to the
previous biasing circuits.

5) VOLTAGEDIVIDERBIASORSELFBIASOREMITTERBIAS

The voltage divider as shown in the fig 4.7 is formed using external resistors R 1 and R2. The
voltage across R2 forward biases the emitter junction. By proper selection of resistors R 1 and R2, the
operatingpointofthetransistorcanbemadeindependentofβ.Inthiscircuit,thevoltagedividerholds the base
voltage fixed independent of base current provided the divider current is large compared to the base
current. However, even with a fixed base voltage, collector current varies with temperature (for
example) so an emitter resistor is added to stabilize the Q-point, similar to the above circuits with
emitter resistor.
 Fig4.7VoltageDividerBiasing Circuit

Inthiscircuitthebasevoltageisgivenby:

voltageacross

provided .

Also

Forthegivencircuit,

Let the current in resistor R1 is I1 and this is divided into two parts – current through base and
resistor R2. Since the base current is very small so for all practical purpose it is assumed that I1 also
flows through R2, so we have

ApplyingKVLinthecircuit,wehave
 It is apparent from above expression that the collector current is independent of ? thus the
stability is excellent. In all practical cases the value of VBE is quite small in comparison to the V2, so it
can be ignored in the above expression so the collector current is almost independent of the transistor
parameters thus this arrangement provides excellent stability.
AgainapplyingKVLincollectorcircuit,we have

The resistor RE provides stability to the circuit. If the current through the collector rises, the
voltage across the resistor RE also rises. This will cause VCE to increase as the voltage V2 isindependent
of collector current. This decreases the base current, thus collector current increases toits former
value.
Stabilityfactorforsuchcircuitarrangementisgivenby

IfReq/REisverysmallcomparedto1,itcanbeignoredintheaboveexpressionthuswe have

Which is excellent since it is the smallest possible value for the stability. In actual practice the
value of stability factor is around 8-10, since Req/RE cannot be ignored as compared to 1.

Merits:

 Unlikeabovecircuits,onlyonedcsupplyisnecessary.
 Operatingpointisalmostindependentofβvariation.
 Operatingpointstabilizedagainstshiftintemperature.
 Demerits:

 Inthiscircuit,tokeepICindependentofβthefollowingconditionmustbemet:

which is approximately the case if

whereR1||R2denotestheequivalentresistanceofR1andR2connectedinparallel.

 As β-value is fixed for a given transistor, this relation can be satisfied either by keeping
RE fairly large, or making R1||R2 very low.

 If RE is of large value, high V CC is necessary. This increases cost as well as precautions

necessary while handling.
 If R1 || R2 is low, either R1 is low, or R2 is low, or both are low. A low R 1 raises VB closerto
VC, reducing the available swing in collector voltage, and limiting how large R C can be made without
driving the transistor out of active mode. A low R 2 lowers Vbe, reducing the allowed collector current.
Lowering both resistor values draws more current from the power supply and lowers the input
resistance of the amplifier as seen from the base.

 AC as well as DC feedback is caused by R E, which reduces the AC voltage gain of the

amplifier. A method to avoid AC feedback while retaining DC feedback is discussed below.

Usage:Thecircuit'sstabilityandmeritsasabovemakeitwidelyusedforlinearcircuits.

BIASCOMPENSATIONUSINGDIODEANDTRANSISTOR

The various biasing circuits considered use some type of negative feedback to stabilize the
operation point. Also, diodes, thermistors and sensistors can be used to compensate for variations in
current.

DIODECOMPENSATION:
 The following fig4.8 shows a transistor amplifier with a diode D connected across the base-
emitter junction for compensation of change in collector saturation current I CO. The diode is of the
same material as the transistor and it is reverse biased by e the emitter-base junction voltage V BE,
allowing the diode reverse saturation current IO to flow through diode D. The base current IB=I-IO.

As long as temperature is constant, diode D operates as a resistor. As the temperature

increases, ICO of the transistor increases. Hence, to compensate for this, the base current I B should be
decreased.

The increase in temperature will also cause the leakage current I O through D to increase and
thereby decrease the base current IB. This is the required action to keep Ic constant.

This type of bias compensation does not need a change in Ic to effect the change in I C, as bothIO
and ICO can track almost equally according to the change in temperature.

THERMISTORCOMPENSATION:

The following fig4.9 a thermistor RT, having a negative temperature coefficient is connected in
parallel with R2.The resistance of thermistor decreases exponentiallywith increase of temperature. An
increase of temperature will decrease the base voltage VBE, reducing IB and IC.
Fig4.9ThermistorCompensation

SENSISTORCOMPENSATION:

In the following fig4.10 shown a sensistor Rs having a positive temperature coefficient is

connected across R1 or RE. Rs increases with temperature. As the temperature increases, theequivalent
resistance of the parallel combination of R1 and Rs also increases and hence V BE decreases, reducing
IBand Ic. This reduced Ic compensates for increased Ic caused by the increase in V BE, ICO and β due to
temperature.
 Fig4.10Sensistor Compensation

THERMALRUNAWAYANDTHERMALSTABILITY
THERMAL RUNAWAY:

The collector current for the CE circuit is given by The three variablesin
the equation, β, , and increases with rise in temperature. In particular, the reverse saturation
current or leakage current changes greatly with temperature. Specifically it doubles for every 10 oC
rise in temperature. The collector current causes the collector base junction temperature to rise
whichinturn,increase ,asaresult willincreasestillfurther,whichwillfurtherrisethe
temperature at the collector base junction. This process will become cumulative leading at thecollector
base junction. This process will become cumulative leading to “thermal runaway”. Consequently, the
ratings of the transistor are exceeded which may destroy the transistor itself.

The collector is made larger in size than the emitter in order to help the heat developed at the
collector junction. However if the circuit is designed such that the base current is made to decrease
automaticallywithriseintemperature,thenthedecreasein willcompensateforincreaseinthe
, keeping almost constant.

THERMAL RESISTANCE

Consider transistor used in a circuit where the ambient temperature of the air around the
transistor is TAoC and the temperature of the collector-base junction of the transistor is T JoC.

Due to heating within the transistor TJ is higher than TA. As the temperature difference TJ- TA is greater,
the power dissipated in the transistor, PD will be greater, i.e, TJ- TA PD

The equation can be written as T J- TA PD. , where is the constant of proportionality and is
called the Thermal resistance. Rearranging the above equation = TJ- TA/PD. Hence is measured in
o
C/W which may be as small as 0.2 oC/W for a high power transistor that has anefficient heat sink orup
to 1000oC/W for small signal, low power transistor which have no cooling provision.

AsΘrepresentstotalthermalresistancefromatransistorjunctiontotheambienttemperature, it is
referred to as ΘJ-A.However, for power transistors, thermal resistance is given form junction to case, Θ J-
C.

Theamountresistancefromjunctiontoambienceisconsideredtoconsistof2parts.
 ΘJ-A=ΘJ-C-ΘC-A.

Which indicates the heat dissipated in the junction must make its way to the surrounding air through
two series paths from junction to case and from case to air. Hence the power dissipated.

PD =(TJ-TA ΘJ-A

=(TJ-TA ΘJ-C+ΘC-A)

ΘJ-C isdetermined bythe type of manufacture of the transistor and how it is located Ithe case, butΘ C-A is
determined by the surface area of the case or flange and its contact with air. If the effective surface
area of the transistor case could be increased, the resistance to heat flows, or could be increased Θ C-A,
could be decreased. This can be achieved by the use of a heat sink.

The heat sink is a relatively large, finned, usually black metallic heat conducting device in close
contact with transistor case or flange. Many versions of heat sink exist depending upon the shape and
size of the transistor. Larger the heat sink smaller is the thermal resistance ΘHS-A.

Thisthermal resistanceisnotadded toΘC-Ainseries,butisinsteadinparallelwithitandif

ΘHS-A is much less than Θ C-A, then ΘC-A will be reduced significantly, thereby improving the dissipation
capability of the transistor. Thus

ΘJ-A=ΘJ-C+ ΘC-A||ΘHS-A.

CONDITIONFOR THERMALSTABILITY
Forpreventingthermalrunaway,therequiredconditionItherateatwhichtheheatisreleased at the
collector junction should not exceed the rate at which the heat can be dissipated under steady state
condition. Hence the condition to be satisfied to avoid thermal runaway is given by

Ifthecircuitisproperlydesigned,thenthetransistorcannotrunawaybelowaspecifiedambient
temperatureor even under any conditions.

Intheselfbiasedcircuitthetransistorisbiasedintheactiveregion.Thepowergeneratedatthe junction
without any signal is

Letusassumethatthequiescentcollectorandtheemittercurrentsareequal.Then
 ………………….(1)

Theconditiontopreventthermalrunawaycanbewrittenas

AsΘand arepositive, shouldbenegativeinordertosatisfytheabovecondition.

Differentiatingequation(1) w.r.t we get

Hencetoavoidthermalrunawayitisnecessarythat

SinceVCE=VCC-IC(RE+RC) then eq(4) implies that VCE<VCC/2. IF the inequality of eq(4) is not satisfied

and VCE<VCC/2, then from eq(3), is positive., and the corresponding eq(2) should be satisfied.
Otherwise thermal runaway will occur.
 UNIT5

FIELDEFFECTTRANSISTOR
INTRODUCTION
1. TheFieldeffecttransistorisabbreviatedasFET ,itisananothersemiconductordevicelikea BJTwhich
can be used as an amplifier orswitch.
2. The Field effect transistor is a voltage operated device. Whereas Bipolar junction transistor is a
current controlled device. Unlike BJT a FET requires virtually no input current.
3. This gives it an extremely high input resistance , which is its most important advantage over
abipolar transistor.
4. FETisalsoathreeterminaldevice,labeledassource,drainandgate.
5. The source can be viewed as BJT’s emitter, the drain as collector, and the gate as the
counterpart of the base.
6. Thematerialthatconnectsthesourcetodrainisreferredtoasthechannel.

7. FET operation depends only on the flow of majority carriers ,therefore they are called uni polar
devices. BJT operation depends on both minority and majority carriers.

8. AsFEThasconductionthroughonlymajoritycarriersitislessnoisythanBJT.

9. FETs are much easier to fabricate and are particularly suitable for ICs because they occupy less
space than BJTs.

10. FET amplifiers have low gain bandwidth product due to the junction capacitive effects and
produce more signal distortion except for small signal operation.

11. The performance of FET is relatively unaffected by ambient temperature changes. As it hasa
negative temperature coefficient at high current levels, it prevents the FET from thermal
breakdown. The BJT has a positive temperature coefficient at high current levels which leads to
thermal breakdown.

CLASSIFICATIONOFFET:
Therearetwomajorcategoriesoffieldeffect transistors:

1. JunctionFieldEffectTransistors

2. MOSFETs

ThesearefurthersubdividedintoP-channelandN-channel devices.

MOSFETsarefurtherclassifiedintotwotypesDepletionMOSFETsandEnhancement.MOSFETs
 When the channel is of N-type the JFET is referred to as an N-channel JFET ,when the channel is of
P-type the JFET is referred to as P-channel JFET.

TheschematicsymbolsfortheP-channelandN-channelJFETsareshowninthefigure.

Fig5.1schematicsymbolsforthe P-channelandN-channelJFET

CONSTRUCTIONANDOPERATIONOFN-CHANNEL FET
Ifthe gateisanN-typematerial,the channel mustbeaP-type material.

CONSTRUCTIONOFN-CHANNELJFET

Fig5.2ConstructionofN-ChannelJFET

A piece of N- type material, referred to as channel has two smaller pieces of P-type material
attached to its sides, forming PN junctions. The channel ends are designated as the drain and
source. And the two pieces of P-type material are connected together and their terminal is called
the gate. Since this channel is in the N-type bar, the FET is known as N-channel JFET.
OPERATIONOFN-CHANNELJFET:-

TheoveralloperationoftheJFETisbasedonvaryingthewidthofthechanneltocontrolthedrain current.

A piece of N type material referred to as the channel, has two smaller pieces of P type
material attached to its sites, farming PN –Junctions. The channel’s ends are designated the drain and
the source. And the two pieces of P type material are connected together and their terminal is called
the gate. With the gate terminalnot connected and thepotential applied positive at the drain negative
at the source a drain current Id flows. When the gate is biased negative with respective to the source
the PN junctions are reverse biased and depletion regions are formed. The channel is more lightly
doped than the P type gate blocks, so the depletion regions penetrate deeply into the channel. Since
depletion region is a region depleted of charge carriers it behaves as an Insulator. The result is that the
channel is narrowed. Its resistance is increased and Id is reduced. When the negative gate bias voltage
is further increased, the depletion regions meet at the center and Id is cut off completely.

Therearetwowaystocontrolthechannelwidth

1. ByvaryingthevalueofVgs
2. AndbyVaryingthevalueofVdsholdingVgs constant

1 ByvaryingthevalueofVgs:-

We can vary the width of the channel and in turn vary the amount of drain
current. Thiscanbedone by varyingthe value ofVgs. Thispoint is illustrated in thefigbelow. Here we
are dealing with N channel FET. So channel is of N type and gate is of P type that constitutes a PN
junction. This PN junction is always reverse biased in JFET operation .The reverse bias is applied by
a battery voltage Vgs connected between the gate and the source terminal i.e positive terminal of
the battery is connected to the source and negative terminal to gate.
1) When a PN junction is reverse biased the electrons and holes diffuse across junction by leaving
immobile ions on the N and P sides , the region containing these immobile ionsis known as
depletion regions.
2) If both P and N regions are heavily doped then the depletion region extends symmetrically on
both sides.
3) But in N channel FET P region is heavily doped than N type thus depletion region extends more
in N region than P region.
4) So when no Vds is applied the depletion region is symmetrical and the conductivity becomes
Zero. Since there are no mobile carriers in the junction.
5) As the reverse bias voltage is increases the thickness of the depletion region also increases.i.e.
the effective channel width decreases .
6) ByvaryingthevalueofVgswecanvarythewidthofthechannel.

2 VaryingthevalueofVdsholdingVgsconstant:-

1) When no voltage is applied to the gate i.e. Vgs=0 , Vds is applied between source and drain the
electrons will flow from source to drain through the channel constituting drain current Id .
2) With Vgs= 0 for Id= 0 the channel between the gate junctions is entirely open .In response to a
small applied voltage Vds , the entire bar acts as a simple semi conductor resistor and the
current Id increases linearly with Vds .
3) Thechannelresistancesarerepresentedasrdandrsasshowninthefig.

4) This increasing drain current Id produces a voltage drop across rd which reverse biases the gate
to source junction,(rd> rs) .Thus the depletion region is formed which is not symmetrical .
 5) The depletion region i.e. developed penetrates deeper in to the channel near drain and less
towards source because Vrd >> Vrs. So reverse bias is higher near drain than at source.
6) As a result growing depletion region reduces the effective width of the channel. Eventually a
voltageVdsisreachedatwhichthechannelispinchedoff.Thisisthevoltage wherethe current Id
begins to level off and approach a constant value.
7) So,byvaryingthevalueofVdswecanvarythewidthofthechannelholdingVgsconstant.

WhenbothVgsandVdsisapplied:-

It is of course in principle not possible for the channel to close Completely and there by reduce
the current Id to Zero for,if such indeed, could be the case the gate voltage Vgs is applied in the
direction to provide additional reverse bias

1) When voltage is applied between the drain and source with a battery Vdd, the electrons flow
from source to drain through the narrow channel existing between the depletion regions. This
constitutes the drain current Id, its conventional direction is from drain to source.
2) The value of drain current is maximumwhen no external voltage is applied between gate and
source and is designated by Idss.
 3) When Vgs is increased beyond Zero the depletion regions are widened. This reduces the
effective width of the channel and therefore controls the flow of drain current through the
channel.
4) When Vgs is further increased a stage is reached at which to depletion regions touch each
other that means the entire channel is closed with depletion region. This reduces the drain
current to Zero.

CHARACTERISTICSOFN-CHANNELJFET
Thefamilyofcurvesthatshowstherelationbetweencurrentandvoltageareknownascharacteristic curves.

TherearetwoimportantcharacteristicsofaJFET.

1) DrainorVICharacteristics
2) Transfercharacteristics
1. DrainCharacteristics:-
2. Drain characteristics shows the relation between the drain to source voltage Vds
and drain current Id. In order to explain typical drain characteristics let usconsider the curve with
Vgs= 0.V.

1) When Vds is applied and it is increasing the drain current ID also increases linearly up to knee
point.
2) ThisshowsthatFETbehaveslikeanordinaryresistor.Thisregioniscalledasohmic region.
3) IDincreaseswithincreaseindraintosourcevoltage.Herethedraincurrentisincreased slowly as
compared to ohmic region.
 4)
5)
6)

4) It is because of the fact that there is an increase in VDS .This in turn increases the reverse bias
voltage across the gate source junction .As a result of this depletion region grows in size thereby
reducing the effective width of the channel.

5) All the drain to source voltage corresponding to point the channel width is reduced to a
minimum valueand is known as pinch off.

5)Thedraintosourcevoltageatwhichchannelpinchoffoccursiscalledpinchoffvoltage(Vp).
PINCHOFFRegion:-

1) Thisistheregionshownbythecurveassaturationregion.
2) It is also called as saturation region or constant current region. Because of the channel is
occupied with depletion region , the depletion region is more towards the drain and less
towards the source, so the channel is limited, with this only limited number of carriers are
only allowed to cross this channel from source drain causing a current that is constant inthis
region. To use FET as an amplifier it is operated in this saturation region.
3) Inthisdraincurrentremainsconstantatitsmaximumvalue IDSS.

4) Thedraincurrentinthepinchoffregiondependsuponthegatetosourcevoltageandis given by the

relation
2
Id=Idss[1-Vgs/Vp]

Thisisknownasshokley’srelation.

BREAKDOWNREGION:-

1) The region is shown by the curve .In this region, thedrain current increases rapidly as
thedrain to source voltage is increased.
2) Itisbecauseofthegatetosourcejunctionduetoavalancheeffect.
 3) The avalanche break down occurs at progressively lower value of VDS because the reverse
bias gate voltage adds to the drain voltage thereby increasing effective voltage across the
gate junction
Thiscauses

1. Themaximumsaturationdraincurrentissmaller
2. Theohmicregionportiondecreased.
4) ItisimportanttonotethatthemaximumvoltageVDSwhichcanbeappliedtoFETisthe lowest
voltage which causes available break down.
3. TRANSFER CHARACTERISTICS:-

These curves shows the relationship between drain current IDand gate to source voltage
VGSfor different values of VDS.

1) First adjust the drain to source voltage to some suitable value , then increase the gate to
source voltage in small suitable value.
2) Plot the graph between gate to source voltage along the horizontal axis and current ID on
the vertical axis. We shall obtain a curve like this.

3) As we know that if Vgsismore negative curves drain current to reduce . where V gs is made
sufficiently negative, Id is reduced to zero. This is caused by the widening of the depletion
region to a point where it is completely closes the channel. The value of V gs at the cutoff
point is designed as Vgsoff
 4) The upper end of the curveasshown bythe draincurrent value isequal toI dssthat iswhen Vgs =
0 the drain current is maximum.

5) Whilethelowerend isindicated byavoltageequal toVgsoff

6) IfVgscontinuouslyincreasing,thechannelwidthisreduced,then Id=0
7) Itmaybenotedthatcurveispartoftheparabola;itmaybeexpressedas
2
Id=Idss[1-Vgs/Vgsoff]

DIFFERENCEBETWEENVpANDVgsoff–

Vp is the value of Vgs that causes the JFET to become constant current component, It is
measured at Vgs =0V and has a constant drain current of I d =Idss .Where Vgsoff is the value of Vgs that
reducesId to approximately zero.

WhythegatetosourcejunctionofaJFETbealwaysreversebiased ?

The gate to source junction of a JFET is never allowed to become forward biased because
the gate material is not designed to handle any significant amount of current. If the junction is allowed
to become forward biased, current is generated through the gate material. This current may destroy
the component.

There is one more important characteristic of JFET reverse biasing i.e. J FET ‘s have
extremely high characteristic gate input impedance. This impedance is typically in the high mega ohm
range.Withtheadvantageofextremelyhighinputimpedanceitdrawsnocurrentfromthesource.The high
input impedance of the JFET has led to its extensive use in integrated circuits. The low current
requirements of the component makes it perfect for use in ICs. Where thousands of transistors mustbe
etched on to a single piece of silicon. The low current draw helps the IC to remain relatively cool, thus
allowing more components to be placed in a smaller physical area.

JFETPARAMETERS
The electrical behavior of JFET may be described in terms of certain parameters. Such parameters are
obtained from the characteristic curves.

A CDrainresistance(rd):

It is also called dynamic drain resistance and is the a.c.resistance between the drain and source
terminal,when the JFET is operating in the pinch off or saturation region.It is given by the ratio of small
change in drain to source voltage∆V ds tothecorresponding change in drain current∆I d for a constant
gate to source voltage Vgs.

Mathematicallyitisexpressedasrd=∆Vds/∆IdwhereVgsisheldconstant. TRANCE

CONDUCTANCE (gm):
It is also called forward transconductance. It is given by the ratio of small change in drain current (∆I d)
to the corresponding change in gate to source voltage (∆Vds)

Mathematicallythetransconductancecanbewrittenas

gm=∆Id/∆Vds

AMPLIFICATIONFACTOR(µ)

It is given by the ratio of small change in drain to source voltage (∆Vds) to the corresponding change in
gate to source voltage (∆Vgs)for a constant drain current (Id).

Thus µ=∆Vds/∆VgswhenIdheld constant

Theamplificationfactorµmaybeexpressedasaproductoftransconductance(gm)andacdrain resistance (rd)

µ=∆Vds/∆Vgs=gm rd

5.5THEFETSMALLSIGNALMODEL
ThelinearsmallsignalequivalentcircuitfortheFETcanbeobtainedinamannersimilarto that used to
derive the corresponding model for a transistor.

WecanexpressthedraincurrentiDasafunctionfofthegatevoltageanddrainvoltageV ds. Id

=f(Vgs,Vds)---------------------(1)

Thetransconductancegmanddrainresistancerd:-

Ifbothgatevoltageanddrainvoltagearevaried,thechangeinthedraincurrentis approximated by using

taylors series considering only the first two terms in the expansion

∆id= |vds=constant.∆vgs |vgs=constant∆vds

we can write ∆id=id

∆vgs=vgs

∆vds=vds

Id=gmv Vds→(1)

Where gm= |Vds |Vds

 gm= |Vds

Is the mutualconductance or transconductance .It is also called as gfs or yfs common source forward
conductance .

Thesecondparameterrdisthedrainresistanceoroutputresistanceisdefinedas

rd= |Vgs |Vgs= |

Vgsrd= |Vgs

Thereciprocaloftherdisthedrainconductancegd.ItisalsodesignatedbyYosandGosand
called the common source output conductance . So the small signal equivalent circuit for FETcan be
drawn in two different ways.

1. smallsignalcurrent–source model

2. smallsignalvoltage-source model.

A small signal current –source model for FET in commonsource configuration can be drawn
satisfyingEq→(1) as shown in the figure(a)

This low frequency model for FET has a Norton’s output circuit with a dependent current
generator whose magnitude is proportional to the gate-to –source voltage. The proportionality factoris
the transconductance ‘gm’. The output resistance is ‘rd’. The input resistance between the gate and
source is infinite, since it is assumed that the reverse biased gate draws no current. For the same
reason the resistance between gate and drain is assumed to be infinite.

Thesmallsignalvoltage-sourcemodelisshowninthefigure(b).

ThiscanbederivedbyfindingtheThevenin’sequivalentfortheoutputpartoffig(a).

These small signal models for FET can be used for analyzing the three basic FET amplifier
configurations:

1.commonsource(CS)2.commondrain(CD)orsourcefollower

3. commongate(CG).
(a)SmallSignalCurrentsourcemodelfor FET (b)SmallSignalvoltagesourcemodelforFET

Heretheinputcircuitiskeptopenbecauseofhavinghighinputimpedanceandtheoutput circuit
satisfies the equation for ID

MOSFET
WenowturnourattentiontotheinsulatedgateFETormetaloxidesemiconductorFETwhichis having the
greater commercial importance than the junction FET.

MostMOSFETShoweveraretriodes,withthesubstrateinternallyconnectedtothesource.Thecircuit symbols
used by several manufacturers are indicated in the Fig below.

(a)DepletiontypeMOSFET (b)EnhancementtypeMOSFET

BothofthemareP-channel

Herearetwobasictypesof MOSFETS

(1)Depletiontype (2)EnhancementtypeMOSFET.

D-MOSFETS can be operated in both the depletion mode and the enhancement mode. E MOSFETS
arerestrictedtooperateinenhancementmode.Theprimarydifferencebetweenthemistheirphysical
construction.
Theconstructiondifferencebetweenthetwoisshowninthefiggivenbelow.

AswecanseetheDMOSFEThavephysicalchannelbetweenthesourceanddrain terminals(Shaded
area)

The E MOSFET on the other hand has no such channel physically. It depends on the gate voltage
to form a channel between the source and the drain terminals.

Both MOSFETS have an insulating layer between the gate and the rest of the component. This
insulatinglayerismadeupofSIO2aglasslikeinsulatingmaterial.Thegatematerialismadeupof
metal conductor .Thus going from gate to substrate, we can have metal oxide semi conductor which is
where the term MOSFET comes from.

Since the gate is insulated from the rest of the component, the MOSFET is
sometimesreferred to as an insulated gate FET or IGFET.

ThefoundationoftheMOSFETiscalledthesubstrate.Thismaterialisrepresentedintheschematic symbol by
the center line that is connected to the source.

InthesymbolfortheMOSFET,thearrowisplaced onthesubstrate.AswithJFETanarrowpointingin represents an N-

channel device, while an arrow pointing out represents p-channel device.

CONSTRUCTIONOFANN-CHANNELMOSFET:-

TheN-channelMOSFETconsistsofalightlydopedptypesubstanceintowhichtwoheavilydoped n+
regions are diffused as shown in the Fig. These n+ sections , which will act as source and drain.
A thin layer of insulation silicon dioxide (SIO2) is grown over the surface of the structure, and
holes are cut into oxide layer, allowing contact with the source and drain. Then the gate metal area is
overlaidontheoxide,coveringtheentirechannelregion.Metalcontactsaremadetodrainandsource and the
contact to the metal over the channel area is the gate terminal.The metal area of the gate, in
conjunction with the insulating dielectric oxide layer and the semiconductor channel, forms a parallel
plate capacitor. The insulating layer of sio2

Isthereasonwhythisdeviceiscalledtheinsulatedgatefieldeffecttransistor.Thislayerresultsinan extremely
high input resistance (10 10 to 10power 15ohms) for MOSFET.

DEPLETION MOSFET

ThebasicstructureofD –MOSFETisshowninthefig.AnN-channelisdiffusedbetweensourceand drain

with the device an appreciable drain current IDSS flows foe zero gate to source voltage, Vgs=0.

Depletionmode operation:-
1) TheabovefigshowstheD-MOSFEToperatingconditionswithgateandsourceterminalsshorted
together(VGS=0V)

2) AtthisstageID=IDSSwhereVGS=0V,withthisvoltageVDS,anappreciabledraincurrentIDSS flows.

3) Ifthegatetosourcevoltageismadenegativei.e.VGsisnegative.Positivechargesareinducedin the
channel through the SIO2 of the gate capacitor.

4) Since the current in a FET is due to majority carriers(electrons for an N-type material) , the
inducedpositivechargesmakethechannellessconductiveandthedraincurrentdropsasVgsis made
more negative.

5) Theredistributionofchargeinthechannelcausesaneffectivedepletionofmajoritycarriers, which
accounts for the designation depletion MOSFET.

6) ThatmeansbiasingvoltageVgsdepletesthechanneloffreecarriersThiseffectivelyreducesthe width
of the channel , increasing its resistance.

7) NotethatnegativeVgshasthe sameeffectonthe MOSFETasithasonthe JFET.

8) Asshowninthefigabove,thedepletionlayergeneratedbyVgs(representedbythewhitespace
between the insulating material and the channel) cuts into the channel, reducing its width. As a
result ,Id<Idss.The actual value of ID depends on the value of Idss,Vgs(off) and Vgs.

Enhancement modeoperationoftheD-MOSFET:-

1) Thisoperatingmode isaresultofapplyingapositivegatetosource voltageVgstothedevice.

2) WhenVgsispositivethechanneliseffectivelywidened.Thisreducestheresistanceofthe channel
allowing ID to exceed the value of IDSS
3) WhenVgsisgivenpositivethemajoritycarriersinthep-typeareholes.Theholesintheptype substrate
are repelled by the +ve gate voltage.
 4) Atthesametime,theconductionbandelectrons(minoritycarriers)intheptypematerialare
attracted towards the channel by the +gate voltage.
5) Withthebuildupofelectronsnearthechannel,theareatotherightofthephysicalchannel
effectively becomes an N type material.
6) Theextendedntypechannelnowallowsmorecurrent,Id> Idss

CharacteristicsofDepletion MOSFET:-

Thefig.showsthedraincharacteristicsfortheNchanneldepletiontypeMOSFET

1) ThecurvesareplottedforbothVgspositiveandVgsnegativevoltages
.
2) WhenVgs=0andnegativetheMOSFEToperatesindepletionmodewhenVgsispositive,the
MOSFET operates in the enhancement mode.
3) ThedifferencebetweenJFETandDMOSFETisthatJFETdoesnotoperateforpositivevaluesof Vgs.

4) WhenVds=0,thereisnoconductiontakesplacebetweensourcetodrain,ifVgs<0andVds>0 then Id
increases linearly.

5) ButasVgs,0inducespositivechargesholesinthechannel,andcontrolsthechannelwidth.Thus the
conduction between source to drain is maintained as constant, i.e. Id is constant.

6) IfVgs>0thegateinducesmoreelectronsinchannelside,itisaddedwiththefreeelectrons
generatedbysource.againthepotentialappliedtogatedeterminesthechannelwidthand
maintains constant current flow through it as shown in Fig
TRANSFER CHARACTERISTICS:-

Thecombinationof3operatingstatesi.e.Vgs=0V,VGs<0V,Vgs>0VisrepresentedbytheD MOSFET
transconductance curve shown in Fig.

1) Hereinthiscurveitmaybenotedthattheregion ABofthecharacteristicssimilartothatof JFET.

2) ThiscurveextendsforthepositivevaluesofVgs
 3) Note that Id=Idss for Vgs=0V when Vgs is negative,Id< Idss when Vgs= Vgs(off) ,Id is reduced to
approximatelyomA.WhereVgsispositiveId>Idss.SoobviouslyIdssisnotthemaximumpossible value
of Id for a MOSFET.

4) ThecurvesaresimilartoJFETsothettheDMOSFEThavethesametransconductanceequation.

E-MOSFETS

TheEMOSFETiscapableofoperatingonlyintheenhancementmode.Thegatepotentialmustbe positive
w.r.t to source.

1) whenthevalueofVgs=0V,thereisnochannelconnectingthesourceanddrainmaterials.

2) Asaresult,therecanbenosignificantamountofdraincurrent.

3) WhenVgs=0,theVddsupplytriestoforcefreeelectronsfromsourcetodrainbutthepresence of p-
region does not permit the electrons to pass through it. Thus there is no drain current at
Vgs=0,

4) IfVgsispositive,itinducesanegativechargeintheptypesubstratejustadjacenttotheSIO2 layer.

5) As the holes are repelled by the positive gate voltage, the minority carrier electrons attracted
towardthisvoltage.ThisformsaneffectiveNtypebridgebetweensourceanddrainprovidinga path
for drain current.

6) This+vegatevoltageformaachannelbetweenthesourceanddrain.

7) ThisproducesathinlayerofNtypechannelinthePtypesubstarate.Thislayeroffreeelectrons is called
N type inversion layer.
 8) Theminimum Vgs which produces this inversion layer is called threshold voltage and is
designatedbyVgs(th).Thisisthepointatwhichthedeviceturnsoniscalledthethreshold voltage
Vgs(th)
9) WhenthevoltageVgsis<Vgs(th)nocurrentflowsfromdrainto source.

10) HoweverwhenthevoltageVgs>Vgs(th)theinversionlayerconnectsthedraintosourceand we get

significant values of current.

CHARACTERISTICSOFEMOSFET:-

1. DRAIN CHARACTERISTICS

ThevoltamperedraincharacteristicsofanN-channelenhancementmodeMOSFETaregiveninthe

fig.
 2. TRANSFER CHARACTERISTICS:-

1) ThecurrentIdssatVgs≤0isverysmallbeinfoftheorderofafewnano amps.
2) AsVgsismade+ve,thecurrentIdincreasesslowlyatforst,andthenmuchmorerapidlywith an
increase in Vgs.
3) ThestandardtransconductanceformulawillnotworkfortheEMOSFET.
4) TodeterminethevalueofIDatagivenvalueofVGswemustusethefollo
wingrelation Id
2
=K[Vgs-Vgs(Th)]

WhereKisconstantfortheMOSFET.foundas

K=

Fromthedataspecificationsheets,the2N7000hasthefollowingratings.

Id(on)= 75mA(minimum).

And Vgs(th)=0.8(minimum)

APPLICATIONOFMOSFET

One of the primary contributions to electronics made byMOSFETscan be found in the area of digital
(computer electronics). The signals in digital circuits are made up of rapidly switching dc levels. This
signal is called as a rectangular wave ,made up of two dc levels (or logic levels). These logic levels
are 0V and +5V.
 A group of circuits with similar circuitry and operating characteristics is referred to as a logic
family. All the circuits in a given logic family respond to the same logic levels, have similar speedand
power-handling capabilities, and can be directly connected together. One such logic family is
complementary MOS (or CMOS)logic. This logic family is made up entirely ofMOSFETs.

BIASINGFET:-

FortheproperfunctioningofalinearFETamplifier,itisnecessarytomaintainthe operating
point Q stable in the central portion of the pinch off region The Q point should be independent of
device parameter variations and ambient temperature variations

ThiscanbeachievedbysuitablyselectingthegatetosourcevoltageVGSanddraincurrentID which is
referred to as biasing

JFETbiasingcircuitsareverysimilarto BJTbiasingcircuitsThemaindifferencebetween JFET

circuits and BJT circuits is the operation of the active components themselves

TherearemainlytwotypesofBiasing circuits

1) Selfbias
2) Voltagedivider bias.

SELFBIAS
Selfbias is aJFETbiasingcircuitthat uses a source resistor to help reversebiastheJFET gate. Aself bias
circuit is shown in the fig. Self bias is the most common type of JFET bias. This JFET must be operated
such that gate source junction is always reverse biased. This condition requires a negative VGS for an N
channel JFET and a positive VGS for P channel JFET. This can be achieved using the self
biasarrangementasshowninFig.ThegateresistorRGdoesn’taffectthebiasbecauseithasessentially no
voltage drop across it, and: the gate remainsat 0V .RG is necessary only to isolate an ac signalfrom
ground in amplifier applications. The voltage drop across resistor RS makes gate source junctionreverse
biased.
 Forthedcanalysiscouplingcapacitorsareopencircuits. For

the N channel FET in Fig (a)

IS produces a voltage drop across RS and makes the source positivew.r.t ground. In any JFET circuit all
the source current passes throughthedevice to the drain circuit .This is due tothe factthat thereis no
significant gate current.

WecandefinesourcecurrentasIS= ID

(VG=0becausethereisnogatecurrentflowinginRGSoVGacrossRGiszero) VG =0

then VS= ISRS =ID RS

VGS=VG-VS=0-ID RS=-ID RS

DCanalysisofself Bias:-

InthefollowingDCanalysis,theNchannelJFETshowninthefig.isused forillustration.

ForDCanalysiswecanreplacecouplingcapacitorsbyopencircuitsandwecanalsoreplacetheresistor RG by a
short circuit equivalent.:. IG = 0.The relation between ID and VGS is given by

Id=Idss[1- ]2

VGSforNchannelJFETis=-idRs

Substutingthisvalueintheaboveequation

Id=Idss[1- ]2

Id=Idss[1+ ]2

FortheN-chanelFETinthe abovefigure
 IsproducesavoltagedropacrossRsandmakesthesourcepositivew.r.tgroundinanyJFETcircuit all the
source current passes through the device to drain circuit this is due to the fact that there is no
significant gate current. Therefore we can define source current as Is=Id and Vg=0 then

Vs=IsRs =IdRs

Vgs=Vg-Vs=0-IdRs=-IdRs

Drawingtheselfbiasline:-

TypicaltransfercharacteristicsforaselfbiasedJFETareshowninthefig.

Themaximumdraincurrentis5mAandthegatesourcecutoffvoltageis-3V.Thismeansthegate voltage
has to be between 0 and -3V.

Now using the equation VGS = -IDRS and assuming RS of any suitable value we can draw the self
biasline.

LetusassumeRS=500Ω

WiththisRs,wecanplottwopointscorrespondingtoID=0andId=IDSS for ID = 0

VGS=-IDRS

VGS=0X(500.Ω)= 0V

Sothefirstpointis(0,0)

(Id,VGS)
 ForID= IDSS=5mA

VGS=(-5mA)(500Ω)=-3V

Sothe2ndPointwillbe(5mA,-3V)

By plotting these two points, we can draw the straight line through the points. This line will
intersect the transconductance curve and it is known as self bias line.The intersection point gives the
operating point of the self bias JFET for the circuit.

AtQpoint,theIDisslightly>than2mAand VGSisslightly>-1V.TheQpointfortheselfbias JFET depends

on the value of Rs.If Rs is large, Q point far down on the transconductance curve ,ID is small, when Rs
is small Q point is far up on the curve , ID is large.

VOLTAGEDIVIDERBIAS:-

The fig. shows N channel JFET with voltage divider bias. The voltage at the source of JFET must
be more positive than the voltage at the gate in order to keep the gate to source junction reverse
biased. The source voltage is

VS =IDRS

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the
voltage divider formula.

Vg= Vdd

Fordc analysis
 ApplyingKVLtotheinputcircuit

VG-VGS-VS =0

:: VGS = VG-Vs=VG-ISRS

VGS = VG-IDRS ::IS=ID

ApplyingKVLtotheinputcircuitweget

VDS+IDRD+VS-VDD =0

::VDS = VDD-IDRD-IDRS

VDS=VDD-ID(RD+RS)

TheQpointofaJFETamplifier,usingthevoltagedividerbiasis IDQ=

IDSS [1-VGS/VP]2

VDSQ=VDD-ID(RD+RS)

COMPARISONOFMOSFETWITHJFET

a. InenhancementanddepletiontypesofMOSFET,thetransverseelectricfieldinduced
across an insulating layer deposited onthe semiconductor material controls the
conductivity of the channel.

b. IntheJFETthetransverseelectricfieldacrossthereversebiasedPNjunctioncontrolsthe
conductivity of the channel.
 c. The gateleakage current in aMOSFET isof the order of 10 -12A. Hence theinput resistance of
aMOSFETisveryhighin theorder of1010to1015 Ω.Thegateleakagecurrent of aJFET is of the
order of 10-9A., and its input resistance is of the order of 108Ω.

d. TheoutputcharacteristicsoftheJFETareflatterthanthoseoftheMOSFET,andhencethe
drainresistanceofaJFET(0.1to1MΩ)ismuchhigherthanthatofaMOSFET(1to50kΩ).

e. JFETsareoperatedonlyinthedepletionmode.ThedepletiontypeMOSFETmaybe
operated in both depletion and enhancement mode.

f. ComparingtoJFET,MOSFETsareeasiertofabricate.

g. SpecialdigitalCMOScircuitsareavailablewhichinvolvenearzeropowerdissipationand very
low voltage and current requirements. This makes them suitable for portable systems.

FETAMPLIFIERS
INTRODUCTION
Field Effect Transistor (FET) amplifiers provide an excellent voltage gain and high input
impedence.BecauseofhighinputimpedenceandothercharacteristicsofJFETstheyarepreferredover BJTs
for certain types of applications.

Thereare3basicFETcircuitconfigurations:
i) CommonSource

ii) CommonDrain
iii) CommonGain

Similar to BJT CE,CCandCBcircuits,onlydifference is inBJT largeoutputcollectorcurrentis

controlledbysmallinputbasecurrentwhereasFETcontrolsoutputcurrentbymeansofsmallinput
voltage. In both the cases output current is controlled variable.
FETamplifiercircuitsusevoltagecontrollednatureoftheJFET.InPinchoffregion,I Ddepends only on
VGS.
 CommonSource(CS)Amplifier

Fig.5.1(a)CSAmplifier(b)Small-signalequivalentcircuit

AsimpleCommonSourceamplifierisshowninFig.5.1(a)and associatedsmallsignalequivalentcircuit using

voltage-source model of FET is shown in Fig. 5.1(b)

Voltage Gain
Sourceresistance(RS)isusedtosettheQ-PointbutisbypassedbyCSformid-frequencyoperation. From the
small signal equivalent circuit ,the output voltage
VO=-RDµVgs(RD+ rd)
WhereVgs=Vi,theinputvoltage, Hence,
the voltage gain,
AV =VO/Vi=-RDµ(RD+rd)
InputImpedence

FromFig.5.1(b)InputImpedenceis Zi

=RG

ForvoltagedividerbiasasinCEAmplifiersofBJT
RG=R1║R2
Output Impedance
OutputimpedanceistheimpedancemeasuredattheoutputterminalswiththeinputvoltageV I=0 From the
Fig. 5.1(b) when the input voltage Vi= 0, Vgs= 0 and hence
µ Vgs=0
TheequivalentcircuitforcalculatingoutputimpedenceisgiveninFig.5.2. Output
impedenceZo= rd║ RD
Normallyrdwill be far greaterthanRD .HenceZo≈ RD

CommonDrainAmplifier
A simple common drain amplifier is shown in Fig. 5.2(a) and associated small signal equivalent circuit
using the voltage source model of FET is shown in Fig. 5.2(b).Since voltage V gd is more easily
determinedthanVgs,thevoltagesourceintheoutputcircuitisexpressedintermsofVgsandThevenin’s theorem.

Fig.5.2(a)CDAmplifier(b)Small-signalequivalentcircuit
Voltage Gain
Theoutputvoltage,
VO=RSµVgd/(µ+1)RS+rd
WhereVgd= Vi the inputvoltage.
Hence, the voltage gain,
Av =VO /Vi =RSµ / (µ +1) RS+rd
InputImpedence
FromFig.5.2(b),InputImpedenceZi=RG
Output Impedence
FromFig.5.2(b),Outputimpedencemeasured attheoutputterminalswithinputvoltageV i=0canbe calculated from
the following equivalent circuit.
AsVi=0:Vgd=0:µvgd/(µ+1)=0 Output
Impedence
 ZO= rd/(µ+1) ║RS
Whenµ»1
ZO= (rd/µ) ║RS=(1/gm) ║RS

BIASINGFET
FortheproperfunctioningofalinearFETamplifier,itisnecessarytomaintainthe operating
point Q stable in the central portion of the pinch off region The Q point should be independent of
device parameter variations and ambient temperature variations

ThiscanbeachievedbysuitablyselectingthegatetosourcevoltageVGSanddraincurrentIDwhichis referred
to as biasing

JFETbiasingcircuitsareverysimilartoBJTbiasingcircuitsThemaindifferencebetweenJFET circuits
and BJT circuits is the operation of the active components themselves

TherearemainlytwotypesofBiasing circuits

1. Selfbias
2. Voltagedivider bias.

5.13.1.SELFBIAS:-

SelfbiasisaJFETbiasingcircuitthatusesasourceresistortohelpreversebiastheJFETgate.

Aselfbiascircuitisshowninthefig5.3
 Self bias is the most common type of JFET bias. This JFET must be operated such that gate
source junction is always reverse biased. This condition requires a negative VGS for an N channel JFET
and apositiveVGSfor PchannelJFET.Thiscan beachievedusingthe self biasarrangementasshown in Fig
5.3. The gate resistor RG doesn’t affect the bias because it has essentially no voltage drop across it, and
: the gate remains at 0V .RG is necessary only to isolate an ac signal from ground in amplifier
applications. The voltage drop across resistor RS makes gate source junction reverse biased.

DCanalysisof self Bias:-

InthefollowingDCanalysis,theNchannelJFETshowninthefig5.4.isusedforillustration.

For DC analysis we can replace coupling capacitors by open circuits and we can also replace the
resistor RG by a short circuit equivalent.

:.IG =0

TherelationbetweenIDandVGSisgivenby

Id=Idss[1- ]2

VGSforNchannelJFETis=-idRs

Substutingthisvalueintheaboveequation

Id=Idss[1- ]2

Id=Idss[1+ ]2
FortheN-chanelFETintheabovefigure

IsproducesavoltagedropacrossRsandmakesthesourcepositivew.r.tground

inanyJFETcircuitallthesourcecurrentpassesthroughthedevicetodraincircuitthisisduetothefact that there

is no significant gate current

thereforewecandefinesourcecurrentasIs=IdandVg=0then Vs= Is

Rs =IdRs

Vgs=Vg-Vs=0-IdRs=-IdRs

Drawingtheselfbiasline:-

TypicaltransfercharacteristicsforaselfbiasedJFETareshowninthefig5.5.

Themaximumdraincurrentis6mAandthegatesourcecutoffvoltageis -3V.Thismeansthegate voltage has

to be between 0 and -3V.

Now using the equation VGS = -IDRS and assuming RS of any suitable value we can draw the self
biasline.

LetusassumeRS=500Ω

WiththisRs,wecanplottwopointscorrespondingtoID=0andId=IDSS for ID = 0

VGS=-IDRS

VGS=0X(500.Ω)= 0V
 Sothefirstpointis(0,0)

(Id,VGS)

ForID= IDSS=6mA

VGS=(-6mA)(500Ω)=-3V

Sothe2ndPointwillbe(6mA,-3V)

By plotting these two points, we can draw the straight line through the points. This line will
intersect the transconductance curve and it is known as self bias line. The intersection point gives the
operating point of the self bias JFET for the circuit.

AtQpoint,theIDisslightly>than2mAandVGSisslightly> -1V.TheQpointfortheselfbias JFET depends

on the value of Rs.If Rs is large, Q point far down on the transconductance curve ,ID is small, when Rs
is small Q point is far up on the curve , ID is large.

5.13.2VOLTAGEDIVIDERBIAS:-

The fig5.6 shows N channel JFET with voltage divider bias. The voltage at the source of JFET
mustbemorepositivethanthe voltage atthe gate in ordertokeepthe gateto sourcejunction reverse
biased. The source voltage is

VS =IDRS

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the
voltage divider formula.

Vg= Vdd
 Fordcanalysisfig5.5

ApplyingKVLtotheinputcircuit

VG-VGS-VS =0

:: VGS = VG-Vs=VG-ISRS

VGS = VG-IDRS ::IS=ID

ApplyingKVLtotheinputcircuitweget

VDS+IDRD+VS-VDD =0

::VDS = VDD-IDRD-IDRS

VDS=VDD-ID(RD+RS)

TheQpointofaJFETamplifier,usingthevoltagedividerbiasis IDQ=

IDSS [1-VGS/VP]2

VDSQ=VDD-ID(RD+RS)

JFETASAVVRORVDR
LetusconsiderthedraincharacteristicsofFETasshowninthefig.
 In this characteristics we can see that in the region before pinch off voltage, drain
characteristics are linear, i.e. FET operation is linear. In this region the FET is useful as a voltage
controlled resistor,i.e. the drain to source resistance is controlled by the bias voltage VGS.( In this
region only FET behaves like an ordinary resistor This resistances can be varied by VGS ) .The operation
of FET in the region is useful in most linear applications of FET.In such an application the FET is also
referred to as a voltage variable resistor (VVR) or voltage dependent resistor (VDR).

Thedraintosourceconductance(rd)

gd= forsmallvaluesofVDSwhichmayalsobeexpressedas

gd=gd0(1- )1/2)

Wheregd0isthevalueofdrainconductance

WhenthevariationoftherdwithVGScanbecloselyapproximatedbytheexpression

rd= )Wherero=drainresistanceatzerogatebias.K=aconstant,dependentuponFET
type.

APPLICATIONOF VVR

The VVR property of FET can be used to vary the voltage gain of a multistage amplifier A, as the
signal level is increased. This action is called AGC automatic gain control. A typical arrangement is
shown in the fig.
 Here maximum value of signal is taken rectified; filter to produce a DC voltage proportional to
the output signal level. This voltage is applied to the gate of JFET, this causing the resistance between
drain and source to change. As this resistance is connected across RE, so effective RE also changes
according to change in the drain to source resistance. When output signal level increases, the drain to
source resistance rd increases, increasing effective RE. Increase in RE causes the gain of transistor Q1to
decrease, reducing the output signal. Exactly reverse process takes place when output signal level
decreased.

:: The output signal level is maintained constant. It is to be noted that the DC bias conditions of
Q1 are not affected by JFET since FET is isolated from Q1 by capacitor C2
 EDCModelPapers
MALLAREDDYCOLLEGEOFENGINEERINGANDTECHNOLOGY, HYDERABAD
B.TechIIYearISemesterExaminations,ModelPaperI-2014

ElectronicDevicesandCircuits
(CommontoEEE,ECE,CSE,EIE,BME,IT,MCT,ETM,ECOMPE)

Time:3hours Max.Marks:75
PART-A
1. Answerallthefollowingquestions:

(a) Whatis a pnjunction?Howis it formed? (2M)

(b) Sketchtheenergy-band picturefor (3M)
i}anintrinsicii}n-typeiii} a p-typesemiconductor
Indicatesthepositionsofthefermi,thedonor &theacceptorlevels.
(c) What is meant byrectifier? (2M)
(d)Comparetheperformancemeasureofdifferentfilters. (3M)
(e)WhyTransistoris calledCurrent Controlled Device? (2M)
(f)Whatisearlyeffect?Howdoesit modifytheV-Icharacteristicsofa BJT? (3M)
(g)What is meantbyoperatingpoint?Explainits significance (2M)
(h)Whatistheconditionforthermalstabilityandthermalresistance? (3M)
(i)ExplainwhenaFET actsas avoltagevariableresistor. (2M)
(j) Explainthedrainandtransfercharacteristicsof aJFETindetails (3M)
Answerallthefollowingquestions 10x5=50

2.a) Derive an expression for total diode current starting from Boltzmann relationship in terms of the
applied voltage.
b) The reverse saturation current of a silicon p – n function diode at an operating temperature of 270C is
50 nA. Compute the dynamic forward and reverse resistances of the diode for applied voltages of 0.8 V
and -0.4 V respectively.
OR
3.a)Explaintheoperationofsiliconp–njunctiondiodeandobtaintheforwardbiasandreversebias Volt –
Ampere characteristics.
b) Obtain the transition capacitance C T of a junction diode at a reverse bias voltage of 12 V if C T of the
diode is given as 15 PF at a reverse bias of 8 V. Differentiate between transition and diffusion
capacitances.
4.a)Definethefollowingtermsofarectifier and filter:
i) Ripple Factor
ii) Regulation
iii) RectificationEfficiency
iv) FormFactor
b) What is the ripple factor if a power supply of 220 V, 50 Hz is to be Full Wave rectified and filtered
witha220μFcapacitorbeforedeliveringtoaresistiveloadof120Ω? Computethevalueofthecapacitor for the
ripple factor to be less than 15%.
OR
5.a)Deriveexpressions forripplefactor ofaFullWaveRectifier withandwithout acapacitive filter.
b) Compute the average and RMS load currents, TUFof an unfiltered centre tapped Full Wave Rectifier
specified below.
Inputvoltagetotransformer=220V/50 Hz.
Stepdownratio ofcentre tappedtransformer =4:1(Primarytoeachsectionsecondary).
Sum of transformer secondary winding in each secondary segment and diode forward resistance =100Ω.
Load resistance, RL= 220Ω.
6.a) With the help of input & output characteristics, explain the operation of a BJT in Common Emitter
Configuration.
b) For an NPN transistor with αN= 0.98, ICO= 2μA and IEO= 1.6μA connected in Common Emitter
Configuration, calculate the minimum base current for which the transistor enters into saturation region.
VCCand load resistance are given as 12 V and 4.0 KΩ respectively.
OR
7.a)Comparethecharacteristicsofa BJTinCB, CEandCC configurations.
b) A Silicon BJT is connected in common Emitter configuration with collector – to –Base bias.Calculate
the base resistance Rb for the quiescent collector – to – Emitter voltage, V CE has to be 4 V.VCC and RC are
given as 2 V and 1 KΩ respectively. Assume β= 100, V BE to be zero volts. Also find the stability factor
of the circuit.
8.a)Explainhow selfbiasingcanbedonein a BJT withrelevant sketchesand waveforms.
b) Design a self bias circuit for the following specifications: V CC = 12 V; VCE = 2V; IC = 4mA; hfe = 80.
Assume any other design parameters required. Draw the designed circuit.
OR
9.a) Explain how biasing is provided to a transistor through potential divider bias. List the assumptions
made. List the need of bias compensation methods.
b)AnNPN transistor with β=50 is usedin common Emitterconfiguration with V CC =10Vand RC=2.2 KΩ.
Biasing is done through a 100 KΩ resistance from collector – to – Base. Assuming V BE to be zero volts,
Find i) The quiescent point ii) The stability factor, „S‟.
10.a) Detail the construction of an n-channel MOSFET of depletiontype. Draw and explain its
characteristics.
b) A self biased p – channel JFET has a pinch – offvoltage of VP = 5 V and IDSS = 12 mA. Thesupply
voltage is 12 V. Determine the values of RD and RS so that ID = 5 mA and VDS = 6V.
OR
11.a) Explain the significance of threshold voltage of a MOSFET. Discuss the methods to reduce
threshold voltage, VT.
b) A FET follows the relation ID = IDSS[1 – VGS/Vp]2. What are the values of ID and gm for VGS = -1.5 V
if IDSS and VP are given as 8.4 mA and -3V respectively.
MALLAREDDYCOLLEGEOFENGINEERINGANDTECHNOLOGY, HYDERABAD

B.TechIIYearISemesterExaminations,ModelPaperII-2014

ElectronicDevicesandCircuits
(CommontoEEE,ECE,CSE,EIE,BME,IT,MCT,ETM,ECOMPE)

Time:3hours Max.Marks:75
PART-A
1.Answerallthefollowingquestions:
(a)Whatdoyou meanbypotential barrierforap-njunction? (2M)
(b)Whatis thesignificanceofnegativeresistance ofatunnel diode (3M)
(c)Definepeakinversevoltage(PIV). (2M)
(d)ExplainFWR workingprinciple with circuitand waveforms. (3M)
(e)Whatarethethree regions ofaTransistor? (2M)
(f)Whatis thermalrunway?how canit avoided? (3M)
(g)Whatisfaithfulamplification? (2M)
(h)Howα,βandγarerelatedtoeach other? (3M)
(i) Definethepinchoffvoltage (Vp)sketchthedepletionregionbeforeandafterpinchoff?(2M)
(j) DeriveExpressionfor saturationdraincurrent (3M)

Answerallthefollowingquestions: 5x10=50 marks

2. Differencebetween
i) Staticanddynamicresistancesof ap–n diode.
ii) TransitionandDiffusion capacitancesofap–n diode.
iii) Volt–Amperecharacteristicsofasinglesiliconp–ndiodeandtwoidenticalsiliconp-ndiodes connected in
parallel.
iv) Avalancheandzener breakdownmechanisms

OR
3.a)Definethefollowing termsforaPN diode
i) Dynamicresistance
ii) Loadline
iii) Differencecapacitance
 iv) Reversesaturationcurrent
b) A reverse bias voltage of 90V is applied to a Germanium diode through a resistance R. The reverse
saturationcurrentofthe diodeis50μAatanoperatingtemperatureof250C.Computethediodecurrent and
voltage for
i) R = 10 MΩ
ii) R =100 KΩ
4.a)DefineRipplefactorandform factor.Establish arelation between them.
b) Explainthe necessityofableederresistor inanL–section filterused with aFull Wavefilter.
c) Compute ripple factor of an L – section choke input filter used at the output of a Full wave
rectifierand capacitor values of the filter are given as 10 H and 8.2 μF respectively.
OR
5.a) List out the merits and demerits of Bridge type Full Wave rectifiers over centre tapped type Full Wave
rectifiers.
b) The secondary voltages of a centre tapped transformer are given as 60V-0V-60V the total resistance
of secondary coil and forward diode resistance of each section of transformer secondary is 62 Ω.
Compute the following for a load resistance of 1 KΩ.
i) Averageloadcurrent
ii) Percentageloadregulation
iii) Rectificationefficiency
iv) Ripplefactorfor 240V/50Hz supplyto primaryof transformer.
c) Whatisbleeder resistancein L –sectionfilters?
6.a)Describethesignificanceoftheterms,„α‟and„β‟.Establisharelationbetweenthem.
b) Atransistorisoperatedataforwardemittercurrentof2mAandwiththecollectoropen–circuited.
AssumingαN=0.98,IEO=1.6 μAandICO=2μA,determine
i) Thejunction voltagesVC and VE
ii) ThecollectortoEmittervoltageVCE
iii) Theregionoftransistoroperation(Saturation/Active/Cut-off).
Assume any other values necessary.
OR
7.a)Describethe functioningofa BJTin commonbaseconfiguration.
b) Determine the collector current of a BJT with both of its junctions reverse biased. Assume I CO = 5μA,
IEO = 3.58 μA, αN = 0.98 and any other parameter values as required.
 c) How do you identify the region of operation of a BJT to be saturation region from the values of
various circuit currents?
8.a) Justify statement “Potential divider bias is the most commonly used biasing method” for BJT circuits.
Explain how bias compensation can be done in such biasing through diodes.
b) An NPN transistor with β= 100 is used in common Emitter configuration with Collector – to – Base bias.
If VCC = 10 V, RC = 1 K and VBE = 0 V, determine i)Rb such that quiescent Collector – to – Emitter
Voltage is 4V.
ii) Thestabilityfactor,„S‟.
OR
9.a) Define all the four hybrid parameters of a BJT in CE configuration. Draw the circuit and its equivalent
circuit.
b)Thesourceandload resistances connectedtoaBJTamplifierin
CE configuration are 680Ω and 1 KΩ respectively. Calculate the voltage gain AV and the input resistance R i
if the h-parameters are listed as hie = 1.1 kΩ ; hre = 2×10-4; hfe= 50 and hoe= 20 μmhas. Compute AV and
Ri using both approximate and exact analysis.
10.a)Withthe helpofa neatschematic, explain thefunctioningofa commonsourceamplifier.
b) Bring out the differences between BJT and FET. Compare the three configurations of JFETamplifiers.
OR
11.a)DifferentiatebetweenenhancementanddepletionmodesofaMOSFETwiththehelpofits characteristics and
construction.
b) Determine the pinch off voltage for an N – channel silicon. JFET if the thickness of its gate region is
given as 3.2×10-4cm and the donor density in n-type region is 1.2x10-5/cm3.
c) Establisha relationbetween thethreeJFETparameters, μ,rdandgm.
 MALLAREDDYCOLLEGEOFENGINEERINGANDTECHNOLOGY, HYDERABAD
B.TechIIYearISemesterExaminations,ModelPaperIII-2014

ElectronicDevicesandCircuits
(CommontoEEE,ECE,CSE,EIE,BME,IT,MCT,ETM,ECOMPE)

Time:3hours Max.Marks:75
PART-A
Answerallthefollowingquestions:
(a)What is mean byzener breakdown (

(b)Explainthe effect of temperatureon the V-Icharacteristicsof pn junctiondiode (

(c)What is meant byfilter (

(d)Bridgerectifier is becomingmoreand morepopular, why? (

(e)WriteB.J.Tspecifications (

(f)ExplainhowtransistoractsasanAmplifier? (

(g)Whatismeant bystabilization (

(h)Whatisthermalrunway?Howcanitavoid? (

(i)Statethe applicationof JFET (

(j)WhenFETactsas avoltagevariable resistor(vvr)? (

Answerallthefollowingquestions: 5x10=50 marks

2.a)Explaintheconcept ofdiodecapacitance.Deriveexpressionfortransitioncapacitance?
b)FindthevalueofD.C.resistanceandA.CresistanceofaGermaniumjunctiondiodeat250Cwith reverse saturation
current, Io= 25μA and at an applied voltage of 0.2V across the diode.
OR
3.a)Whatdoyouunderstandbydepletionregionatp-njunction?Whatistheeffectofforwardand reverse biasing of
p-n junction on the depletion region? Explain with necessary diagrams.
b)Explain Zenerand avalanchebreakdown mechanismsin detail.

4.Definethefollowingtermsandderivetheequationswithrespecttohalf-waverectifier:i)Ripple factor ii) Peak

inverse voltage iii) Rectification efficiencyiv) % Regulation.
OR
5.a)Drawthecircuitdiagramoffull-waverectifierwithinductorfilter.Explainitsoperationwith necessary equations.
b) A HWR circuit supplies 100mA DC current to a 250Ω load. Find the DC output voltage, PIV
ratingof a diode and the r.m.s. voltage for the transformer supplying the rectifier

6.a) With neat sketches and necessary waveforms, explain the input and output characteristics of a BJT
in CB configuration. Also derive expression for output current.
b)Derivetherelation amongα, βand γ.
OR
7.a) With neat sketches and necessary waveforms, explain the input and output characteristics of a BJT
in CE configuration. Also derive expression for output current.
b)Calculatethecollectorcurrentandemittercurrentforatransistorwithα=0.99andICBO=50μA when the base
current is 20μA.

8.a) Explain the basic requirements of transistor biasing. Verify these requirements in collector to base
bias circuit.
b)Designafixedbiascircuitusingsilicontransistor,withthefollowingspecifications:VCC=16V, VBE = 0.7V,
VCEQ= 8V, ICQ = 4 mA & β= 50.
OR
9.a)What isthermal runawayin transistors?Obtain the conditionforthermalstabilityin transistors.
b)Drawthecircuitdiagram,ACequivalent&smallsignalequivalentofEmitterFolloweramplifier using
accurate h-parameter model. Derive expressions for AVs , AIs, RI & RO.

10.a) Explain the construction & operation of an N-channel enhancement and depletion MOSFET with
the help of static drain characteristics and transfer characteristics.
b)Definepinch-offvoltageandtransconductance infieldeffecttransistors.
OR
11(a)Writeshortnotesonapplications ofFET asavoltagevariable resistor.
b)ExplaintheprincipleofCSamplifierwiththehelpofcircuitdiagram.DerivetheexpressionsforA , input
V

impedance and output impedance.

 MALLAREDDYCOLLEGEOFENGINEERINGANDTECHNOLOGY, HYDERABAD
B.TechIIYearISemesterExaminations,ModelPaperIV-2014

ElectronicDevicesandCircuits
(CommontoEEE,ECE,CSE,EIE,BME,IT,MCT,ETM,ECOMPE)

Time:3hours Max.Marks:75
PART-A
1. Answerallthefollowing questions:
a) What is diodeequation? (2M)
b) Drawthev-Icharacteristics ofSCR&defineall related terms. (3M)
c) Whatisthepurposeof bleeder resistanceinarectifiercircuitusingLCfilter? (2M)
d) WriteshortnoteonFullwaverectifier(FWR) alongwith inputoutput waveforms. (3M)
e) Whyhybridparameters arecalled so?Define those (2M)
f) Whatfactors aretobe consideredforselectingtheoperatingpointQfor anamplifier?(3M)
g) Whydoespotential dividermethodofbiasing becomeuniversal? (2M)
h) Whatis themajordifferencebetween a BJT and FET? (3M)
i) Draw the symbols of JFET ( NChannel/P channel )MOSFET (Depletion MOSFET (n-
channel/p-channel)andEnhancementMOSFET(n-channel/p-channel) (2M)
j) Drawthelowfrequencyhybrid equivalentcircuit forC.E .C.Band CC (3M)

Answerallthefollowingquestions: 5x10=50 marks

2.a)Explain aboutvarious currentcomponents inaforwardbiased p-njunction diode.
b)With neatsketches andnecessarywaveforms explainabout theregulation characteristics
OR
3.a)Withneat sketchesandnecessarywaveformsexplainthe voltamperecharacteristics ofPN diode.
b) ExplainthetemperaturedependenceofVIcharacteristicsofPN diode.
c) Compareidealandpractical diodes.
4.a)Drawthecircuitoffull-waverectifierwithcapacitorfilter.Explainitsoperationwithnecessary equations.
b) Afullwaverectifiercircuitusestwosilicondiodeswithaforwardresistanceof20Ωeach.ADC voltmeter
connected across the load of 1K
Ωreads55.4volts. Calculate
i) Irms
ii) Averagevoltageacrosseachdiode
iii) ripplefactoriv)Transformersecondaryvoltagerating.
OR
5.a)Drawthecircuitoffull-waverectifierwithL-sectionfilterandderiveexpression for its
ripple factor.
b) A230 V, 60Hz voltageis applied to theprimaryofa5:1 step down, center tapped
transformerusedinafullwaverectifierhavingaloadof900Ω. Ifthediode resistanceandthesecondary coil
resistance together has a resistance of 100Ω,
determine
i) dcvoltageacross the load.
ii) dccurrent flowingthrough the load.
iii) dcpowerdeliveredtotheload.
iv) PIVacrosseach diode.
6.a) With neat sketches and necessary waveforms, explain the input and output characteristics of a BJT
in CE configuration. Also derive expression for output current.
b)Thereverseleakagecurrentof the transistor whenconnected in CB configuration
is 0.2 μA while it is 18 μA when the same transistor is connected in CE configuration. Calculate α and β
of the transistor.
OR
7.a)WiththehelpofaneatdiagramexplaindifferentcurrentcomponentsinanNPN bipolar
junction transistor.
b) Withreferencetobipolarjunctiontransistors,definethefollowingtermsand
explain.
i) Emitter efficiency.
ii) BaseTransportationfactor.
iii) Largesignal
8.a)ExplainhowICOvariationsarecompensatedwiththehelpofdiodeandthermistorintransistor biasing
circuits?
b)Design acollector tobasebias circuitusingsilicontransistor toachieveastability
factor of 20, with the following specifications: VCC = 16V, VBE = 0.7V, VCEQ= 8V, ICQ= 4mA
&β= 50.
 OR
9.a) Explain the basic requirements of transistor biasing. Verify these requirements in Emitter feedback
bias circuit.
b) An NPN Silicon transistor with β=50 is used in a common emitter circuit with VCC=10V, RC=2K.
The bias is obtained byconnecting a 100K resistance from collector to base. Find i) Q-Point ii) Stability
factor, S

10.a) Explain the construction & operation of an P-channel enhancement and depletion MOSFET with
the help of static drain characteristics and transfer characteristics.
b)Explainwhyfieldeffecttransistor iscalled asunipolarand voltagecontrolled device
OR
11.a)Withneatsketches,necessaryequationsexplainthedrain&transfer
characteristics of MOSFET in enhancement mode.
b)WhyisaFieldEffectTransistorcalledunipolar&voltagecontrolleddevice?Explainthedrain& transfer
characteristics of a JFET in detail.
 MALLAREDDYCOLLEGEOFENGINEERINGANDTECHNOLOGY, HYDERABAD
B.TechIIYearISemesterExaminations,ModelPaperV-2014

ElectronicDevicesandCircuits
(CommontoEEE,ECE,CSE,EIE,BME,IT,MCT,ETM,ECOMPE)

Time:3hours Max.Marks:75
1. Answerallthefollowingquestions: 5x2=10 marks
a) Whatis“darkcurrent” ofaphoto diode? (2M)
b) Whichtypeof diodecapacitanceis usedinthevaractordiode,explain. (3M)
c) WhatisDiffusion andDrift Currents? (2M)
d) Deriveripple factorofFWR. (3M)
e) Whatis a dcpower supply(Regulated power supply)? (2M)
f) Drawthe characteristicsofPhotoDiode. (3M)
g) Definereverseleakage currentinC.Econfiguration (2M)
h) CompareCB, CEand CC configurations. (3M)
i) Definethe four-hparameters (2M)
j) Explain the JFETsmall signal model (3M)
Answer all the following questions: 5x10= 50 marks
1a)Explaintheformationofdepletionregioninanopencircuitedpnjunctionwithneat Sketches.
b)Thevoltageacrossasilicondiodeatroomtemperatureof300oKis0.7Vwhen2mA Current flows
through it. If the voltage increases to 0.75V, calculate the diode current.
(OR)
3.Discuss theconstructional detailsof SCR andSchotkybarrier diode.

2. A HWR circuit supplies 100mA DC current to a 250Ω load. Find the DC output voltage, PIV ratingof
a diode and the r.m.s. voltage for the transformer supplying the rectifier
(OR)
Drawthecircuitoffull-waverectifierwithcapacitorfilter.Explainitsoperationwithnecessary equations.
3. The reverse leakage current of the transistor, when connected in CB configuration is 0.2mA, while it
is 18 m A when the same transistor is connected in CE configuration.
Calculateαand β of the transistor
(OR)
a) Comparethe threetransistor amplifierconfigurations withrelated to A,A,RandR.
I V i O

b) FortheemitterfollowerwithR=0.5K,R=50K,h=-50,h=1K,h=25μA/V,h=1.Calculate
S L fe ie oe re

A, A,ZandZ.
V I i O

4. Drawafixedbiascircuitandexplainitsoperation.CalculatetheStabilityfactor
(OR)
(a)Whatisthermal runawayin transistors?Obtain thecondition forthermal stabilityin transistors.
b)Designaselfbiascircuitusingsilicontransistortoachieveastabilityfactorof10,withthefollowing
specifications:V
CC =16V, V =0.7V, V =8V,I =4 mA&β =50.
BE CEQ CQ

5. a)Writetheexpressionsformid-frequencygainof aFET CommonSourceAmplifier.

b)Discuss thehighfrequencyresponseof CD Configuration.
(OR)
ExplaintheworkingofMOSFETini)Enhancementmodeii)Depletionmode. Draw
the necessary diagrams and graphs.