16-Bit, 100 kSPS, Single-Ended

PulSAR ADC in MSOP/QFN

Data Sheet AD7683
FEATURES APPLICATION DIAGRAM
0.5V TO VDD 2.7V TO 5.5V
16-bit resolution with no missing codes
Throughput: 100 kSPS
INL: ±1 LSB typical, ±3 LSB maximum
REF VDD
0V TO VREF
Pseudo differential analog input range +IN DCLOCK
0 V to VREF with VREF up to VDD –IN AD7683 DOUT
3-WIRE SPI
INTERFACE
Single-supply operation: 2.7 V to 5.5 V GND
CS

04301-001
Serial interface SPI/QSPI/MICROWIRE/DSP compatible
Power dissipation: 4 mW @ 5 V, 1.5 mW @ 2.7 V,
Figure 1.
150 μW @ 2.7 V/10 kSPS
Standby current: 1 nA
8-lead packages:
MSOP
Table 1. MSOP, QFN (LFCSP)/SOT-23, 14-/16-/18-Bit
3 mm × 3 mm QFN (LFCSP) (SOT-23 size) PulSAR ADC
400 kSPS
Improved second source to ADS8320 and ADS8325
100 250 to ≥1000 ADC
Type kSPS kSPS 500 kSPS kSPS Driver
18-Bit True AD7691 AD7690 AD7982 ADA4941-1
APPLICATIONS Differential AD7984 ADA4841-1
Battery-powered equipment 16-Bit True AD7684 AD7687 AD7688 ADA4941-1
Data acquisition Differential AD7693 ADA4841-1
Instrumentation 16-Bit AD7680 AD7685 AD7686 AD7980 ADA4841-1
Pseudo AD7683 AD7694
Medical instruments Differential
Process control 14-Bit AD7940 AD7942 AD7946 ADA4841-1
Pseudo
Differential
GENERAL DESCRIPTION
The AD7683 is a 16-bit, charge redistribution, successive analog input, +IN, between 0 V to REF with respect to a ground
approximation, PulSAR® analog-to-digital converter (ADC) sense, –IN. The reference voltage, REF, is applied externally and
that operates from a single power supply, VDD, between 2.7 V can be set up to the supply voltage. Its power scales linearly with
and 5.5 V. It contains a low power, high speed, 16-bit sampling throughput.
ADC with no missing codes (B grade), an internal conversion The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN
clock, and a serial, SPI-compatible interface port. The part also (LFCSP) package, with an operating temperature specified from
contains a low noise, wide bandwidth, short aperture delay, −40°C to +85°C.
track-and-hold circuit. On the CS falling edge, it samples an

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD7683 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Circuit Information.................................................................... 12
Applications ....................................................................................... 1 Converter Operation.................................................................. 12
Application Diagram ........................................................................ 1 Transfer Functions ..................................................................... 12
General Description ......................................................................... 1 Typical Connection Diagram ................................................... 13
Revision History ............................................................................... 2 Analog Input ............................................................................... 13
Specifications..................................................................................... 3 Driver Amplifier Choice ........................................................... 13
Timing Specifications .................................................................. 5 Voltage Reference Input ............................................................ 14
Absolute Maximum Ratings............................................................ 6 Power Supply............................................................................... 14
Thermal Resistance ...................................................................... 6 Digital Interface .......................................................................... 14
ESD Caution .................................................................................. 6 Layout .......................................................................................... 14
Pin Configurations and Function Descriptions ........................... 7 Evaluating the AD7683 Performance ...................................... 14
Terminology ...................................................................................... 8 Outline Dimensions ....................................................................... 15
Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 16
Applications Information .............................................................. 12

REVISION HISTORY
2/16—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 1
Added Figure 7 and Table 9; Renumbered Sequentially ............. 7
Changes to Table 10 ........................................................................ 13
Changes to Digital Interface Section............................................ 14
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16

2/08—Rev. 0 to Rev. A
Change to Title .................................................................................. 1
Moved Figure 3, Figure 4, and Figure 5 ......................................... 5
Changes to Figure 4 .......................................................................... 5
Moved Figure 17 and Figure 18 .................................................... 11
Changes to Figure 22 ...................................................................... 13
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16

9/04—Initial Version: Revision 0

Rev. B | Page 2 of 16
Data Sheet AD7683

SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted.

Table 2.
AD7683 All Grades
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range +IN − (–IN) 0 VREF V
Absolute Input Voltage +IN −0.1 VDD + 0.1 V
−IN −0.1 0.1 V
Analog Input CMRR fIN = 100 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
THROUGHPUT SPEED
Complete Cycle 10 µs
Throughput Rate 0 100 kSPS
DCLOCK Frequency 0 2.9 MHz
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 100 kSPS, V+IN − V−IN = VREF/2 = 2.5 V 50 µA
DIGITAL INPUTS
Logic Levels
VIL −0.3 0.3 × VDD V
VIH 0.7 × VDD VDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
Input Capacitance 5 pF
DIGITAL OUTPUTS
Data Format Serial, 16 bits straight binary
VOH ISOURCE = −500 µA VDD − 0.3 V
VOL ISINK = +500 µA 0.4 V
POWER SUPPLIES
VDD Specified performance 2.7 5.5 V
VDD Range1 2.0 5.5 V
Operating Current 100 kSPS throughput
VDD VDD = 5 V 800 µA
VDD = 2.7 V 560 µA
Standby Current2, 3 VDD = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5 V 4 6 mW
VDD = 2.7 V 1.5 mW
VDD = 2.7 V, 10 kSPS throughput2 150 µW
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +85 °C
1
See the Typical Performance Characteristics section for more information.
2
With all digital inputs forced to VDD or GND, as required.
3
During acquisition phase.

Rev. B | Page 3 of 16
AD7683 Data Sheet
VDD = 5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted.

Table 3.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.5 0.5 LSB
Gain Error1, TMIN to TMAX ±2 ±24 ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, TMIN to TMAX ±0.7 ±1.6 ±0.4 ±1.6 mV
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 LSB
AC ACCURACY
Signal-to-Noise fIN = 1 kHz 90 88 91 dB2
Spurious-Free Dynamic Range fIN = 1 kHz −100 −108 dB
Total Harmonic Distortion fIN = 1 kHz −100 −106 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 90 88 91 dB
Effective Number of Bits fIN = 1 kHz 14.7 14.8 Bits
1
See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference.
2
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

VDD = 2.7 V; VREF = 2.5V; TA = –40°C to +85°C, unless otherwise noted.

Table 4.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.85 0.85 LSB
Gain Error1, TMIN to TMAX ±2 ±30 ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, TMIN to TMAX ±0.7 ±3.5 ±0.7 ±3.5 mV
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity VDD = 2.7 V ±5% ±0.05 ±0.05 LSB
AC ACCURACY
Signal-to-Noise fIN = 1 kHz 85 86 dB2
Spurious-Free Dynamic Range fIN = 1 kHz −96 −100 dB
Total Harmonic Distortion fIN = 1 kHz −94 −98 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 85 86 dB
Effective Number of Bits fIN = 1 kHz 13.8 14 Bits
1
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
2
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

Rev. B | Page 4 of 16
Data Sheet AD7683
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted.

Table 5.
Parameter Symbol Min Typ Max Unit
Throughput Rate tCYC 100 kHz
CS Falling to DCLOCK Low tCSD 0 μs
CS Falling to DCLOCK Rising tSUCS 20 ns
DCLOCK Falling to Data Remains Valid tHDO 5 16 ns
CS Rising Edge to DOUT High Impedance tDIS 14 100 ns
DCLOCK Falling to Data Valid tEN 16 50 ns
Acquisition Time tACQ 400 ns
DOUT Fall Time tF 11 25 ns
DOUT Rise Time tR 11 25 ns

Timing and Circuit Diagrams

tCYC
COMPLETE CYCLE
CS

tSUCS tACQ
POWER DOWN

DCLOCK 1 4 5

tCSD tEN tHDO tDIS

HIGH-Z HIGH-Z
DOUT 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
(MSB) (LSB)
NOTES

04301-002
1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.

Figure 2. Serial Interface Timing

500µA IOL

TO DOUT 1.4V
CL
100pF
04301-003

500µA IOH

Figure 3. Load Circuit for Digital Interface Timing

2V
0.8V

tEN tEN
04301-004

2V 2V
0.8V 0.8V

Figure 4. Voltage Reference Levels for Timing

90%
DOUT
10%
04301-006

tR tF

Figure 5. DOUT Rise and Fall Timing

Rev. B | Page 5 of 16
AD7683 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
Analog Inputs stress rating only; functional operation of the product at these
+IN1, –IN1 GND − 0.3 V to VDD + 0.3 V or or any other conditions above those indicated in the operational
±130 mA
section of this specification is not implied. Operation beyond
REF GND − 0.3 V to VDD + 0.3 V
the maximum operating conditions for extended periods may
Supply Voltages
affect product reliability.
VDD to GND −0.3 V to +6 V
Digital Inputs to GND −0.3 V to VDD + 0.3 V THERMAL RESISTANCE
Digital Outputs to GND −0.3 V to VDD + 0.3 V
Storage Temperature Range −65°C to +150°C Table 7. Thermal Resistance
Junction Temperature 150°C Package Type θJA θJC Unit
Lead Temperature Range JEDEC J-STD-20 8-Lead MSOP 200 44 °C/W
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C ESD CAUTION
1
See the Analog Input section.

Rev. B | Page 6 of 16
Data Sheet AD7683

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF 1 8 VDD
+IN 2 AD7683 DCLOCK7

–IN 3 TOP VIEW 6 DOUT

04301-005
(Not to Scale)
GND 4 5 CS

Figure 6. 8-Lead MSOP Pin Configuration

Table 8. 8-Lead MSOP Pin Function Descriptions

Pin No. Mnemonic Type1 Function
1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the
REF pin closely to the GND pin with a ceramic capacitor of a few μF.
2 +IN AI Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V
to VREF.
3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground.
4 GND P Power Supply Ground.
5 CS DI Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as
soon as the conversion is completed. It also enables DOUT. When high, DOUT is high impedance.
6 DOUT DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK.
7 DCLOCK DI Serial Data Clock Input.
8 VDD P Power Supply.
1
AI = analog input; DI = digital input; DO = digital output; and P = power.

REF 1 8 VDD
+IN 2 AD7683 7 DCLOCK
TOP VIEW
–IN 3 (Not to Scale) 6 DOUT
GND 4 5 CS

NOTES
04301-107

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION

IS NOT REQUIRED TO MEET SPECIFIED ELECTRICAL PERFORMANCE.

Figure 7. 8-Lead QFN (LFCSP) Pin Configuration

Table 9. 8-Lead QFN (LFCSP) Pin Function Descriptions

Pin No. Mnemonic Type1 Function
1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the
REF pin closely to the GND pin with a ceramic capacitor of a few μF.
2 +IN AI Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V
to VREF.
3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground.
4 GND P Power Supply Ground.
5 CS DI Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as
soon as the conversion is completed. It also enables DOUT. When high, DOUT is high impedance.
6 DOUT DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK.
7 DCLOCK DI Serial Data Clock Input.
8 VDD P Power Supply.
EPAD Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet specified
electrical performance.
1
AI = analog input; DI = digital input; DO = digital output; and P = power.

Rev. B | Page 7 of 16
AD7683 Data Sheet

TERMINOLOGY
Integral Nonlinearity Error (INL) Signal-to-(Noise + Distortion) Ratio (SINAD)
Linearity error refers to the deviation of each individual code SINAD is the ratio of the rms value of the actual input signal to
from a line drawn from negative full scale through positive the rms sum of all other spectral components below the Nyquist
full scale. The point used as negative full scale occurs ½ LSB frequency, including harmonics but excluding dc. The value for
before the first code transition. Positive full scale is defined as SINAD is expressed in dB.
a level 1½ LSB beyond the last code transition. The deviation Effective Number of Bits (ENOB)
is measured from the middle of each code to the true straight ENOB is a measurement of the resolution with a sine wave
line (see Figure 22). input. It is related to SINAD (as represented by S/(N+D)) by
Differential Nonlinearity Error (DNL) the following formula and is expressed in bits:
In an ideal ADC, code transitions are 1 LSB apart. DNL is the ENOB = (S /[N + D ]dB − 1.76 ) / 6.02
maximum deviation from this ideal value. It is often specified in
Total Harmonic Distortion (THD)
terms of resolution for which no missing codes are guaranteed.
THD is the ratio of the rms sum of the first five harmonic
Offset Error components to the rms value of a full-scale input signal and is
The first transition should occur at a level ½ LSB above analog expressed in dB.
ground (38.1 µV for the 0 V to 5 V range). The offset error is
Signal-to-Noise Ratio (SNR)
the deviation of the actual transition from that point.
SNR is the ratio of the rms value of the actual input signal to
Gain Error the rms sum of all other spectral components below the Nyquist
The last transition (from 111...10 to 111...11) should occur for frequency, excluding harmonics and dc. The value for SNR is
an analog voltage 1½ LSB below the nominal full scale expressed in dB.
(4.999886 V for the 0 V to 5 V range). The gain error is the
Aperture Delay
deviation of the actual level of the last transition from the ideal
Aperture delay is a measure of the acquisition performance and
level after the offset has been adjusted out.
is the time between the falling edge of the CS input and when
Spurious-Free Dynamic Range (SFDR) the input signal is held for a conversion.
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal. Transient Response
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.

Rev. B | Page 8 of 16
Data Sheet AD7683

TYPICAL PERFORMANCE CHARACTERISTICS

3 3
POSITIVE INL = +0.43LSB POSITIVE DNL = +0.43LSB
NEGATIVE INL = –0.97LSB NEGATIVE DNL = –0.41LSB
2 2

1 1

DNL (LSB)
INL (LSB)

0 0

–1 –1

–2 –2

04301-012

04301-011
–3 –3
0 16384 32768 49152 65536 0 16384 32768 49152 65536
CODE CODE
Figure 8. Integral Nonlinearity vs. Code Figure 11. Differential Nonlinearity vs. Code

7000 120000
62564 VDD = REF = 2.5V VDD = REF = 5V
102287
6000
100000

5000
80000

4000
COUNTS

COUNTS

35528
60000
3000
25440
40000
2000

1000 20000 15152 13619

04301-009

4604

04301-010
2755 8
0 0 1 50 130 0 0 0 0 6 0 0
0 0
79FD 79FE 79FF 7A00 7A01 7A02 7A03 7A04 7A05 7A06 7A07 7A08 7A0E 7A0F 7A10 7A11 7A12 7A13 7A14 7A15 7A16
CODE IN HEX CODE IN HEX
Figure 9. Histogram of a DC Input at the Code Center Figure 12. Histogram of a DC Input at the Code Center

0 0
16384 POINT FFT 16384 POINT FFT
VDD = REF = 5V VDD = REF = 2.5V
–20 –20
fS = 100kSPS fS = 100kSPS
fIN = 20.43kHz fIN = 20.43kHz
AMPLITUDE (dB OF FULL SCALE)

AMPLITUDE (dB OF FULL SCALE)

–40 SNR = 92.7dB –40 SNR = 88.7dB

THD = –105.7dB THD = –102.6dB
–60 SFDR = –106.4dB –60 SFDR = –104.6dB

–80 –80

–100 –100

–120 –120

–140 –140

–160
04301-008

–160
04301-007

–180 –180
0 10 20 30 40 50 0 10 20 30 40 50
FREQUENCY (kHz) FREQUENCY (kHz)
Figure 10. FFT Plot Figure 13. FFT Plot

Rev. B | Page 9 of 16
AD7683 Data Sheet
100 17 –80

–85
VREF 2.5V = –1dB
95 16
SNR
–90
SNR, SINAD (dB)

ENOB (Bits)

THD (dB)
90 15 –95

SINAD
VREF 5V = –1dB
ENOB –100

85 14
–105

04301-013

04301-015
80 13 –110
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 40 80 120 160 200
REFERENCE VOLTAGE (V) FREQUENCY (kHz)

Figure 14. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. THD vs. Frequency

100 1200
fS = 100kSPS
95 1000
VREF = 5V, –10dB

OPERATING CURRENT (µA)

90 800
VREF = 5V, –1dB
SINAD (dB)

85 600

VREF = 2.5V, –1dB

80 400

75 200
04301-014

04301-017
70 0
0 50 100 150 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
FREQUENCY (kHz) SUPPLY (V)

Figure 15. SINAD vs. Frequency Figure 17. Operating Current vs. Supply

Rev. B | Page 10 of 16
Data Sheet AD7683
900 6
VDD = 5V, fS = 100kSPS
5
800
4
700

OFFSET, GAIN ERROR (LSB)

3
OPERATING CURRENT (µA)

600 2
OFFSET ERROR
VDD = 2.7V, fS = 100kSPS 1
500
0
400
–1
300 –2
GAIN ERROR
–3
200
–4
100

04301-018

04301-016
–5

0 –6
–55 –34 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 18. Operating Current vs. Temperature Figure 20. Offset and Gain Error vs. Temperature

1000
POWER-DOWN CURRENT (nA)

750

500

250
04301-019

0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)

Figure 19. Power-Down Current vs. Temperature

Rev. B | Page 11 of 16
AD7683 Data Sheet

APPLICATIONS INFORMATION
+IN

SWITCHES CONTROL
MSB LSB SW+

32,768C 16,384C 4C 2C C C BUSY

REF
CONTROL
COMP
LOGIC
GND
OUTPUT CODE
32,768C 16,384C 4C 2C C C

MSB LSB SW–

CNV

04301-020
–IN

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION array between GND and REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4...VREF/65,536).
The AD7683 is a low power, single-supply, 16-bit ADC using a The control logic toggles these switches, starting with the MSB,
successive approximation architecture. to bring the comparator back into a balanced condition. After
The AD7683 is capable of converting 100,000 samples per the completion of this process, the part returns to the acquisition
second (100 kSPS) and powers down between conversions. phase and the control logic generates the ADC output code.
When operating at 10 kSPS, for example, it consumes typically
TRANSFER FUNCTIONS
150 µW with a 2.7 V supply, ideal for battery-powered
applications. The ideal transfer function for the AD7683 is shown in Figure 22
and Table 10.
The AD7683 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
ADC CODE (STRAIGHT BINARY)

111...111
The AD7683 is specified from 2.7 V to 5.5 V. It is housed in an 111...110
8-lead MSOP or a tiny, 8-lead QFN (LFCSP) package. 111...101

The AD7683 is an improved second source to the ADS8320 and

ADS8325. For even better performance, consider the AD7685.
CONVERTER OPERATION
The AD7683 is a successive approximation ADC based on a
000...010
charge redistribution DAC. Figure 21 shows the simplified 000...001
schematic of the ADC. The capacitive DAC consists of two 000...000
–FS –FS + 1 LSB
identical arrays of 16 binary-weighted capacitors that connect +FS – 1 LSB
–FS + 0.5 LSB +FS – 1.5 LSB 04301-021
to the two comparator inputs.
ANALOG INPUT
During the acquisition phase, terminals of the array tied to the Figure 22. ADC Ideal Transfer Function
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs. Table 10. Output Codes and Ideal Input Voltages
Thus, the capacitor arrays are used as sampling capacitors and Analog Input Digital Output Code
acquire the analog signal on the +IN and −IN inputs. When the Description VREF = 5 V Hexadecimal
acquisition phase is complete and the CS input goes low, a con- FSR – 1 LSB 4.999924 V FFFF1
Midscale + 1 LSB 2.500076 V 8001
version phase is initiated. When the conversion phase begins,
Midscale 2.5 V 8000
SW+ and SW− are opened first. The two capacitor arrays are
Midscale – 1 LSB 2.499924 V 7FFF
then disconnected from the inputs and connected to the GND
–FSR + 1 LSB 76.3 µV 0001
input. Therefore, the differential voltage between the inputs,
–FSR 0V 00002
+IN and −IN, captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to 1
This is also the code for an overranged analog input (V+IN – V–IN above
VREF – VGND).
become unbalanced. By switching each element of the capacitor 2
This is also the code for an underranged analog input (V+IN – V–IN below VGND).

Rev. B | Page 12 of 16
Data Sheet AD7683
(NOTE 1)
REF 2.7V TO 5.25V
CREF
100nF
2.2µF TO 10µF
(NOTE 2)

REF VDD
33Ω
+IN
0V TO VREF DCLOCK
(NOTE 3) 2.7nF AD7683
DOUT 3-WIRE INTERFACE

(NOTE 4) –IN CS
GND

NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

04301-022
3. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.

Figure 23. Typical Application Diagram

TYPICAL CONNECTION DIAGRAM pass filter that reduces undesirable aliasing effects and limits
Figure 23 shows an example of the recommended application the noise.
diagram for the AD7683. When the source impedance of the driving circuit is low, the
AD7683 can be driven directly. Large source impedances signi-
ANALOG INPUT
ficantly affect the ac performance, especially THD. The dc
Figure 24 shows an equivalent circuit of the input structure of performances are less sensitive to the input impedance.
the AD7683. The two diodes, D1 and D2, provide ESD protec-
tion for the analog inputs, +IN and −IN. Care must be taken to DRIVER AMPLIFIER CHOICE
ensure that the analog input signal never exceeds the supply rails Although the AD7683 is easy to drive, the driver amplifier
by more than 0.3 V because this causes these diodes to become needs to meet the following requirements:
forward-biased and start conducting current. However, these  The noise generated by the driver amplifier needs to be
diodes can handle a forward-biased current of 130 mA maximum. kept as low as possible to preserve the SNR and transition
For instance, these conditions can eventually occur when the noise performance of the AD7683. Note that the AD7683
input buffer (U1) supplies are different from VDD. In such a has a noise figure much lower than most other 16-bit
case, use an input buffer with a short-circuit current limitation ADCs and, therefore, can be driven by a noisier op amp
to protect the part. while preserving the same or better system performance.
VDD
The noise coming from the driver is filtered by the AD7683
D1 CIN
analog input circuit, 1-pole, low-pass filter made by RIN
+IN RIN
OR –IN
and CIN or by the external filter, if one is used.
CPIN D2
 For ac applications, the driver needs to have a THD
04301-023

GND
performance suitable to that of the AD7683. Figure 16 shows
the THD vs. frequency that the driver should exceed.
Figure 24. Equivalent Analog Input Circuit
 For multichannel multiplexed applications, the driver
This analog input structure allows the sampling of the differen-
amplifier and the AD7683 analog input circuit must be
tial signal between +IN and −IN. By using this differential input,
able to settle for a full-scale step of the capacitor array at a
small signals common to both inputs are rejected. For instance,
16-bit level (0.0015%). In the amplifier data sheet, settling
by using −IN to sense a remote signal ground, ground potential
at 0.1% to 0.01% is more commonly specified. This could
differences between the sensor and the local ADC ground are
differ significantly from the settling time at a 16-bit level
eliminated. During the acquisition phase, the impedance of the
and should be verified prior to driver selection.
analog input, +IN, can be modeled as a parallel combination of
Capacitor CPIN and the network formed by the series connection Table 11. Recommended Driver Amplifiers
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically Amplifier Typical Application
600 Ω and is a lumped component consisting of some serial ADA4841-1 Very low noise and low power
resistors and the on resistance of the switches. CIN is typically OP184 Low power, low noise, and low frequency
30 pF and is mainly the ADC sampling capacitor. During the AD8605, AD8615 5 V single-supply, low power
conversion phase, when the switches are opened, the input AD8519 Low power and low frequency
impedance is limited to CPIN. RIN and CIN make a 1-pole, low- AD8031 High frequency and low power

Rev. B | Page 13 of 16
AD7683 Data Sheet
VOLTAGE REFERENCE INPUT DCLOCK falling edges. The data is valid on both DCLOCK
The AD7683 voltage reference input, REF, has a dynamic input edges. Although the rising edge can be used to capture the data,
impedance. Therefore, it should be driven by a low impedance a digital host also using the DCLOCK falling edge allows a
source with efficient decoupling between the REF and GND faster reading rate, provided it has an acceptable hold time.
pins, as explained in the Layout section.
CONVERT
When REF is driven by a very low impedance source (such as
CS DIGITAL HOST
an unbuffered reference voltage like the low temperature drift
AD7683
ADR435 reference or a reference buffer using the AD8031 or DOUT DATA IN
DCLOCK
the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is

04301-025
appropriate for optimum performance. CLK

If desired, smaller reference decoupling capacitors with values Figure 26. Connection Diagram
as low as 2.2 μF can be used with a minimal impact on perfor- LAYOUT
mance, especially DNL.
Design the PCB that houses the AD7683 so that the analog and
POWER SUPPLY digital sections are separated and confined to certain areas of
The AD7683 powers down automatically at the end of each the board. The pin configuration of the AD7683, with all its
conversion phase and, therefore, the power scales linearly with analog signals on the left side and all its digital signals on the
the sampling rate, as shown in Figure 25. This makes the part right side, eases this task.
ideal for low sampling rates (even of a few Hz) and low battery- Avoid running digital lines under the device because these
powered applications. couple noise onto the die, unless a ground plane under the
1000
AD7683 is used as a shield. Fast switching signals, such as CS
or clocks, should never run near analog signal paths. Avoid
VDD = 5V crossover of digital and analog signals.
100
OPERATING CURRENT (µA)

Use at least one ground plane. It can be common or split between

VDD = 2.7V the digital and analog sections. In such a case, it should be joined
10
underneath the AD7683.
1 The AD7683 voltage reference input (REF) has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. Accomplish this by placing the reference decoupling
0.1
ceramic capacitor close to, and ideally right up against, the REF
04301-024

and GND pins and by connecting these pins with wide, low
0.01 impedance traces.
10 100 1k 10k 100k
SAMPLING RATE (SPS) Finally, decouple the power supply, VDD, of the AD7683 with a
Figure 25. Operating Current vs. Sampling Rate ceramic capacitor, typically 100 nF, placed close to the AD7683.
DIGITAL INTERFACE Connect it using short and large traces to provide low impedance
The AD7683 is compatible with SPI®, QSPI™, digital hosts, paths and reduce the effect of glitches on the power supply lines.
MICROWIRE™, and DSPs (for example, Blackfin® ADSP-BF531, EVALUATING THE AD7683 PERFORMANCE
ADSP-BF532, ADSP-BF533, or the ADSP-2191M). The connection
Other recommended layouts for the AD7683 are outlined in the
diagram is shown in Figure 26 and the corresponding timing is
evaluation board for the AD7683 (EVAL-AD7683CBZ). The
given in Figure 2.
evaluation board package includes a fully assembled and tested
A falling edge on CS initiates a conversion and the data transfer. evaluation board, documentation, and software for controlling
After the fifth DCLOCK falling edge, DOUT is enabled and forced the board from a PC via the EVAL-CONTROL BRD3Z.
low. The data bits are then clocked, MSB first, by subsequent

Rev. B | Page 14 of 16
Data Sheet AD7683

OUTLINE DIMENSIONS
3.20
3.00
2.80

8 5 5.15
3.20 4.90
3.00 4.65
2.80 1
4

PIN 1
IDENTIFIER

0.65 BSC

0.95 15° MAX

0.85 1.10 MAX
0.75
0.80
0.15 6° 0.23
0.40 0.55
0.05 0° 0.09 0.40
COPLANARITY 0.25

10-07-2009-B
0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 27. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)
Dimensions Shown in millimeters

3.10 0.35
3.00 SQ 0.30 0.65 BSC
2.90 0.25
5 8

PIN 1 INDEX EXPOSED 1.74

AREA PAD
1.64
0.50 1.49
0.40
0.30
4 1 0.20 MIN
TOP VIEW BOTTOM VIEW PIN 1
INDICATOR
0.80 MAX 2.48 (R 0.2)
0.80 0.55 NOM 2.38
0.75 0.05 MAX 2.23
0.70 0.02 NOM
FOR PROPER CONNECTION OF
SEATING THE EXPOSED PAD, REFER TO
02-05-2013-C

PLANE 0.20 REF THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

Figure 28. 8-Terminal Quad Flat No Lead Package (QFN) [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-3)
Dimensions Shown in millimeters

Rev. B | Page 15 of 16
AD7683 Data Sheet
ORDERING GUIDE
Integral Package Ordering
Model1 Nonlinearity Temperature Range Package Description2 Option Branding Quantity
AD7683ACPZRL7 ±6 LSB max –40°C to +85°C 8-Lead QFN [LFCSP_WD] CP-8-3 C4G Reel, 1,500
AD7683ARMZ ±6 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C4G Tube, 50
AD7683ARMZRL7 ±6 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C4G Reel, 1,000
AD7683BCPZRL7 ±3 LSB max –40°C to +85°C 8-Lead QFN [LFCSP_WD] CP-8-3 C38 Reel, 1,500
AD7683BRMZ ±3 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C38 Tube, 50
AD7683BRMZRL7 ±3 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C38 Reel, 1,000
EVAL-AD7683SDZ Evaluation Board
EVAL-CONTROL BRD3Z Controller Board
1
Z = RoHS Compliant Part.
2
The EVAL CONTROL BRD3Z board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04301-0-2/16(B)

Rev. B | Page 16 of 16