Gateway Classes
COA by PRAGYARAJ VANSHI MA’AM
B.TECH
COA– Important Questions
𝐔𝐧𝐢𝐭 − 𝟎𝟏
Q.1- What is bus arbitration? Why bus arbitration is needed? Explain different types of bus arbitration with
their advantages and disadvantages
Q.2- What are different addressing modes? An Instruction is Stored at location 200 with its address field at
location 201. The address field has the value 400. A processor register R1 contain the value 200. Find out the
effective address if the addressing mode of the instruction is: - 1) Immediate 2) Direct 3) Register indirect 4)
Relative 5) Index with R1 as the Index Register
Q.3- What is bus transfer? Explain
(i) bus transfer through multiplexer with suitable diagram/common bus system using multiplexer
(ii)bus transfer through three state buffer and decoder instead of multiplexer.
Q.4-Diffrence between-
(i) memory stack and register stack
(ii) memory read and memory write
(iii) data bus, address bus, control bus
Q.5- A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed
with multiplexers. a. How many selection inputs are there in each multiplexer? b. What sizes of multiplexers
are needed? c. How many multiplexers are there in the bus?
𝐔𝐧𝐢𝐭– 𝟎𝟐
Q.1- Show the multiplication process using Booth’s Algorithm when the following numbers are multiplied:
(i) (-13) by (+8)
(ii) (-7) by (-3)
Q.2-Explain Restoring and non-restoring division algorithm with example.
Q.3- Explain half adder, full adder and ripple Carry adder
Q.4- explain4 bit /3bit carry look adder with proper diagram and equation
Q.5- Explain 4-bit array multiplier.
Q.6- Represent the following decimal numbers in IEEE standard format in a single and double precision
method i. (65.175)10 ii. (-307.1875)10
Gateway Classes
COA by PRAGYARAJ VANSHI MA’AM
𝐔𝐧𝐢𝐭 − 𝟎𝟑
Q.1- What is RISC and how it differs with CISC?
Q.2- What are differences between hardwired and microprogrammed control unit?
Q.3- Differentiate between Horizontal & Vertical microprogramming
Q.4- Explain the pipelining in detail with neat and clean diagram and explain different type of pipelihne
Q.5- Explain the following term. i)Micro operation ii) Microinstruction iii) Microprogram iv) Micro Code.
vi) pipelining and Parallelism vii) linear and non-linear pipeline
Q.6- Explain different types of micro operations.
Q.7- Explain Microinstruction format and microprogrammed control unit.
Q.8- Explain Microprogram sequencer.
Q.9- What is instruction format. Explain different types of instruction format
Numerical Problems:
N.1- A vertical microprogrammed control unit support 512 instructions. The system is using 8 conditional
flag and contain 31 control, signals. Each instruction on an average has 1 micro operations. Calculate the
approximate size of memory in bytes.
N.2- Evaluate the arithmetic statement X = (A+B)*(C+D) using general register computer with Zero Address
,One Address, Two Address and Three Address instruction formats.
N.3- A non-pipelined system takes 50 ns to process a task. The same task can be processed in a six-segment
pipeline with a clock cycle of 10 ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the
maximum speedup that can be achieved?
𝐔𝐧𝐢𝐭 − 𝟎𝟒
Q.1- A virtual memory system has an address space of 8K words, a memory space of 4K words and page and
block sizes of 1K words. The following page reference changes occur during given time interval (only page
changes are listed. If the same page is referenced again it is not listed twice.) 4 2 0 1 2 6 1 4 0 1 0 2 3 5 7
Determine the four pages that are resident in main memory after each page reference change if the
replacement algorithm used is (a) FIFO (b) LRU.
Q.2- A two-way set associative cache memory uses blocks of four words. The cache can accommodate a total
of 2048 words from main memory. The main memory size is 128K X 32. a. Formulate all pertinent information
required to construct the cache memory. b. What is the size of cache memory?
Gateway Classes
COA by PRAGYARAJ VANSHI MA’AM
Q.3- What is memory hierarchy?
Q.4- What is cache mapping Explain different types of cache mapping techniques
Q.5- What is hit ratio and miss ratio and static and dynamic RAM and locality of reference.
Q.6 Give the structure of commercial 8Mx8 bz
𝐔𝐧𝐢𝐭 − 𝟎𝟓
Q.1-What is Asynchronous data transfer? Explain the modes of data transfer
Q.2- Give the block diagram of DMA controller? Why read and write lines in DMA controller is Bi-
directional
Q.3- Difference between-
(i) strobe and handshaking asynchronous data transfer modes.
(ii) processor and IOP
(iii) synchronous and asynchronous data transfer modes.
(iv) serial and parallel communication
(v) vectored and non-vectored interrupt
(vi) trap and exception
(vii) mask able and non-mask able interrupt
(Viii) I/O programmed controlled transfer and DMA transfer
Q.4- Explain the input output processor with suitable diagram along with CPU-IOP communication
