TC358768AXBG/TC358778XBG

CMOS Digital Integrated Circuit Silicon Monolithic

TC358768AXBG/TC358778XBG
Mobile Peripheral Devices
TC358768AXBG
Overview
Parallel Port to MIPI® DSISM (TC358768AXBG/TC358778XBG) is a
bridge device that converts RGB to DSI. All internal registers can
access through I2C or SPI.
P-VFBGA72-0404-0.40A3
Weight: 32mg (Typ.)

TC358778XBG

P-VFBGA80-0707-0.65-001
Weight: 68 mg (Typ.)

Features
● DSI-TX Interface - Writing to DCS registers will trigger DCS
 MIPI DSI compliant (Version 1.02.00– June Command transmits over DSI
28, 2010) ● GPIO signals
- Support DSI Video Mode data transfer  2 GPIO signals
- DCSSM Command for panel register - Two GPIO signals can be configured as
access SPI signals (SPI_SS and SPI_MISO)
 Supports up to 1 Gbps per data lane - Or One GPIO signal can be configured as
 Supports1, 2, 3 or 4 data lanes Interrupt output signal, INT.
 Supports video data formats
- RGB888/666/565 ● System
 Clock and power management support to
● RGB Interface achieve low power states.
 Supports data formats
- 24-bit data bus ● Power supply inputs
 RGB888/666/565 data formats  Core and MIPI D-PHYSM: 1.2V
 Up to 166 MHz input clock  I/O: 1.8V – 3.3V
 Support VSYNC/HSYNC polarity option ● Typical Power Consumption
(default LOW)  WXGA @60fps: Pixel Clk: 74.25 MHz,
 Support DE polarity option (default High) DSIClk: 312 MHz  66.7 mW
● I2C/SPI Slave Interface (Option to select either  1080P @60fps: Pixel Clk: 148.5 MHz,
I2C or SPI interface) DSIClk: 471 MHz  91.4 mW
 I2C Interface (when CS = L)  Power Down Condition is achieved by
- Support for normal (100 kHz), fast mode turning off clock sources: PClk and RefClk.
(400 kHz) and Special mode (1 MHz)
- Configure all
TC358768AXBG/TC358778XBG internal
registers
- Writing to DCS registers will trigger DCS
Command transmits over DSI
 SPI interface (when CS = H)
- SPI interface support for up to 25 MHz
operation.
- Configure all
TC358768AXBG/TC358778XBG internal
registers

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Table of contents
REFERENCES ..................................................................................................................................................... 4
1. Overview .......................................................................................................................................................... 5
2. Features ........................................................................................................................................................... 6
3. External Pins .................................................................................................................................................... 8
3.1. TC358768AXBG pinout description .......................................................................................................... 8
3.2. TC358768AXBG BGA72 Pin Count Summary ......................................................................................... 9
3.3. TC358778XBG pinout description........................................................................................................... 10
3.4. TC358778XBG BGA80 Pin Count Summary .......................................................................................... 11
3.5. TC358768AXBG Pin Layout.................................................................................................................... 12
3.6. TC358778XBG Pin Layout ...................................................................................................................... 13
4. Package ......................................................................................................................................................... 14
4.1. TC358768AXBG Package....................................................................................................................... 14
4.2. TC358778XBG Package ......................................................................................................................... 15
5. Electrical Characteristics ................................................................................................................................ 16
5.1. Absolute Maximum Ratings..................................................................................................................... 16
5.2. Operating Condition................................................................................................................................. 16
5.3. DC Electrical Specification ...................................................................................................................... 17
6. Revision History ............................................................................................................................................. 18
RESTRICTIONS ON PRODUCT USE............................................................................................................... 19

List of Figures
Figure 1.1 System Overview with TC358768AXBG/TC358778XBGin RGB to DSI-TX ............................ 5
Figure 3.1 TC358768AXBG 72-Pin Layout (Top View) ........................................................................... 12
Figure 3.2 TC358778XBG 80-Pin Layout (Top View).............................................................................. 13
Figure 4.1 TC358768AXBG P-VFBGA72-0404-0.40A3 package ........................................................... 14
Figure 4.2 TC358778XBG P-VFBGA80-0707-0.65-001 package ........................................................... 15

List of Tables
Table 3.1 TC358768AXBG Functional Signal List ..................................................................................... 8
Table 3.2 TC358768AXBG BGA 72 Pin Count Summary ......................................................................... 9
Table 3.3 TC358778XBG Functional Signal List ..................................................................................... 10
Table 3.4 TC358778XBG BGA 80 Pin Count Summary ......................................................................... 11
Table 4.1 TC358768AXBG P-VFBGA72-0404-0.40A3 Mechanical Dimension...................................... 14
Table 4.2 TC358778XBG P-VFBGA80-0707-0.65-001 Mechanical Dimension ..................................... 15
Table 6.1 Revision History ....................................................................................................................... 18

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1 NOTICE OF DISCLAIMER
2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled
3 by any of the authors or developers of this material or MIPI. The material contained herein is provided on
4 an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS
5 AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all
6 other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if
7 any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of
8 accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of
9 negligence.

10 All materials contained herein are protected by copyright laws, and may not be reproduced, republished,
11 distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express
12 prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related
13 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and
14 cannot be used without its express prior written permission.

15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET

16 POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD
17 TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY
18 AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR
19 MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE
20 GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER
22 CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR
23 ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,
24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
25 DAMAGES.

26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is
27 further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the
28 contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;
29 and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance
30 with the contents of this Document. The use or implementation of the contents of this Document may
31 involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,
32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI
33 does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any
34 IPR or claims of IPR as respects the contents of this Document or otherwise.

35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:

36 MIPI Alliance, Inc.

37 c/o IEEE-ISTO
38 445 Hoes Lane
39 Piscataway, NJ 08854
40 Attn: Board Secretary

This Notice of Disclaimer applies to all DSI input and processing paths related descriptions throughout this
document.

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REFERENCES

1. MIPI® DSISM, "mipi_DSI_specification_v01-02-00, June 28, 2010"

2. MIPI® DCSSM “DRAFT mipi_DCS_specification_v01-02-00_r0-02, December 2008”
3. MIPI® D-PHYSM, “mipi_D-PHY_specification_v01-00-00, May 14, 2009"
4. I2C bus specification, version 2.1, January 2000, Philips Semiconductor

● MIPI® is a registered service mark of MIPI Alliance, Inc. DCSSM, DSISM and D-PHYSM are service
marks of MIPI Alliance, Inc.
● Other company names, product names, and service names may be trademarks of their respective
companies.

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1. Overview
The Parallel Port to MIPI DSI (TC358768AXBG/TC358778XBG) is a bridge device that converts RGB to
DSI. All internal registers can access through I2C or SPI.

TC358768AXBG
TC358778XBG DSI
(1-4 Data Lanes)

CP/CN
(16/18/24-bit) RGB
(RGB) D0P/D0N
DSI
HOST To D1P/D1N
(VSYNC/HSYNC/DE) D2P/D2N Panel
DSI
D3P/D3N

I2C/SPI
Converter

Figure 1.1 System Overview with TC358768AXBG/TC358778XBGin RGB to DSI-TX

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2. Features
Below are the main features supported by TC358768AXBG/TC358778XBG.
● DSI-TX Interface
 MIPI DSI compliant (Version 1.02.00– June 28, 2010)
- Support DSI Video Mode data transfer
- DCS Command for panel register access
 Supports up to 1 Gbps per data lane
 Supports1, 2, 3 or 4 data lanes
 Supports video data formats
- RGB888/666/565
● RGB Interface
 Supports data formats
- 24-bit data bus
 RGB888/666/565 data formats
 Up to 166 MHz input clock
 Support VSYNC/HSYNC polarity option (default LOW)
 Support DE polarity option (default High)
● I2C/SPI Slave Interface (Option to select either I2C or SPI interface)
 I2C Interface (when CS = L)
- Support for normal (100 kHz), fast mode (400 kHz) and Special mode (1 MHz)
- Configure all TC358768AXBG/TC358778XBG internal registers
- Writing to DCS registers will trigger DCS Command transmits over DSI
 SPI interface (when CS = H)
- SPI interface support for up to 25 MHz operation.
- Configure all TC358768AXBG/TC358778XBG internal registers
- Writing to DCS registers will trigger DCS Command transmits over DSI
● GPIO signals
 2 GPIO signals
- Two GPIO signals can be configured as SPI signals (SPI_SS and SPI_MISO)
- Or One GPIO signal can be configured as Interrupt output signal, INT.
● System
 Clock and power management support to achieve low power states.
● Power supply inputs
 Core and MIPI D-PHY: 1.2 V
 I/O: 1.8 V to 3.3 V

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● Typical Power Consumption

 WXGA @60fps: Pixel Clk: 74.25 MHz, DSIClk: 312 MHz  66.7 mW
 1080P @60fps: Pixel Clk: 148.5 MHz, DSIClk: 471 MHz  91.4 mW

VDDC VDDIO VDDMIPI Total

1.2 V 3.3 V 1.2 V Power

42.8 mA 0.4 mA 32.3 mA

1080P Video
51.36 mW 1.32 mW 38.76 mW 91.44 mW
34.71 mA 0.167 mA 20.36 mA
WXGA Video
41.652 mW 0.551 mW 24.432 mW 66.64 mW

Power Down 0. 074 mA 0. 025 mA 0. 004 mA

w/o PCLK, RefClk 0. 089 mW 0. 0825 mW 0. 0048 mW 176.1 µW

 Power Down Condition is achieved by turning off clock sources: PClk and RefClk.

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3. External Pins
3.1. TC358768AXBG pinout description
TC358768AXBG resides in BGA72 pin packages. The following table gives the signals of
TC358768AXBG and their function.

Table 3.1 TC358768AXBG Functional Signal List

Group Pin Name I/O Type Function Note

RESX I Sch System reset input, active low -
REFCLK I N Reference clock input (6MHz - 40MHz) -
System: Mode Select
Reset & MSEL I N 1'b0: Test mode -
Clock 1'b1: Normal mode
(4) Configuration Select
CS I N - When CS = L, enable I2C interface -
- When CS = H, enable SPI interface
MIPI_CP - PHY MIPI-DSI clock positive -
MIPI_CN - PHY MIPI-DSI clock negative -
MIPI_D0P - PHY MIPI-DSI Data 0 positive -
MIPI_D0N - PHY MIPI-DSI Data 0 negative -
MIPI-DSI MIPI_D1P - PHY MIPI-DSI Data 1 positive -
(10) MIPI_D1N - PHY MIPI-DSI Data 1 negative -
MIPI_D2P - PHY MIPI-DSI Data 2 positive -
MIPI_D2N - PHY MIPI-DSI Data 2 negative -
MIPI_D3P - PHY MIPI-DSI Data 3 positive -
MIPI_D3N - PHY MIPI-DSI Data 3 negative -
I2C I2C_SCL OD Sch I2C serial clock or SPI_SCLK 4 mA
(2) I2C_SDA OD Sch I2C serial data or SPI_MOSI 4 mA
Parallel Port Input Data
PD[23:0] I N Note: PD[23:16] can be configure to be -
Parallel GPIO[10:3]
Port IF VSYNC I N Parallel port VSYNC signal -
(28) HSYNC I N Parallel port HSYNC signal -
DE I N Parallel Port DE signal -
PCLK I N Parallel Port Clock signal -
GPIO[2:1] signals
- (GPIO[1] option to become SPI_SSor
GPIO
GPIO[2:1] I/O N INT signal) 4 mA
(2)
- (GPIO[2] option to become SPI_MISO
signal)
VDDC (1.2 V) NA - VDD for Internal Core (3) -
VDDIO
POWER NA - VDDIO is for IO power supply (4) -
(1.8 V-3.3 V)
(9)
VDD_MIPI
NA - VDD for the MIPI (2) -
(1.2 V)
GROUND
VSS NA - Ground -
(17)

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3.2. TC358768AXBG BGA72 Pin Count Summary

Table 3.2 TC358768AXBG BGA 72 Pin Count Summary

Group Name Pin Count Note

SYSTEM 4 -
MIPI-DSI 10 -
I2C IF 2 -
GPIO 2 -
Parallel Port IF 28 -
POWER 9 IO, MIPI and Core Power
GROUND 17 -
TOTAL 72

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3.3. TC358778XBG pinout description

TC358778XBG resides in BGA80 pin packages. The following table gives the signals of TC358778XBG
and their function.

Table 3.3 TC358778XBG Functional Signal List

Group Pin Name I/O Type Function Note

RESX I Sch System reset input, active low -
REFCLK I N Reference clock input (6MHz - 40MHz) -
System: Mode Select
Reset & MSEL I N 1'b0: Test mode -
Clock 1'b1: Normal mode
(4)
Configuration Select
CS I N - When CS = L, enable I2C interface -
- When CS = H, enable SPI interface
MIPI_CP - PHY MIPI-DSI clock positive -
MIPI_CN - PHY MIPI-DSI clock negative -
MIPI_D0P - PHY MIPI-DSI Data 0 positive -
MIPI_D0N - PHY MIPI-DSI Data 0 negative -
MIPI-DSI MIPI_D1P - PHY MIPI-DSI Data 1 positive -
(10) MIPI_D1N - PHY MIPI-DSI Data 1 negative -
MIPI_D2P - PHY MIPI-DSI Data 2 positive -
MIPI_D2N - PHY MIPI-DSI Data 2 negative -
MIPI_D3P - PHY MIPI-DSI Data 3 positive -
MIPI_D3N - PHY MIPI-DSI Data 3 negative -
I2C IF I2C_SCL OD Sch I2C serial clock or SPI_SCLK 4 mA
(2) I2C_SDA OD Sch I2C serial data or SPI_MOSI 4 mA
Parallel Port Input Data
PD[23:0] I N Note: PD[23:16] can be configure to be -
GPIO[10:3]
Parallel
Port IF VSYNC I N Parallel port VSYNC signal -
(28) HSYNC I N Parallel port HSYNC signal -
DE I N Parallel Port DE signal -
PCLK I N Parallel Port Clock signal -
GPIO[2:1] signals
GPIO - (GPIO[1] option to become SPI_SSor INT
GPIO[2:1] I/O N 4 mA
(2) signal)
- (GPIO[2] option to become SPI_MISO signal)
VDDC (1.2V) NA - VDD for Internal Core (3) -
POWER VDDIO
NA - VDDIO is for IO power supply (4) -
(9) (1.8V - 3.3V)
VDD_MIPI (1.2V) NA - VDD for the MIPI (2) -
GROUND
VSS NA - Ground -
(25)

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3.4. TC358778XBG BGA80 Pin Count Summary

Table 3.4 TC358778XBG BGA 80 Pin Count Summary

Group Name Pin Count Note

SYSTEM 4 -
MIPI-DSI 10 -
I2C IF 2 -
GPIO 2 -
Parallel Port IF 28 -
POWER 9 IO, MIPI and Core Power
GROUND 25 -
TOTAL 80

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3.5. TC358768AXBG Pin Layout

A1 A2 A3 A4 A5 A6 A7 A8 A9

VSS PD17 PD19 PD21 PD23 GPIO2 I2C_SCL MSEL VSS

B1 B2 B3 B4 B5 B6 B7 B8 B9

VDDC PD16 PD18 PD20 PD22 GPIO1 I2C_SDA RESX VDDIO

C1 C2 C3 C4 C5 C6 C7 C8 C9

PD15 PD14 VSS VSS VSS VSS VDD_MIPI MIPI_D3P MIPI_D3N

D1 D2 D3 D7 D8 D9

PD13 PD12 VSS VSS MIPI_D2P MIPI_D2N

E1 E2 E3 E7 E8 E9

VSS VSS VDDC VDD_MIPI MIPI_CP MIPI_CN

F1 F2 F3 F7 F8 F9

VSS VSS VSS VSS MIPI_D1P MIPI_D1N

G1 G2 G3 G4 G5 G6 G7 G8 G9

PD11 PD10 VDDIO VSS VSS VDDIO VDDIO MIPI_D0P MIPI_D0N

H1 H2 H3 H4 H5 H6 H7 H8 H9

VDDC PD8 PD6 PD4 PD2 PD0 PCLK DE CS

J1 J2 J3 J4 J5 J6 J7 J8 J9

VSS PD9 PD7 PD5 PD3 PD1 REFCLK VSYNC HSYNC

Figure 3.1 TC358768AXBG 72-Pin Layout (Top View)

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3.6. TC358778XBG Pin Layout

Figure 3.2 TC358778XBG 80-Pin Layout (Top View)

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4. Package
4.1. TC358768AXBG Package
The packages for TC358768AXBG is described in the figure below.

Weight: 32 mg (Typ.)

Figure 4.1 TC358768AXBG P-VFBGA72-0404-0.40A3 package

Table 4.1 TC358768AXBG P-VFBGA72-0404-0.40A3 Mechanical Dimension

Dimension Min Typ. Max
Solder ball pitch - 0.4 mm -
Solder ball height 0.15 mm 0.2 mm 0.25 mm
Package dimension - 4.5 × 4.5 mm2 -
Package height - - 1.0 mm

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4.2. TC358778XBG Package

The package for TC358778XBG is described in the figure below.

Weight: 68 mg (Typ.)

Figure 4.2 TC358778XBG P-VFBGA80-0707-0.65-001 package

Table 4.2 TC358778XBG P-VFBGA80-0707-0.65-001 Mechanical Dimension

Dimension Min Typ. Max
Solder ball pitch - 0.65 mm -
Solder ball height 0.20 mm 0.25 mm 0.30 mm
Package dimension - 7.0 × 7.0 mm2 -
Package height - - 1.0 mm

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5. Electrical Characteristics
5.1. Absolute Maximum Ratings

VSS = 0V reference
Parameter Symbol Rating Unit
Supply voltage
VDDIO -0.3 to +3.9 V
(1.8V - Digital IO)
Supply voltage
VDDC -0.3 to +1.8 V
(1.2V – Digital Core)
Supply voltage
VDD_MIPI -0.3 to +1.8 V
(1.2V – MIPI PHY)
Input voltage
VIN_DSI -0.3 to VDD_MIPI+0.3 V
(DSI IO)
Output voltage
VOUT_DSI -0.3 to VDD_MIPI+0.3 V
(DSI IO)
Input voltage
VIN_IO -0.3 to VDDIO+0.3 V
(Digital IO)
Output voltage
VOUT_IO -0.3 to VDDIO+0.3 V
(Digital IO)
Junction temperature Tj 125 oC

Storage temperature Tstg -40 to +125 oC

5.2. Operating Condition

VSS = 0 V reference
Parameter Symbol Min Typ. Max Unit

Supply voltage (1.8V – Digital IO) VDDIO 1.65 1.8 1.95 V

Supply voltage (3.3V – Digital IO) VDDIO 3.0 3.3 3.6 V
Supply voltage (1.2V – Digital Core) VDDC 1.1 1.2 1.3 V
Supply voltage (1.2V – MIPI PHY) VDD_MIPI 1.1 1.2 1.3 V
Operating temperature (ambient
Ta -30 +25 +85 oC
temperature with voltage applied)
Supply Noise Voltage VSN - - 100 mVpp

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5.3. DC Electrical Specification

Parameter Symbol Min Typ. Max Unit

Input voltage, High level input Note1 VIH 0.7 VDDIO - VDDIO V
Input voltage, Low level input Note1 VIL 0 - 0.3 VDDIO V
Input voltage High level
VIHS 0.7 VDDIO - VDDIO V
CMOS Schmitt Trigger Note1, Note2
Input voltage Low level
VILS 0 - 0.3 VDDIO V
CMOS Schmitt Trigger Note1, Note2
Output voltage High level Note1, Note2
VOH 0.8 VDDIO - VDDIO V
(Condition: IOH = -0.4 mA)
Output voltage Low level Note1, Note2
VOL 0 - 0.2 VDDIO V
(Condition: IOL = 2 mA)
Input leak current, High level (Normal IO
or Pull-up IO) IILH1 Note3 -10 - 10 µA
(Condition: VIN = +VDDIO, VDDIO = 3.6 V)
Input leak current, High level (Pull-down
IO) IILH2 Note3 - - 100 µA
(Condition: VIN = +VDDIO, VDDIO = 3.6 V)
Input leak current, Low level (Normal IO
or Pull-down IO) IILL1 Note4 -10 - 10 µA
(Condition: VIN = 0 V, VDDIO = 3.6 V)
Input leak current, Low level (Pull-up IO)
IILL2 Note4 - - 200 µA
(Condition: VIN = 0 V, VDDIO = 3.6 V)

Note 1: Each power source is operating within operating condition.

Note 2: Current output value is specified to each IO buffer individually. Output voltage changes with
output current value.
Note 3: Normal pin or Pull-up IO pin applied VDDIO supply voltage to Vin (input voltage)
Note 4: Normal pin or Pull-down IO pin applied VSSIO (0V) to Vin (input voltage)

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6. Revision History
Table 6.1 Revision History

Revision Date Description

1.11 2014-05-28 Newly released
・Package’s weight is rounding up digits after the decimal point to
1.12 2016-04-01 form an integer.
・Modified TC358768AXBG’s package code.
Changed header, footer and the last page.
1.6 2017-10-18
Changed corporate name.
Modified descriptions of trademark and service mark.
Corrected typos.
1.65 2019-02-08 Corrected weight of TC358778XBG in cover page and chapter 4.
Revised the last page “RESTRICTIONS ON PRODUCT USE” and
added URL.

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RESTRICTIONS ON PRODUCT USE

Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”.
Hardware, software and systems described in this document are collectively referred to as “Product”.
• TOSHIBA reserves the right to make changes to the information in this document and related Product without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH
MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without
limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical
equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to
control combustions or explosions, safety devices, elevators and escalators, and devices related to power plant. IF YOU USE
PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your
TOSHIBA sales representative or contact us via our website.
• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the
U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited
except in compliance with all applicable export laws and regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of
Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled
substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES
OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.

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