Inputs:

1.What are the inputs required for pd, What is the content present in each and every input file?

2. sanity checks after loading inputs?

Ans: check_design, check_timing, check_library ( go through indetail in google)

Floorplan:
1. What are the guidelines followed to place macros?
 Based on flyline connectivity
 We will check IO ports to macro flylines and place macros near to ports which has more
flyline connectivity.
 Need to maintain Macro-macro horizontal and vertical spacing and also macro edges to core
edge.
 Creating halos across macros to avoid cell density near macro pins.
 Creating proper partial blockages in macro spacing to avoid congestion issues in macro
channels.
 Align macro edges properly and fix all the macros.
 Macro pins mainly we will place towards core area.

2. What are physical cells?

3. Why we will place end cap cells? Why we will place tap cells?

4. What is latchup issue?

5. On what basis we will decide block size and shape?

Ans: Based on aspect ratio and standard cell utilization we will get block size and shape.
Ex: aspect ratio 1 ( square)
Initial utilization ( 65% to 70%)

6. What are the checks we will do after floorplan?

 Routing congestion ( Basically tool checks horizontal metals overflow and vertical metals
overflow )  If value is greater than 1% then we have routing congestion it need to be
below 1% ( 0.5 or 0.4 % )
 Check_legality of macros
 Check_pin_alignment( to check whether ports are properly aligned with tracks or not)
 Base drc ( poly continuity , Diffusion continuity, Nwell continuity) If physical cells are not
inserted properly we will face base drc violations.
 7. Can we place macros at centre of core?

8. Command to get total number of macros in design, How to select macros and how to get macros
count?

9. Command to get total number of ports in design?

POWERPLAN:

1. What are the commands in powerplan?

 Set_pg_strategies ( in this command we will specify what are the metal layers we are
planning to create stripes & width of that metal layer & spacing between those stripes)
 Compile_pg( The main command which will create all stripes)

2. What is static IR DROP vs Dynamic IR DROP?

 Static IR DROP we will check after powerplan using Redhawk tool, It is an average
voltage drop in design,
Fixes:
We will try to increase power stripes in design by changing power strip width and
spacing between power stripes.

 Dynamic IR drop we will check after route, It will report all the cells which are having IR
DROP
Fixes:
1.Downsize cells if setup margin is available ( size_cell)
2.Adding power stripes on top of cells
3. Moving cells to other location where we have less congestion. ( move_objects)

3. What are the checks after power plan?

 Check_pg_drc
 Check_pg_connectivity
PLACEMENT:
1. What are the steps in placement?
Ans: place_opt is command which perform placement of cells.

Steps:
 Coarse placement ( rough placement of all cells without any legalization)
 Logic optimization ( tool will try to do logic optimization inorder to fix setup timing)
 High fanout net synthesis ( Based on fanout limit tool will try to do splitting and cloning )
 Scan chain reordering. (Scan chain connections of flops to be reordered to its nearby flops in
placement stage)  If scan chain reordering is not happen properly will face routing
congestion issues
 Legalization of all cells.  cells overlapped with other cells which results in drc.

2. Checks after placement stage?

 Setup timing. ( report_timing )
 Congestion. ( report_congestion or we also check in gui by using view map cell
density)
 Check_legality.

3. What are different path groups in our design?

4. What are the criticalities you faced in place stage?

SETUP TIMING:

 We have setup timing violations below are the few category types of violations we faced
and by using below techniques we fixed those violations.

LEVELS OF LOGIC :
 Levels of logic is more in datapath ( combinational cells are more in data path)  If data
path cells are more we will request RTL team to reduce levels of logic in data path

BOUNDS:
 For few of the paths few hierarchy cells are sitting very far due to that we are getting
more delays in data path, Inorder to fix this issue we created bounds and tell the tool to
place those cells near to each other.
Ex: create_bound ( go through man page)
Create_bound -region { } -cell { need to specify cells to place in this region}

GROUP PATH WEIGHTAGE:

 If any paths are having high wns we try by giving more weightage to those paths so tool
will consider those paths as high priority and try to fix those paths.
 Ex: group_path -from { start_point cell_name} -to { end_point cell_name} -weightage
100 ( go through man page)

PLACEMENT ATTRACTION:
 In macro to register path group, register is sitting very far from macro due to that we
have more setup WNS, Inorder to fix this violations we created placement attraction for
those registers which are sitting very far.
Ex: create_placement_attraction -region { near macro region } -cells { registers to get
attract} ( go through man page)

CONGESTION:
 Global congestion : global congestion is congestion across the core area, Inorder to
avoid this issue we will set max_density limits in our design.

 Local congestion : local congestion is congestion in any particular area in core, Inorder
to avoid this issue we will use blockage techniques.
Ex: soft blockage, Hard blockage, partial blockage
Create_placement_blockage ( go through man page).

CTS:
Distributing clock from main clock source to each and every registers clock pin in our design.

Cts specifications: we will set specifications before starting cts to build clock tree effectively with
minimal skew and latencies.

 Go through skew, latency, local skew, global skew, jitter, uncertainty definitions in google.

1.target skew : 50ps

2. target latency : 250ps

3. set_dont_use { cells list}  we will set cells list which don’t want to use in clock nets by using this
command.

4. set ndr rules : set_routing_rules ( we will set double width and double spacing for all the clock nets
which helps to avoid signal integrity issues in clock nets)

Go through definitions of below 2 topics.

Signal integrity:

1. Electromigration  double width in clock nets helps to avoid electromigration issues in clock
nets

Other fixes:

 Via ladder technique( divides current and reducing current density in metal)
 Metal jogging( Metal jogging in higher metal layers)

2. Crosstalk  double spacing helps to avoid crosstalk violations in clock nets.

1.crosstalk noise
2.crosstalk delay
- Go through definitions

Other fixes:

 Upsize driver
 Add_buffer_on_route(breaking victim net)
 Shielding ( shielding clock nets with VSS)

 Will crosstalk affect setup and hold timing? If yes how??

3. Did you face any latency issues in cts?  yes faced macro clock pins are having high latency 
In order to avoid this issue for all macro clock pins we early clock skew with 50ps by using below
command.

Ex: set_clock_balancing_point { specify macro clock pins which need to early} -early 50

Previously latency is high for those macro pins (~300ps) after earlying with 50ps it came back to
( ~250ps)

4. What happens if latency is high in ur design??

Ans: If latency is high tool adds more clock buffers in ur design which will consume more area in
ur design and power dissipation also more in ur design so our main goal is to reduce latency.

5. Suppose if you have 2 design one with high latency & less skew and other design is opposite
which design is good??
Ans: We prefer design with less latency( reason specified in 4th question)

6. Main goals after cts??  latency and skew need to be minimal and those values need to meet
with targets which we specified.
7. Checks after cts:
Ans: 1. Latency 2. Skew 3. Setup 4. Hold 5. Clock drvs
OPTCTS:
After cts tool will perform optcts stage in this stage tool will try to fix setup and hold timing
automatically based on app option setting which we specified.

ROUTE:
In Route stage tool will give connections to all standard cell pins based on track availability in ur design
without affecting drcs.

1. Global route ( rough routing without considering any drcs)

2. Track assignment ( tool will check track availability and assign tracks without any drcs)
3. Detail routing ( tool will perform detail routing and give proper connections to all cells)

Checks after routing:

1. Setup and hold timing

2. Drcs and shorts.

1. If timing is good in cts and not good in route what is the reason?
Ans: Some times if there are any long nets, If those nets are routed in lower layers then those
nets will contribute more delays and will affect setup timing in ur design.

Inorder to avoid above issue we will set routing rules on those long nets and tell the tool to
route those nets in higher layers.

PROJECT SPECIFICATIONS:
1. Operating frequency : tell frequency specified in resume.(units mega hertz or giga hertz)
 2. Time period : 1/frequency is ur time period ( units pico seconds or nano seconds)
3. Block dimensions : tell some random width height 350x1400(WxH) sq um ( units sq microns)
4. Clocks : 5 clocks in my block
5. Instance count : 1 Million or 800k instance count
6. Scenarios : Total 10 scenarios
Setup : SSG0P6v-40C (PVT  Process – SSG ( slow ) , Voltage – 0.6v, Temperature : -40C)
TT0P9v  (T Typical)
TT0p65v
TT0p6v
Hold: FF1P05vRcworst ( F Fast)
FF1P05vRcbest
Similarly we can tell 125C temperature to other scenarios)

Introduction to ur lead or manager :

This is Vicky, I have 4.5 years of experience in physical design, I worked on block level ownership from
netlist to GDSII and also worked on signoff checks like physical verification and static timing analysis,
Upto now I worked on 3 projects with this client, I have good exposure on floorplan placement cts and
route, Upto now I worked on different technologies like 10nanometer, 7nm ( tell technologies which
specified in resume), I worked on synopsys tools like icc2_shell and prime_time, I have good exposure in
scripting languages like tcl. ( 2 years experience guys don’t tell about having experience in physical
verification and static timing analysis mainly tell I worked on PNR).

Some times they can ask some random questions like manager name project name team name tell some
random names.

Project name: DCG group.

Block name : par_gbe

Physical Verification:
Shorts & Opens:

Fixed shorts where two different signals with similar metals are getting interacted, We draw nets in
different tracks.

DRCS:

1.Metal spacing: Spacing between two metals is not following properly, We need to provide proper
space between those metals.

2.Min length: Metal need to follow min length which specified in drc rule deck file, We need to increase
length of that metal

3.Min density: In specific region metals of that particular layer is very less, We need to add more metals
in that area to increase metal density.

4. Antenna Violations: Check about definition in google.

Fix:

1. Adding Diode.
2. Metal jogging.

Static timing analysis (Prime_time):

We will generate ecos in prime time for timing and Drv fixes.

SETUP FIXES:

1.vt swap
2.up size
3.add_buffer_on_route if transition is high due to high net length
4. Manually route in higher layer is there are any long nets and those are routing in lower layers

HOLD FIXES:
1.Insert buffer by checking setup margin
2.down size

DRV FIXES:

1. add_buffer_on_route by checking net length

2. Vt swap
3. Up size

EMIR FIXES:
EM FIXES:
1. Via ladder --> drawing parallel metals to divide current upto M5 layers
2. Metal jogging

IR FIXES:
1.Adding stripes on cells
2. Downsize cells
3. Move_objects

Cloning:
1. Downsize original cell --> D16 -- > D8
2.creating new clone cell
3.connecting cp pin of clone cell to driver pin of original cell
4.getting fanout of original cell and divide it by 2 and connect half of load to clone cell z pin