IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO.

2, APRIL 2007 1235

Real-Time Digital Hardware Simulation of

Power Electronics and Drives
Gustavo G. Parma, Member, IEEE, and Venkata Dinavahi, Member, IEEE

Abstract—This paper presents a digital hardware realization of while providing immunity to damage to the actual equipment
a real-time simulator for a complete induction machine drive using due to any malfunction of the controller. However, currently
a field-programmable gate array (FPGA) as the computational available real-time simulators still suffer from modeling inac-
engine. The simulator was developed using Very High Speed Inte-
grated Circuit Hardware Description Language (VHDL), making curacies and limited computational bandwidth. The modeling
it flexible and portable. A novel device-characteristic based model of the power converter is a particular challenge due to the

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suitable for FPGA implementation has been proposed for the demands its high frequency operation places on the accuracy
2-level 6-pulse IGBT-based voltage-source converter (VSC). The and precision of accounting the gating signals coming from the
VSC model is computed at a fixed time-step of 12.5 ns allowing digital controller. This has prompted several correction algo-
a highly detailed and precise accounting of gating signals. The
simulator also models a squirrel cage induction machine, a direct rithms [4]–[7], both offline and real-time, to be proposed using
field-oriented control system, a space-vector pulse-width modula- techniques such as interpolation/extrapolation and variable
tion scheme (SVPWM) and a measurement system. A multirate simulation step-size.
simulation of the system shows the slow (machine) as well as the Power-electronic devices are often modeled in time-domain
fast (VSC and control) dynamic components. Real time simulation

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simulation programs mainly using one of the following three
results under steady-state and transient conditions demonstrate
modeling accuracy and efficiency. behavioral [8] models: 1) ideal model, 2) switching function
model, and 3) averaged model. The ideal model represents
Index Terms—Field-programmable gate arrays, induction
each switch as a two-valued resistor for its on and off states. A
motor drives, pulse-width-modulated power converters, real-time
change of switch status, therefore, results in a change of circuit
systems.
O topology which, in turn, requires the modification of the system
matrix—a computationally intensive procedure especially at
I. INTRODUCTION high switching frequencies. For real-time simulation, the pre-
ferred approach is to precompute and store all possible matrix
permutations for a converter with switches, trading
EAL-TIME digital simulators can play a vital role in
R higher memory requirements for computational gains. The
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the design and development of large industrial ac drives
[1]–[3]. The two main components of a modern variable-speed switching function model circumvents this precomputation and
ac drive are the power stage and the controller stage. The power storage requirement by representing the switches as controlled
stage includes an insulated-gate bipolar transistor (IGBT)-based voltage and current sources. This model is suitable for high-fre-
quency operation, and the switching functions can be usually
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voltage-source converter (VSC) and the induction machine,

while the controller stage includes the digital controller, and a obtained by directly inspecting the converter circuit; however,
high-frequency pulsewidht-modulated (PWM) gating pattern the limitation of this model is that it does not accurately rep-
generator. Before prototyping, the controller stage is usually resent the rectifier action of the converter when the load is
subjected to several cycles of testing and re-design in an expen- regenerative. The main drawback of the averaged model is that
sive facility containing the power converter, motor-generator it only shows the low-frequency components of the switching
sets, sensors, switchgear, and other test equipment. A real-time functions ignoring all the high-frequency components. While
digital simulator that can model the power stage accurately this is not a concern for controller design, it causes a loss of
realism for the real-time simulator.
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and efficiently, provides an alternate means for testing the

In this paper, we propose a detailed device-characteristic
controller in a hardware-in-the-loop (HIL) configuration. This
approach has the advantage of substantially reducing cost, based model for the VSC suitable for digital hardware realiza-
human resources, power consumption, and physical space, tion on a field-programmable gate array (FPGA). The converter
model is computed at a fixed time-step, albeit, at an extremely
small step-size (of the order of a few nanoseconds). The ad-
vantages of this approach include: 1) freedom from reliance
Manuscript received January 10, 2006; revised July 12, 2006. This work was
supported in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível on complicated correction algorithms, 2) detailed represen-
Superior (CAPES), Brazil, and in part by the Natural Science and Engineering tation of the device switching characteristics, and 3) ability
Research Council of Canada (NSERC). Paper no. TPWRD-00749–2005. to interface the model to a large-scale real-time simulator,
G. G. Parma is with the Department of Electronics, Federal University of
Minas Gerais, Belo Horizonte CEP 3009-210, Brazil (e-mail: parma@cpdee. such as a PC-cluster [9], modeling a larger and more complex
ufmg.br). host power system in which the power electronic converter
V. Dinavahi is with the Department of Electrical and Computer Engineering, is embedded. Potential applications of this approach include
University of Alberta, Edmonton, AB T6G 2V4, Canada (e-mail: dinavahi@ece.
ualberta.ca). modular FPGA-based simulators with a library of models for
Digital Object Identifier 10.1109/TPWRD.2007.893620 multipulse and multilevel power electronic converters used in

0885-8977/$25.00 © 2007 IEEE

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1236 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 2, APRIL 2007

electric drives, and power system applications such as FACTS

and HVDC systems.
Since their introduction in the mid-1980s, FPGAs have
roughly doubled in capacity every year, with the current
state-of-the-art devices containing in excess of 200,000 logic
cells, thus enabling large system-on-chip (SoC) implementa-
tion. Concurrently, development in the software CAD tools
and intellectual property (IP) cores has also kept pace allowing
rapid prototyping of complex digital designs. Still designing
in VHDL ensures portability and platform independence. In
the area of power electronics and drives, FPGAs have hitherto
been used mainly for implementing control algorithms [10], Fig. 1. Characteristic V 0I curve of a generic IGBT for a specific value
of V .
[11] and/or PWM gating pattern generators [12], [13], either as

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stand-alone processors or as companion processors for DSPs.
This paper reports the first application of FPGAs for modeling
a complete ac drive system. The rest of the paper is organized as
follows: Sections II–VI present the modeling details followed
by the FPGA realization of the VSC, the induction machine,
the control system, the gating signal generator, and the mea-
surement system, respectively. Section VII shows how all of

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the individual models are brought together to achieve real-time
simulation of the complete drive system on a Altera Stratix
EP1S80 FPGA. Real-time simulation results are presented in
Section VIII, followed by conclusions in Section IX.

II. VOLTAGE-SOURCE CONVERTER MODEL

O Fig. 2. Basic circuit used to analyze the IGBT timing diagram.

The power-electronic drive includes a 2-level, 6-pulse IGBT-

based voltage-source converter. This section describes how the
VSC model was developed and implemented in the FPGA.
D
A. IGBT Electrical Characteristics
In a 2-level, 3-phase VSC, six IGBTs are necessary. If a
three-level three-phase converter is desired, 12 IGBTs are nec-
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essary. Although highly detailed IGBT models, which take into

account all the capacitances, inductances and resistances associ-
ated with the IGBT, can be found in literature [14], such models
are mainly used in simulation programs with integrated circuit
emphasis such as SPICE, SABER, etc., for device manufac- Fig. 3. Timing diagram of an IGBT during turn-on.
turing. For real time simulation such models are neither neces-
sary or possible (at least at the present time), due to the compu-
tational effort to simulate several connected IGBTs. In this case, is analyzed with the aid of the standard circuit, shown in Fig. 2,
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only the most important features of the IGBT must be taken into used by the manufacturer to determine the IGBT timing char-
account. acteristics. The values of the circuit elements are also standard
For drive applications, the IGBTs are used only in switched values defined by the manufacturer.
mode, i.e., Region I in Fig. 1. Furthermore, the largest possible Figs. 3 and 4 show a typical timing chart of an IGBT during
value for gate-to-emitter voltage is used to minimize con- turn-on and turn-off, respectively. These figures are also used
duction loss in this region. In this case, the forward characteristic to show the switching time definitions. As can be observed in
of the IGBT can be represented by a linear substitute character- Fig. 3, when the IGBT is turned-on, there is a initial time delay
istic (dotted line in Fig. 1), which is given as follows: between the on-signal at the gate and the growing value
of (and decreasing of ). After this time delay grows
(1) exponentially until it reaches its steady value after an overshoot,
defining the rise time depicted in Fig. 3. Fig. 4 shows the
In (1), is the device on-state resistance and is time delay between the turn-off gate signal and the instant at
the collector-emitter threshold voltage. These data can be easily which starts to decrease, defining . After this delay,
found in the IGBT manufacturer’s datasheet. the current decreases until it reaches 10% of its initial value,
Another important characteristic of an IGBT for the VSC is defining the fall time . These figures also define the current
the timing chart for switching operation of the device. This chart time , which is the elapsed time between the sensed gate signal

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PARMA AND DINAVAHI: REAL-TIME DIGITAL HARDWARE SIMULATION OF POWER ELECTRONICS AND DRIVES 1237

Fig. 4. Timing diagram of an IGBT during turn-off.

TABLE I
IMPLEMENTED DATA FOR CM100DU-24F IGBT UNIT FROM POWEREX

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Fig. 7. One leg of the three-phase VSC.

For each combination, in every time-step of the real-time sim-

ulation, the value of is used to determine whether the cur-
rent is flowing through the IGBT or the anti-parallel diode. If
and both gate signals are zero, the IGBTs are replaced

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by their off-state resistances and the steady-state output voltage
becomes .
For example, consider that at time , the gate signals
of and are changed to 1 and 0, respectively. If is
O positive, for it would flow through the diode
the steady-state output voltage would be
and
, the
voltage drop across the diode. After , will
start to conduct and will flow through the IGBT. The output
voltage will then rise linearly until it reaches its steady-state of
Fig. 5. Idealized timing characteristic of an IGBT during turn-on. . On the other hand, if is negative
and assuming that for the gate signals of and
D
were equal to 0 (dead-time), the current would flow through
the diode , and at it will continue flowing through
the same diode, resulting in the steady-state output voltage of
. The third and last possibility is when
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is equal to zero. In this case, the steady-state value for the output
voltage will be similar to the situation when the current was pos-
itive. The remaining switching combinations listed above can be
analyzed in a similar fashion.

B. FPGA Implementation
Fig. 6. Idealized timing characteristic of an IGBT during turn-off.
The functional block diagram of the hardware realization of
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a single leg of the VSC is shown in Fig. 8. The implementation

and the moment when the current reaches 99% of its steady-state was done entirely in VHDL.
value. Instead of receiving both gate signals, the model receives only
The characteristics of the implemented IGBT model are the gate signal for the switch . This signal goes through a
based on the CM100DU-24F IGBT from Powerex (Table I) block that adds the dead-time and then generates the two gate
with the idealized timing charts shown in Figs. 5 and 6. As signals for and . This approach was chosen to simulate the
can be observed in these figures, the major characteristics of presence of the IGBT gate drivers, which usually add the dead-
time-delay, rise time and fall time are taken into account. time after the PWM generation. With the gate signals, , and
The VSC model has been developed based first on the model as inputs, the model then implements a state machine with
for one single leg, as shown in Fig. 7. For this leg, all three four states, one for each possible combination of the switches.
possible combinations for the two IGBTs are considered: In each state, the output current value of the leg is verified in
1) switch closed and switch open; order to determine the path of current flow. The state machine
2) switch closed and switch open; interacts with the counters responsible for modeling the time
3) Both switches open (during the dead-time): delays, rise time and fall time, generating control signals that
• both switches are open just after was closed; drive these counters. The counter outputs are used to determine
• both switches are open just after was closed. the output voltage with respect to the negative terminal of dc

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1238 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 2, APRIL 2007

TABLE II
NUMBER FORMAT FOR THE VSC MODEL VARIABLES

. All the variables are considered as being signed fixed point

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numbers except the gate signals which are single bits. Table II
summarizes the number format for the input and output vari-
ables. In this table, 19.5 means that 19 b are used to represent
the integer part of the number and 5 b are used to represent the
fractional part. The internal variables of the model usually have
more fractional bits than the input/output variables in order to
preserve the resolution of the simulation calculations. The de-

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veloped model considers that in one simulation time-step there
is no change in the current signal. This is a valid assumption
Fig. 8. Functional block diagram of the hardware realization for one VSC leg. since the time-step chosen for the VSC model was 12.5 ns.
O III. INDUCTION MACHINE MODEL

A. Induction Machine Electrical Characteristics

The model is based on the fifth-order stator stationary ref-
erence frame squirrel cage induction machine model [15]. This
D
model can be described using two subsets of equations. The first
is a state-space equation for the electrical side, using the stator
and rotor fluxes as state variables. The second is for the me-
chanical side, using the rotor electrical speed as state variable.
The output variables are the stator and rotor currents for the first
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subset and the rotor speed for the second subset. The model can
be completely described by (2)–(6)
Fig. 9. System components for real-time simulation.

bus. The model also outputs the current through or

, which will be used to determine the output current of the
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dc link.
As mentioned earlier, the model implements the voltage
drop across the IGBT. Due to the small value of (typically
around 1 according to the datasheet), it is possible to
consider a constant voltage drop independent of the current .
In this case, (1) is replaced by when the
current is flowing through the IGBT. The voltage drop (2)
across the anti-parallel diode is also considered a constant value
when the current is flowing through it. All of the necessary data
retrieved from the component’s data sheet are shown in Table I.
After the model of one leg of the converter was built, it was (3)
duplicated to build the other two legs to implement the three-
phase VSC shown in Fig. 9. The overall VSC model requires
as inputs, the three phase currents, the dc voltage and the three (4)
gate signals. The outputs of the model are the three voltages ,
and with respect to the negative dc bus and the current (5)

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PARMA AND DINAVAHI: REAL-TIME DIGITAL HARDWARE SIMULATION OF POWER ELECTRONICS AND DRIVES 1239

TABLE III
INDUCTION MACHINE PARAMETERS

TABLE IV
NUMBER FORMAT FOR THE INDUCTION MACHINE MODEL VARIABLES

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Fig. 10. Functional block of the implemented induction machine model. adders and multipliers, and registers were used to add the nec-
essary time-delays. The block in Fig. 10 responsible for deter-
where mining the flux magnitude, given by (8), was implemented using
O a binary square root function. The flux position determination,
given by (9) and (10), was implemented with two dividers and
two multiplexers to implement the two position options in these
(6) equations
(8)
is the mutual inductance; and are the stator and
rotor self inductances; and are the stator and rotor re- when
(9)
when
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sistances; is the electrical rotor speed; is the number of
poles and is the total rotor inertia. is the load torque; , when (10)
, and are the stator and rotor flux components; , when
, and are the stator and rotor current components; The model also converts and to the rotor flux ref-
and are the stator voltage components in the stationary
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erence frame values, which are required by the controller pre-

stator reference frame. sented in the next section.
The parameters of the 4-pole, 50 HP, 460 V squirrel cage
induction motor used for the real-time simulation are shown in
B. FPGA Implementation
Table III.
For hardware realization, the machine model must be dis- The system shown in Fig. 10 was implemented in MATLAB/
cretized. As can be observed from (2)–(6) the model is non- SIMULINK, using the DSP Toolbox from Altera, and the gen-
linear, not only due to the parameter nonlinearity, but also due erated code was integrated with the rest of the system. Table IV
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to the multiplication of state variables. Owing to the mechan- shows the number format for the input and output variables.
ical time constant being larger than the electrical time constants,
the system can be analyzed as two decoupled systems. There- IV. CONTROL SYSTEM
fore, during discretization the rotor speed can be assumed to be
constant during one time-step of the electrical system solution, A. Direct Field-Oriented Control
which is followed by the mechanical system solution. This ap- Since its introduction by Blaschke [16], it is well known that
proach avoids the nonlinearity due to variable multiplication. field-oriented control allows high performance speed and torque
Trapezoidal rule with a time-step s was used to response of induction machines. When the control is oriented by
discretize the model based on the following transformation: the rotor flux, the induction machine behaves like a dc machine
with separate excitation. Considering a machine representa-
(7) tion, where the axis is aligned with the rotor flux space vector
rotating at rad/s and the axis is 90 apart, the following
equations [17] can be obtained:
The functional block diagram of the discretized machine
model is shown in Fig. 10. The discretized versions of (2)–(6)
were implemented using basic arithmetic functions such as (11)

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1240 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 2, APRIL 2007

Fig. 11. Direct field-oriented controller based on rotor flux. Fig. 12. Implementation of a PI controller.

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TABLE V
(12) NUMBER FORMAT FOR THE CONTROLLER VARIABLES

(13)

As can be observed in (11)–(13), the axis current controls

the flux while the axis current, considering the flux constant,
controls the torque and the machine speed. In these equations,

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is the rotor time constant defined as .
When the induction machine is fed by a voltage source con-
verter instead of a current source converter, the following equa-
tions can also be obtained:
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(14) the controller. The adder that is used as an integrator has an en-
able input, which is disabled every time the controller’s output
reaches its limit (saturation), avoiding a continuing integration
(15)
of the error when the controller is saturated. Due to the inherent
parallelism of the FPGA, all the controllers execute their func-
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(16) tions at the same time, which would allow a much higher oper-
ational frequency than the chosen 4 kHz.
(17) The gains of the PI controllers were chosen using the pole-
placement method followed by fine tuning in offline simula-
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Equations (14)–(17) reveal that there is an axis coupling rep- tion. The model was implemented in MATLAB/SIMULINK
resented by the terms and , which is contrary to the with a posteriori conversion to the VHDL code. It is impor-
principle of vector (decoupled) control of the induction motor. tant to notice that the control system was directly implemented
However, it is addressed by the high gain current controller. in the hardware, without the use of any co-processor such as
Fig. 11 shows the controller block diagram. The controller re- the embedded softcore NIOS processor, available for the Stratix
quires the measurement of rotor speed , stator currents ( FPGA.
and ), the modulus of the rotor flux and rotor flux posi- As mentioned in the previous subsection, the controller re-
tion . and are the references for the rotor flux and quires the information about the rotor flux, which is usually ob-
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electrical speed, respectively. The information about the rotor tained from an observer. As this was a simulated system, the
flux (magnitude and angle) is usually obtained with the aid of a rotor flux information was readily available in the induction ma-
flux observer [18], [19]. chine model and the observer was not modeled. Table V shows
the number format for the input and output variables of the im-
B. FPGA Implementation plemented controller.
The hardware realization is a straightforward implementation
of the block diagram shown in Fig. 11. All PI controllers have V. GATING SIGNAL GENERATION
saturated outputs and are implemented in the same fashion, as
shown in Fig. 12. A. Space Vector Pulse-Width Modulation
The control frequency was chosen to be 4 kHz in order to The aim of symmetrical space vector pulse-width modulation
maintain compatibility to average commercial controllers, al- (SVPWM) is to generate a controllable three-phase voltage for
though a higher control frequency is also possible. Each PI con- the ac machine by using only two adjacent available voltage
troller uses one two-input subtractor, two adders with two inputs space vectors. This is achieved in a way that the mean value
and three multipliers with one input (the other input is a constant of the voltage output within the PWM period is equal to the
value). The comparator and multiplex blocks are used to saturate reference value used to generate the PWM pattern, in order to

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PARMA AND DINAVAHI: REAL-TIME DIGITAL HARDWARE SIMULATION OF POWER ELECTRONICS AND DRIVES 1241

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Fig. 13. Synthesized voltage space vectors.

Fig. 15. Functional block diagram of the SVPWM hardware realization.

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the PWM period; is the time during which the upper switch
of the leg is ON.
The SVPWM algorithm can be described as follows.
O 1) At the beginning of the PWM period, the voltages to be
generated are sampled.
2) The voltages are sorted according to .
3) , and are evaluated from (18).
4) The turn-off time of each switch is calculated in order to
produce a symmetrical SVPWM.
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5) The gate signals of Fig. 14(a) are applied to each upper
Fig. 14. (a) Generic gating signal pattern generated by the SVPWM. (b) Phase switch of the VSC ( , , or ). The gate signals for the
voltage generated by the VSC, with respect to the load neutral point. lower switches are the complements of those for the upper
switches. Dead-time insertion is part of the VSC model
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discussed in Section II.

minimize the harmonic distortion of the rotating magnetomotive
force in the ac machine. B. FPGA Implementation
Fig. 13 shows the eight possible voltage space vectors the Fig. 15 shows the functional diagram of SVPWM implemen-
VSC can synthesize, as a function of the state of switches , tation with a PWM frequency of 8 kHz. The synchronized PWM
, and (numbers inside the parentheses). counter is reset in each new PWM cycle when it generates an en-
Fig. 14 shows a generic gating signal pattern generated by the able signal for the register. Once the voltage values are sam-
symmetrical SVPWM. Referring to Figs. 14 and 9, if the gating pled, they are transformed to the three phase system and sorted
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signals , , and are applied to switches , , and , according to . Then the model implements (18)
respectively, then the voltage space vectors used to synthesize to obtain the , , and values, which are within the PWM
the voltage output are those denoted in Fig. 14(a), and the phase period, by symmetrical comparators. The output of the symmet-
voltage , , and will be equal to , , and , respec- rical comparators are the gate signals , , and , which are
tively. Fig. 14(b) clearly shows that only two adjacent active properly related to the outputs , , and by the unsorted
voltage space vectors are used in one PWM period and that the logic block.
application time of the active vectors depends only of the switch The model also generates a synchronization signal (one single
time difference. If , , and represent the mean value of clock pulse on each new PWM period) not shown in Fig. 15
the output voltages to be generated with , the which will be used by the measurement block explained in the
following equation can be obtained from Fig. 14: next section. Table VI summarizes the number format for the
input and output variables of the implemented SVPWM.
(18)
VI. MEASUREMENT SYSTEM
where , 2, 3 represents the legs , , after the required The voltage input to the machine as a consequence of the
ordering ; is the dc link voltage; is PWM VSC control is a waveform with high frequency com-

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1242 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 2, APRIL 2007

TABLE VI
NUMBER FORMAT FOR THE SVPWM VARIABLES

ponents. The fundamental component of this supply voltage

is often needed by the control system, for example, to imple-
ment a flux observer. However, control systems usually lack the
high input frequency bandwidth to measure the high frequency

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components of the input voltage. This voltage measurement is
usually done by filtering the input voltage by analog or digital
means with the drawback of adding a phase delay proportional Fig. 16. Stratix FPGA development board used to build the real-time simulator.
to the fundamental frequency of the voltage. When the control
system is a variable frequency control, such as vector control,
this phase delay may be difficult to predict and to compensate.
In order to avoid this varying time delay, a digital integration

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of the PWM voltage in one PWM period was implemented. The
measurement system implements (19) and (20) given as follows:

(19)
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(20)

where and are the measured value of the output’s

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fundamental voltage component in the th PWM period;
and are the PWM output voltages of the
VSC.
The integration described in (19) and (20) must be synchro-
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nized with the PWM period in order to precisely implement the

measurement system. Therefore, it is necessary that the PWM
system generator outputs a synchronizing signal to the measure- Fig. 17. Block diagram on the Stratix FPGA Development Board used to build
ment system. This signal is used to output the integrated value the real-time simulator. The number inside the arrow indicates the bus width of
and to reset the integrators in every new PWM period. The mea- the component.
surement system is also responsible for determining the mean
value of within the PWM period.
and to reverse the speed set-point. The DIP switches were used
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to load the machine and to control the increment/decrement

VII. REAL-TIME DIGITAL SIMULATION OF PWM VSC-FED of speed set-point. In order to view all the major signals of
INDUCTION MACHINE DRIVE the real-time simulation, an auxiliary board by Analog Devices
The simulator was build on a Stratix EP1S80 FPGA Devel- was also used. This board implements a 40-channel DAC based
opment Board (Fig. 16), supplied by the Canadian Microelec- on the AD5380 converter, and interfaces directly to the FPGA
tronics Corporation (CMC). The FPGA (Stratix EP1S80 from board using one of the two 40-pin connectors.
Altera) used in this board has as main features: 79,040 logic el- Once all the models presented in the previous sections were
ements (LEs); 7,427,520 total RAM bits; 176 DSP blocks with developed using VHDL, a final file was written to properly con-
9 bit elements; 12 PLLs; and 679 maximum user I/O pins. nect all of them to achieve real-time simulation of the complete
The development board includes an 80-MHz crystal oscillator system shown in Fig. 9.
used as a basic clock generator, two digital-to-analog converters The overall system requires three main inputs:
(DACs), and two analog-to-digital converters (ADCs), as shown 1) dc-link voltage ;
in Fig. 17. The development board also includes two 256 K 36 2) reference for the rotor speed ;
SRAM memory banks, which are not being used by the simu- 3) reference for the magnitude of the rotor flux .
lator. To create a human interface to the simulator, the three push There is also one additional input used to apply load
buttons are used to reset the system, change the speed set-point onto the induction machine shaft, to simulate load transients.

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PARMA AND DINAVAHI: REAL-TIME DIGITAL HARDWARE SIMULATION OF POWER ELECTRONICS AND DRIVES 1243

TABLE VII accuracy and the available FPGA resources. The bit-length of
FPGA RESOURCES UTILIZED BY SYSTEM COMPONENTS input/output variables, such as voltages measured in a prac-
tical application, was limited to 24 b, in order to simulate a
24-b ADC. The fractional part of such variables was represented
using 5 b, which results in a reasonable resolution (0.03125)
commonly found in real world applications where ADCs are
introduced. The bit-length of the internal variables of the sim-
ulator was limited to a maximum value of 32 b with a longer
fractional part in order to reduce the discretization error of the
input variables, and to minimize the round-off error of output
variables.
For example, for the implementation of the field-oriented
controller (Section IV-B), it was necessary to implement a

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function for axis conversion. This function was im-
plemented using a look-up-table, whose output has a 2.11
representation (two b for the integer part and 11 b for the
fractional part), while the reference voltage was coded using
a 19.5 representation, with only 5 b for the fractional part.
With a 2.11 representation, the possible numerical range is
1.99951171875 to 2.00000000000, which easily accommo-

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dates the range of the function with
an accurate resolution (0.00048828125), while minimizing the
round-off error of the output variable (reference voltage). The
rest of the control variables, such as currents and speed signals
O listed in Table V, use a 32-bit resolution (19.13) to achieve
required accuracy.
Fig. 18. Real-time simulator timing resolution.
VIII. RESULTS AND DISCUSSION
This section presents the real-time experimental results ob-
Once the VHDL code for the simulator was compiled, the
tained from the simulator. The results are shown with the aid of
D
bitstream was downloaded to the development board through
a four-channel oscilloscope connected to the DACs. The results
the JTAG interface. Table VII summarizes the FPGA resources
show a detail of the IGBT switching characteristic, the VSC
used by individual components of the simulator. In this table,
steady-state waveforms, and the induction machine transients.
the connection system refers to the final file necessary to con-
EA

nect all developed components and D/A interface refers to the

A. IGBT Switching Characteristics
VHDL component necessary to interface the real-time simulator
to the auxiliary Analog Devices board. Table VII shows that the Fig. 19 shows the output voltage of one leg of the three-
overall design occupies only about half of the logic elements of phase VSC (Fig. 7) with respect to the negative side of the
the FPGA; the induction machine model being computationally dc bus as a function of the gate signal , when is posi-
intensive takes up most of the DSP blocks. tive. Considering the instant at which is turned-off and
Fig. 18 shows the multirate nature of the real-time simulation. the instant at which is turned-on it can be observed at
As can be observed, the components of the system use different the output voltage linearly decreases until it
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frequencies. The most important component, the VSC, requires reaches at . The voltage
the highest frequency ns to model its dynamics, remains until , when lin-
while it is directly connected to the induction machine model early increases until it reaches at
s and the measurement system ns , . In this case, the IGBT does not even turn
which runs at a slower frequencies. on, since its on-time is the minimum value allowed, equal to
All the required frequencies were derived from the common , which is less than the dead-time added by the cir-
clock frequency of 80 MHz. The subfrequencies were obtained cuit that drives the gate signal.
directly inside the FPGA using a PLL or after a further fre- Fig. 20 is similar to Fig. 19 but when the current is zero
quency division to achieve the desired frequency. and is turned-on after the dead-time. In this case, as can be
observed, at , linearly decreases until it
A. Impact of Bit Length on Simulation Accuracy reaches at and remains
at this value during the entire dead-time, when both switches
An important issue about the FPGA-based real-time simu- are off . When is turned-on,
lation is the bit-length of the implemented variables, and the after the dead-time, linearly falls again, accordingly to the
number of fractional bits reserved for each variable. This issue rise-time of switch , until it reaches at
was resolved as a compromise between the required numerical .

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1244 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 2, APRIL 2007

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Fig. 19. Output voltage (V ) of one leg of the three-phase VSC with respect Fig. 21. Steady state of the 60-Hz voltage v applied to the machine. (v ,
v ): 555 V/div.

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to the negative dc bus (Fig. 7) as a function of the gate signal (A1) when I
is positive.
O
D
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Fig. 22. Steady-state of the 60-Hz voltage v applied to the machine. (v ,

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v ): 480 V/div.
Fig. 20. Output voltage (V ) of one leg of the three-phase VSC with respect
to the negative dc bus (Fig. 7) as a function of the gate signal (A1) when I
is zero.
component at , the FFT calculated by the oscillo-
scope shows a fictitious dc component which was
added by the DAC since its output is a monopolar value between
B. Steady-State Results
0 V and 5 V. Other significant components are the sidebands
Figs. 21 and 22 show the VSC output after the induction ma- centered at kHz and kHz, since the PWM fre-
chine reaches its steady-state with . Fig. 21 quency is equal to 8 kHz. This FFT analysis is coherent with the
shows the VSC output voltage , a detailed portion of it, analytical results presented in [20].
its mean value within a PWM period determined by the Fig. 22 is equivalent to the previous figure, but shows
measurement system and its fast Fourier transform (FFT). The instead of . Considering a balanced load, the voltage
voltage is equal to the phase voltage , of the balanced is proportional to the phase-to-phase voltage ; it is
three-phase system that supplies the machine. In this figure possible to observe the one level voltage present in the phase-to-
is possible to observe the typical 2 level voltages present in phase voltage. The FFT results agree very well with analytical
the converter phase voltage. Besides the fundamental frequency analysis.

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PARMA AND DINAVAHI: REAL-TIME DIGITAL HARDWARE SIMULATION OF POWER ELECTRONICS AND DRIVES 1245

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Fig. 23. Machine speed (! ), electromagnetic torque (T ) and VSCs I cur- Fig. 25. Machine speed (! ) and currents (i and i ) for: machine startup at
rent for: machine startup at t , speed set-point variation at t , application and t , speed set-point variation at t , application and removal of load at t and t ,

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removal of load at t and t , respectively, and speed reversal at t . (! , ! ): respectively, and speed reversal at t . (! , ! ): 377 (rad/s)/div., (i , i ): 150
377 (rad/s)/div., T : 400 N.m./div., I : 150 A/div. A/div.
O
D
EA
R

Fig. 26. Offline simulation: machine speed (! ) and currents (i and i ) for:
machine startup at t , speed set-point variation at t , application and removal
Fig. 24. Offline simulation: machine speed (! ), electromagnetic torque (T ) of load at t and t , respectively, and speed reversal at t .
and VSCs I current for: machine startup at t , speed set-point variation at t ,
application and removal of load at t and t , respectively, and speed reversal at
t. observed from the machine torque and speed, the controller has
a fast performance during the transients, and no perturbation
C. Transient Results can be seen in the speed during the application or removal of
the load. As the machine was modeled ignoring the mechanical
Fig. 23 shows the machine speed , the speed reference losses, and the machine resistances are quite small, the value of
, the electromagnetic torque , and the mean value of is almost zero once the machine reaches steady-state. A sig-
within one PWM period when the machine is subjected to the nificant value of different from zero can be observed during
following transients: (1) machine startup with a speed set-point the machine transients and when the load is applied to the shaft.
of 150 rad/s at , (2) speed set-point variation to 377 rad/s at During the transients, the converter must supply or absorb the
, (3) application of 100 N.m. load at and removal of the power consumed or generated by the machine as a function of
load at , and (4) speed reversal to 377 rad/s at . As can be the controller action. It is possible to observe that this current

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1246 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 2, APRIL 2007

can be positive or negative, depending on the transient, which [5] V.-Q. Do, D. McCallum, P. Giroux, and B. D. Kelper, “A backward-
shows the inverter or rectifier operation of the VSC. forward interpolation technique for a precise modeling of power elec-
tronics in HYPERSIM,” in Proc. Int. Conf. Power Systems Transients,
Fig. 25 shows , , and the currents and for the same Rio de Janeiro, Brazil, Jun. 2001, pp. 337–342.
transients listed above. Once again the fast behavior of the con- [6] V. R. Dinavahi, M. R. Iravani, and R. Bonert, “Real-time digital simu-
troller can be seen during the transients. It is also possible to ob- lation of power electronic apparatus interfaced with digital controllers,”
IEEE Trans. Power Del., vol. 16, no. 4, pp. 775–781, Oct. 2001.
serve the current frequency variation during the speed reversal. [7] M. O. Faruque, V. Dinavahi, and W. Xu, “Algorithms for the ac-
These results have been validated by offline simulation using counting of multiple switching events in digital simulation of power
MATLAB/SIMULINK as shown in Figs. 24 and 26, and they electronic systems,” IEEE Trans. Power Del., vol. 20, no. 2, pt. 1, pp.
1157–1167, Apr. 2005.
clearly prove that the machine model and the control system are [8] H. Jin, “Behavior-mode simulation of power electronic circuits,” IEEE
working properly. Trans. Power Electron., vol. 12, no. 3, pp. 443–452, May 1997.
[9] L. Pak, M. O. Faruque, X. Nie, and V. Dinavahi, “A versatile
cluster-based real-time digital simulator for power engineering re-
search,” IEEE Trans. Power Syst., vol. 21, no. 2, pp. 1–11, May 2006.
[10] S. Jung, M. Chang, J. Jyang, L. Yeh, and Y. Tzou, “Design and im-
IX. CONCLUSION

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plementation of an FPGA-based control IC for ac-voltage regulation,”
IEEE Trans. Power Electron., vol. 14, no. 3, pp. 522–532, May 1999.
With the emergence of FPGAs with higher density, lower [11] A. de Castro, P. Zumel, O. Garcia, T. Riesgo, and J. Uceda, “Con-
current and simple digital controller of an ac/dc converter with power
cost, and higher processing rates, it is imperative that this tech- factor correction based on an FPGA,” IEEE Trans. Power Electron.,
nology be exploited for the real-time simulation of power elec- vol. 18, no. 1, pp. 334–343, Jan. 2003.
tronics and drives. With this goal in mind, this paper presented [12] Y. Tzou and H. Hsu, “FPGA realization of space-vector PWM control
IC for three-phase pwm inverters,” IEEE Trans. Power Electron., vol.
the digital hardware realization of a complete ac drive system on 12, no. 6, pp. 953–963, Oct. 1997.
a FPGA. The main challenge in achieving this realization was [13] V. Dinavahi, M. R. Iravani, and R. Bonert, “Design of a real-time digital

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the VSC for which a novel device-characteristic based model simulator for a D-STATCOM system,” IEEE Trans. Ind. Electron., vol.
51, no. 5, pp. 1001–1008, Oct. 2004.
was proposed. The model is extremely detailed allowing a pre- [14] K. Sheng, B. W. Williams, and S. J. Finney, “A review of IGBT
cise accounting of switching signals coming from the digital models,” IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1250–1266,
controller without the need for any correction algorithms. The Nov. 2000.
other components of the implemented real-time simulator in-
clude a detailed induction machine model, a direct field-oriented
O [15] P. C. Krause, O. Wasynczuk, and S. D. Sudhoff, Analysis of Electric
Machinery. New York: IEEE Press, Jan. 1995.
[16] F. Blaschke, “The principles of field orientation as applied to the new
control system, a space-vector PWM scheme, and a measure- transvector closed-loop system for rotating field machines,” Siemens
Rev., vol. 34, pp. 217–220, 1972.
ment system. The entire model was written in VHDL to preserve [17] D. W. Novotny and T. A. Lipo, Vector Control and Dynamics of AC
the portability and flexiblity of the design. Real-time digital sim- Drives. Oxford, U.K.: Oxford Univ. Press, 2000.
ulation results are presented under steady-state and transient [18] G. C. Verghese and S. R. Sanders, “Observers for flux estimation in
D
induction machines,” IEEE Trans. Ind. Electron., vol. 35, no. 1, pp.
conditions to demonstrate the successful implementation of the 85–94, Feb. 1988.
drive system. The FPGA resource utilization table provides an [19] Y. Hori and T. Umeno, “Implementation of robust flux observer based
idea of the level of model complexity that can be attained with field orientation (fofo) controller for induction machines,” in Proc.
Conf. Rec. IEEE Industry Applications Soc. Annu. Meeting, Oct. 1989,
current FPGA technology. We envision that in future real-time vol. 1, pp. 523–528.
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simulators, the concurrency and high-speed parallel operation of [20] J. T. Boys and P. G. Handley, “Harmonic analysis of space vector mod-
FPGAs can be taken advantage of by hardwiring computation- ulated PWM waveforms,” Proc. Inst. Elect. Eng. B, vol. 137, no. 4, pp.
197–204, Jul. 1990.
ally intensive portions of the system model. Such an implemen-
tation can be interfaced with a larger and more complex power Gustavo G. Parma (S’98-M’06) received the B.Eng.
system model running on a large-scale real-time simulator. The and Ph.D. degrees in electrical engineering from Uni-
applications of such implementation include the modeling of versidade Federal de Minas Gerais, Belo Horizonte,
Brazil, in 1996 and 2000, respectively.
multilevel multipulse converters not only for drives but also for Currently, he is a Professor at the University of
power system applications such as FACTS and HVDC systems. Minas Gerais, Belo Horizonte, Brazil. He was a
R

Postdoctoral Fellow at the University of Alberta,

Edmonton, AB, Canada during 2005–2006. His
research interests include machine control, slid mode
control, digital electronics, power electronics, and
REFERENCES real-time digital simulation and control.

[1] A. G. Jack, D. J. Atkinson, and H. J. Slater, “Real-time emulation for

power equipment development. I. Real-time simulation,” Proc. Inst.
Elect. Eng., vol. 145, no. 2, pp. 92–97, Mar. 1998. Venkata Dinavahi (M’00) received the B.Eng.
[2] H. Le-Huy, G. Sybille, P. Giroux, J. Soumagne, and F. Guay, “Dig- degree in electrical engineering from VRCE Nagpur
ital real-time simulation of a four-quadrant dc drive for static transfer University, Nagpur, India, in 1993, the M.Tech.
switch testing,” in Proc. IEEE Power Eng. Soc. Summer Meeting, 1998, degree from the Indian Institute of Technology,
pp. 761–765. Kanpur, in 1996, and the Ph.D. degree in electrical
[3] R. Champagne, L.-A. Dessaint, H. Fortin-Blanchette, and G. Sybille, and computer engineering from the University of
“Analysis and validation of a real-time AC drive simulator,” IEEE Toronto, Toronto, ON, Canada, in 2000.
Trans. Power Electron., vol. 19, no. 2, pp. 336–345, Mar. 2004. Currently, he is an Associate Professor at the
[4] P. Kuffel, K. Kent, and G. Irwin, “The implementation and effective- University of Alberta, Edmonton, AB, Canada. His
ness of linear interpolation in digital simulation,” in Proc. IPST Int. research interests include electromagnetic transients,
Conf. Power Systems Transients, Lisbon, Portugal, Sep. 1995, pp. power electronics, and real-time digital simulation
499–504. and control.

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