PHẠ M VIỆT HÙNG
INTERNSHIP
PROFILE
I am currently a final-year student majoring in Electrical and Electronics Engineering. I
intend to start my career focusing on VLSI. I am a highly motivated and dedicated
VLSI student with an academic background and experience in using EDA tools, HDL
coding, and self-studied additional IP from various sources. With a strong desire to
gain a good understanding and strategic insight into the field of VLSI, especially in
Digital Design.
CONTACT Engaging in a long-term internship program within the company will push me to
develop resilience and long-term skills. I ensure to work enthusiastically, embracing
0975817546 on challenges, disciplined work.
Thu Duc, Ho Chi Minh City Capstone Project 1: RISC-V 32F/D Floating-Point Extensions
Processor interfaces with peripheral and SRAM on FPGA( 2024)
linkedin.com/Viehung
In practice, MCUs require peripheral pins to interface with external devices. In this
design, I assumed the peripherals to be switches, seven-segment displays, and
github.com/hungphamvie186 SRAM SDRAM. I designed a new IP module so that when deploying the RISC-V kit
onto the DE2 FPGA, it can utilize the on-board SRAM (16M x 16). Additionally, I
EDUCATION executed several preloaded assembly programs.
To enhance work efficiency, I wrote a Makefile to quickly and effectively run
2021 - Present simulations using Synopsys tools like VCS and Verdi.
HO CHI MINH UNIVERSITY OF I have designed a RISC-V processor using pipeline techniques (both non-
TECHNOLOGY (HCMUT) forwarding and forwarding) to minimize the number of cycles requiring NOP and
Electronics and increased the CPU's IPC (Instructions Per Cycle). I have also added an ALU with the
Telecommunication Engineering capability of floating-point 32-bit compliant IEEE 754 computation for RISC-V to
support the execution of ISA RV32F/D Floating-Point Extensions.
Vending machine with verilog ( 2024)
SKILLS A simple vending machine with the capability to dispense change.
To optimize the execution speed, I replaced the ripple adder with a Carry
Presentation Lookahead Adder (CLA) to improve runtime efficiency and reduce circuit size.
Effective Communication Find max min in SRAM memory(2023)
IP capable of finding the maximum and minimum values within a 1k memory
Critical Thinking
region. Capable of being upgraded to scan a larger memory area.
Self-Studying I have written a Makefile to streamline the invocation of Cadence’s Xcelium and
TOEIC R&L: 690 Genus tools, enhancing speed and accelerating the workflow.
The Electronics Department's research group
I am part of the MARS (Multipurpose Advanced RISC-V Systems) research group of
TECHNICAL the department. I am currently working on RISC-V superscalar architecture and
developing additional peripheral IPs.
RTL Design, CMOS, DSP Online Courses & Certifications
Verilog CS61C, UC Berkele
Here, I learned about how a basic CPU operates, why it is designed in a
AVR, RISC-V Assembly
fundamental way, and the performance of different methods.
EDA Tool: Cadance, Synopsys,...
VLSI Hardware Design Comprehensive Masterclass
Using tools for simulation and
I learned about the efficient design process in the field of digital design, learned
synthesis how to write HDL code more effectively, and applied it to some basic IPs such as
FIFO.
C Programming
Linux, Bash, Shell
ACTIVITIES
HCMUT Blue Sharks: The club organizes sports events for the university.
Comparch: RISC-V architecture
Has experience coordinating and organizing university-level football
Script language: Makefile, TCL. tournaments and the inter-university football tournament VUG in the years
2022 and 2023.
Organized the Student Tet Festival and Spring Volunteer Program in Da Lat
within the club.
