UNIT 11

LATCHES AND FLIP-FLOPS

Fall 2022
 Latches and Flip-Flops
2 © Iris H.-R. Jiang
¨ Contents
¤ Set-Reset latch
¤ Gated D latch

¤ Edge-triggered D flip-flop

¤ S-R flip-flop
¤ J-K flip-flop

¤ T flip-flop

¤ Flip-flops with additional inputs

¨ Reading
¤ Unit 11

Latches & FFs

 Recap: Two Types of Switching Circuits
3 © Iris H.-R. Jiang
¨ Combinational circuits (memoryless)
¤ Outputs depend only on present inputs
X1
X2 Combinational circuit
... Z = F(X1, X2, …, Xn)
Xn F

¨ Sequential circuits (with memory)

¤ Outputs depend on both present & past inputs
¤ In general, sequential ckts = combinational ckts + memory
X1
X2 Combinational circuit
...

F Z = F(X1, X2, …, Xn, D(n-1))

Xn

D(n-1) D(n)

Memory element

Latches & FFs

 How to Remember the Past?
4 © Iris H.-R. Jiang
¨ Feedback: the output of one of the gates is connected back into
the input of another gate in the ckt so as to form a closed loop
¤ e.g., inverter with feedback
n Q: How fast does the circuit oscillate?
n A: Determined by the propagation delay of the inverter
Feedback X Oscillation at inverter output

X
t
¤ e.g., a feedback loop with two inverters
n Two stable states
n Latch: basic memory unit (store 1 bit)
Now, the values
0 1 1 0 1 0 0 1
can be kept

Latches & FFs

5 Set-Reset Latch

S-R latch

Latches & FFs

 Set-Reset (S-R) Latch (1/2)
6 © Iris H.-R. Jiang

P P
Q Q
1 0
S 0 0 S 1 1
R0 R0
stable set
Q=0 S: 0 ®1; Q: 0 ®1

P P
Q Q
0 1
S 0 1 S 0 0
R0 R1
stable reset
Q=1 R: 0 ®1; Q: 1 ®0

P = Q'
Latches & FFs
 S-R Latch (2/2)
7 © Iris H.-R. Jiang
¨ Cross-coupled form
Q Q' Q' Q

R : Reset
L
S : Set

R S R S

¨ S = R = 1 Þ Unstable! Not allowed!!

1®0
S
P 0 ® 1 ® 0 ® 1…

P ¹ Q'

R Q 0 ® 1 ® 0 ® 1…
1®0

Latches & FFs

 Next-State Equation
8 © Iris H.-R. Jiang
¨ Timing diagram
S S
P 0 1 0
R

Q є є
R Q
t1 t2 t3 t4 t

¨ Operation t1+є t3+є є: 2 gate delay

S(t)
S(t) R(t) Q(t) Q(t +є)
R(t)Q(t) 0 1
0 0 0 0 00 0 1 Next-state equation:
Unchanged
0 0 1 1 (Characteristic equation)
0 1 0 0 01 1 1 Q+ = S+R'Q
Reset to 0
0 1 1 0 under SR=0
1 0 0 1 K-map 11 0 X (S=1, R=1 not allowed)
Set to 1
1 0 1 1
10 0 X
1 1 0 –
Inputs not allowed
1 1 1 – Q(t+є)=S(t)+R'(t)Q(t)
Latches & FFs
 Application: Switch Debouncing
9 © Iris H.-R. Jiang
¨ When a mechanical switch is opened or closed, switch contacts
tend to vibrate before settling down Þ Debounce with S-R latch
¤ e.g, when the switch is flipped from a to b…
¤ Work only with a “double throw” switch

n Double throw: switch between two contacts

n Single throw: switch between one contact and open S=R=0
Q unchanged
S
S
b
+V
1 R
a
Q
R
Q

Pull down resistors Switch Switch Switch

at a Bounce between Bounce at b
at a a and b at b
Latches & FFs
 Alternative Form with NAND-Gates
10 © Iris H.-R. Jiang
¨ S-R latch: active-low inputs for S & R
S
Q S R Q Q+

1 1 0 0
Unchanged
1 1 1 1

R Q′ 1 0 0 0 Reset to 0
1 0 1 0
0 1 0 1
Set to 1
S S Q 0 1 1 1
L 0 0 0 –
Inputs not allowed
R R Q′ 0 0 1 –

Latches & FFs

11 Gated D Latch

D Q
L
G Q′

Latches & FFs

 Gated D Latch
12 © Iris H.-R. Jiang

G 0 1 0
D
S Q
G L D

R Q′
Q

G D Q Q+ GD
Q 00 01 11 10
D Q 0 0 0 0
L 0 0 0 1 0
0 0 1 1 Unchanged
G Q′
0 1 0 0 Q+= Q
0 1 1 1 1 1 1 1 0
1 0 0 0
Q+=G′Q+GD
1 0 1 0 Update
1 1 0 1 Q+= D
1 1 1 1
Latches & FFs
13 Edge-Triggered D Flip-Flop

D Q

Ck Q′

Latches & FFs

 Edge-Triggered D Flip-Flops
14 © Iris H.-R. Jiang
¨ Output changes are aligned with clock edges
¤ Positive (rising-edge) trigger
¤ Negative (falling-edge) trigger

¤ Symbol ¤ Truth table

D Q Q+
Q′ Q Q′ Q
FF FF 0 0 0
Ck Ck Q+ = D
D D 0 1 0
1 0 1
Rising-edge trigger Falling-edge trigger 1 1 1

¤ Timing diagram for falling-edge triggered D FF

D 1 0 1 1 0

Ck

Q 0 1 0 1 1 0 0
Latches & FFs
 D FF – Rising Edge Trigger
15 © Iris H.-R. Jiang
¨ Construct from 2 gated D latches
P
D D1 Q1 D2 Q2 Q
L1 L2
CLK
G1 G2

¨ Timing diagram (setup/hold time)

L2 hold L1 hold L2 hold
CLK=G2 Q: What’s the
difference between
G1 a latch and a FF?
D

Q A Flip-Flop has a clock signal,

while a latch does not.

Latches & FFs

16 S-R Flip-Flop

S Q
Ck
R Q′

Latches & FFs

 S-R Flip Flop S Q
Ck © Iris H.-R. Jiang
17
¨ Output changes at clock edges R Q′
¨ Construct from 2 latches
S
S P
S Q Q
CLK’
CLK Master
Slave
R P′
R R Q′ Q′

CLK

¨ Operation CLK′
S R operation
S
0 0 No state change
0 1 Reset Q to 0 (after active Ck edge) R
1 0 Set Q to 1 (after active Ck edge)
P
1 1 Not allowed
Q
t1 t2 t3 t4 t5
Not an edge-triggered FF
Latches & FFs Þ Do not allow SR change while CLK is low
18 J-K Flip-Flop

J Q
Ck
K Q′

Latches & FFs

 J-K Flip-Flop Q′ Q
FF
19 K Ck J © Iris H.-R. Jiang
¨ Extension of S-R FF
¤ J: jump to 1
¤ K: clear to 0 J S P
S Q Q
CLK Master
Slave
K R P′
R Q′ Q′

J K Q Q+ Q+ = JQ′ + K′Q J = K = 1, Toggle

CLK
0 0 0 0
Unchanged
0 0 1 1
0 1 0 0 J
Clear to 0
0 1 1 0
1 0 0 1 K
Jump to 1
1 0 1 1
1 1 0 1 Q tp tp tp
Toggle
1 Latches
1 1 & 0FFs t1 t2 t3
20 T Flip-Flop

T Q

Ck Q′

Latches & FFs

 T Flip-Flop Q′
FF
Q

Ck
21 T © Iris H.-R. Jiang
¨ T: Toggle
T Q Q+=T′Q+TQ′=TÅQ Ck
0 0 0
Unchanged T
0 1 1
1 0 1
Toggle Q tp tp
1 1 0
t1 t2 t3 t4
¨ Implementation

Q′ Q J-K FF based: Q′ Q D FF based:

J = K = 0 Unchanged D input: TÅQ
J = K = 1 Toggle Q+ = TÅQ
K Ck J Ck D
Q+ = JQ′ + K′Q = TQ′ + T′Q
= TQ′ + T′Q

T Clock Clock

T
Latches & FFs
22 FFs with Additional Inputs

Latches & FFs

 D FF with Clear and Preset
23 © Iris H.-R. Jiang
¨ Use additional inputs to set FF to an initial state independent of
the clock
¤ e.g., asynchronous Clear and Preset

Q′ Q
CLK
ClrN PreN
Ck
D D

Ck D PreN ClrN Q+ ClrN

x x 0 0 - (not allowed)
x x 0 1 1 PreN
x x 1 0 0
↑ 0 1 1 0 Q
↑ 1 1 1 1
t1 t2 t3 t4
0,1,↓ x 1 1 Q (no change)
Normal FF Keep whole cycle
Latches & FFs
 D FF with Clock Enable
24 © Iris H.-R. Jiang
¨ We want some Flip-flops to hold existing data even though the
data input may be changing
¤ Gated clock: gate the clock by clock enable (CE)

D Q
CE
Ck Q′

Din D Q
0
D Q
CLK Din 1
Ck Q′
En
CE
CLK Ck Q′

Q+ = D = CE•Q + CE• Din

Latches & FFs

25 Summary

Latches & FFs

 Characteristic Equations for Latches & FFs
26 © Iris H.-R. Jiang

Type Q+
S-R latch or FF Q+ = S + R'Q (SR = 0)
Gated D latch Q+ = G′Q + GD
D FF Q+ = D
D-CE FF Q+ = D•CE + Q•CE'
J-K FF Q+ = JQ′ + K′Q
T FF Q+ = TÅQ

Latches & FFs