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Sol+Marking scheme Comp Arch Labtest 2025

The document describes a series of Verilog modules for digital design, including a sequence detector (SEQ_DET), binary counter (BIN_Counter), decoder (DEC_8), and an integrator (INTG). Each module has specific input and output functionalities, with grading criteria outlined for behavioral and state machine implementations. Additionally, a testbench is provided to simulate and monitor the behavior of the INTG module.

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10 views

Sol+Marking scheme Comp Arch Labtest 2025

The document describes a series of Verilog modules for digital design, including a sequence detector (SEQ_DET), binary counter (BIN_Counter), decoder (DEC_8), and an integrator (INTG). Each module has specific input and output functionalities, with grading criteria outlined for behavioral and state machine implementations. Additionally, a testbench is provided to simulate and monitor the behavior of the INTG module.

Uploaded by

ironmaansnap
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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module SEQ_DET (

input wire CLK,


input wire RST,
input wire X,
output reg Z1 Sequence detector module:
);
6 Marks. If Moore machine not used
// State encoding using parameters then only 3 marks. If behavioral not
parameter IDLE = 3'b000; used then 0 marks.
parameter S1 = 3'b001;
parameter S10 = 3'b010;
parameter S100 = 3'b011;
parameter S1001 = 3'b100;

reg [2:0] current_state, next_state;

// State transition logic


always @(posedge CLK) begin
if (RST)
current_state <= IDLE;
else
current_state <= next_state;
end

// Next state and output logic


always @(current_state,X) begin
// next_state = current_state;
// Z1 = 1'b0;

case (current_state)
IDLE: begin
if (X)
next_state = S1;
else
next_state = IDLE;
end

S1: begin
if (X)
next_state = S1;
else
next_state = S10;
end

S10: begin
if (X)
next_state = S1;
else
next_state = S100;
end

S100: begin
if (X)
begin
next_state = S1001;
end
else
next_state = IDLE;
end

S1001: begin

if (X)
next_state = S1;
else
next_state = S10;
end

default: next_state = IDLE;


endcase
end
always @(current_state)
begin
case(current_state)
IDLE: Z1 = 0;
S1: Z1 = 0;
S10: Z1 = 0;
S100: Z1 = 0;
S1001: Z1 = 1;
default: Z1 = 0;
endcase
end
endmodule

///////////////////////////////////////--BIN_Counter--
/////////////////////////////////////

module BIN_Counter (
output reg [2:0] Q_out,
input wire CLR1, Binary Counter module:
input wire CLR2,
4 Marks. If saturation logic not done
input wire Clock
); then only 2 marks. If behavioral not
always @(posedge Clock) begin used then 0 marks.
if (CLR1 || CLR2)
Q_out <= 3'b000;
else
Q_out <= (Q_out == 3'b111) ? 3'b111 : Q_out + 1;
end
initial
Q_out = 3'b000;
endmodule

////////////////////////////////////////////////////--DEC_8--
/////////////////////////////////////

module DEC_8 (
output reg [7:0] O,
input wire [2:0] S
);

always @(*) begin


O = 8'b00000000;
case (S)
Decoder Module:
3'b000: O[0] = 1;
3'b001: O[1] = 1; 3 Marks. If behavioral not used then
3'b010: O[2] = 1;
3'b011: O[3] = 1; 0 marks.
3'b100: O[4] = 1;
3'b101: O[5] = 1;
3'b110: O[6] = 1;
3'b111: O[7] = 1;
default: O = 8'b00000000;
endcase
end

endmodule

////////////////////////////////////////////////////--INTG--
/////////////////////////////////////

module INTG (
output wire [7:0] Z2,
input wire X,
input wire CLK,
input wire RST,
output wire z1,
output wire [2:0] Q_out
Integrator module:
);
2 marks each for instantiating 3
wire Z;
// Instantiate SEQ_DET modules with correct connections =
SEQ_DET seq_det_inst ( 6 Marks. If behavioral not used then
.Z1(Z), 0 marks.
.X(X),
.CLK(CLK),
.RST(RST)
);

// Instantiate BIN_Counter
BIN_Counter bin_counter_inst (
.Q_out(Q_out),
.CLR1(RST),
.CLR2(Z2[3]),
.Clock(Z)
);

// Instantiate DEC_8
DEC_8 dec_8_inst (
.S(Q_out),
.O(Z2)
);
assign z1=Z;
endmodule

/////////////////////////////////////////TESTBENCH///////////////////////
//////////

module TESTBENCH;

reg X, CLK, RST;


wire [7:0] Z2;
wire Z1;
wire [2:0]Q_out;

INTG dut (
.z1(Z1),
.Z2(Z2),
.X(X),
.CLK(CLK),
.RST(RST),
.Q_out(Q_out)
);

// Generate clock signal


initial CLK = 1;
always #5 CLK = ~CLK;
// for printing
integer i=0;
always #10 i=i+1;
// Test sequence
initial begin
// Initialize inputs
RST = 1;
//Z1=1'b0;
X = 0;
#10 RST = 0;

// Input sequence
X = 1;
#10 X = 0;
#10 X = 0;
#10 X = 1;
#10 X = 0;
#10 X = 0;
#10 X = 1;
#10 X = 1;
#10 X = 0;
#10 X = 0;
#10 X = 1;
#10 X = 0;
#10 X = 0;
#10 X = 0;
#10 X = 0;
#10 X = 1;
#10 X = 0;
#10 X = 0;
#10 X = 1;
#10 X = 0;
#10 X = 0;
#10 X = 1;
#10 X = 0;
#10 X = 0;
#10 X = 1;
// Finish simulation
#10 $finish;
end

// Monitor output values


initial begin
$monitor("i=%d|Time=%0t | Q_out=%b | X=%b | Z1=%b | Z2[3]=%b",
i,$time,Q_out, X, Z1 , Z2[3]);
end

endmodule

Z1 correct: 7 Marks.
No partial marking

Z2 correct: 8 Marks
No partial marking

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