XEF216-512-FB236 Datasheet

2020/10/05
Document Number: X007546
 XEF216-512-FB236 Datasheet

Table of Contents
1 xCORE Multicore Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 XEF216-512-FB236 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Example Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8 Boot Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 USB PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11 RGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
12 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
13 Board Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
15 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
16 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
A Configuration of the XEF216-512-FB236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
B Processor Status Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C Tile Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
D Node Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
E USB Node Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
F USB PHY Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
G JTAG, xSCOPE and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
H Schematics Design Check List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I PCB Layout Design Check List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
J Associated Design Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
K Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
L Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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 XEF216-512-FB236 Datasheet

1 xCORE Multicore Microcontrollers

The xCORE200 Series is a comprehensive range of 32-bit multicore microcontrollers that
brings the low latency and timing determinism of the xCORE architecture to mainstream
embedded applications. Unlike conventional microcontrollers, xCORE multicore micro-
controllers execute multiple real-time tasks simultaneously and communicate between
tasks using a high speed network. Because xCORE multicore microcontrollers are com-
pletely deterministic, you can write software to implement functions that traditionally
require dedicated hardware.

X0Dxx xTIME xTIME X1Dxx

scheduler
PLL scheduler
I/O pins I/O pins
Hardware response ports JTAG Hardware response ports

xCORE logical core xCORE logical core

xCORE logical core xCORE logical core
xCORE logical core xCORE logical core
xCONNECT Switch

xCORE logical core xCORE logical core FLASH

xCORE logical core xCORE logical core

xCORE logical core xCORE logical core
Figure 1:
xCORE logical core xCORE logical core
XEF216-512-
xCORE logical core xCORE logical core
FB236 block
Link 8

diagram USB SRAM OTP OTP SRAM RGMII

Key features of the XEF216-512-FB236 include:

· Tiles: Devices consist of one or more xCORE tiles. Each tile contains between five and
eight 32-bit xCOREs with highly integrated I/O and on-chip memory.

· Logical cores Each logical core can execute tasks such as computational code, DSP
code, control software (including logic decisions and executing a state machine) or
software that handles I/O. Section 6.1

· xTIME scheduler The xTIME scheduler performs functions similar to an RTOS, in hard-
ware. It services and synchronizes events in a core, so there is no requirement for in-
terrupt handler routines. The xTIME scheduler triggers cores on events generated by
hardware resources such as the I/O pins, communication channels and timers. Once
triggered, a core runs independently and concurrently to other cores, until it pauses to
wait for more events. Section 6.2

· Channels and channel ends Tasks running on logical cores communicate using chan-
nels formed between two channel ends. Data can be passed synchronously or asyn-
chronously between the channel ends assigned to the communicating tasks. Section
6.5

· xCONNECT Switch and Links Between tiles, channel communications are implemented
over a high performance network of xCONNECT Links and routed through a hardware
xCONNECT Switch. Section 6.6

2
 XEF216-512-FB236 Datasheet

· Ports The I/O pins are connected to the processing cores by Hardware Response
ports. The port logic can drive its pins high and low, or it can sample the value on
its pins optionally waiting for a particular condition. Section 6.3

· Clock blocks xCORE devices include a set of programmable clock blocks that can be
used to govern the rate at which ports execute. Section 6.4

· Memory Each xCORE Tile integrates a bank of SRAM for instructions and data, and
a block of one-time programmable (OTP) memory that can be configured for system
wide security features. Section 9

· PLL The PLL is used to create a high-speed processor clock given a low speed external
oscillator. Section 7

· USB The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go
functionality. Data is communicated through ports on the digital node. A library is
provided to implement USB device functionality. Section 10

· RGMII The device has a set of pins that can be dedicated to communicate with an
RGMII, including Gbit Ethernet PHYs, according to the RGMII v1.3 specification. Sec-
tion 11

· Flash The device has a built-in 2MBflash. Section 8

· JTAG The JTAG module can be used for loading programs, boundary scan testing,
in-circuit source-level debugging and programming the OTP memory. Section 12

1.1 Software

Devices are programmed using C, C++ or xC (C with multicore extensions). XMOS pro-
vides tested and proven software libraries, which allow you to quickly add interface and
processor functionality such as USB, Ethernet, PWM, graphics driver, and audio EQ to
your applications.

1.2 xTIMEcomposer Studio

The xTIMEcomposer Studio development environment provides all the tools you need to
write and debug your programs, profile your application, and write images into flash mem-
ory or OTP memory on the device. Because xCORE devices operate deterministically,
they can be simulated like hardware within xTIMEcomposer: uniquely in the embedded
world, xTIMEcomposer Studio therefore includes a static timing analyzer, cycle-accurate
simulator, and high-speed in-circuit instrumentation.

xTIMEcomposer can be driven from either a graphical development environment, or the

command line. The tools are supported on Windows, Linux and MacOS X and available
at no cost from xmos.ai/software-tools.

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 XEF216-512-FB236 Datasheet

2 XEF216-512-FB236 Features
· Multicore Microcontroller with Advanced Multi-Core RISC Architecture
• 16 real-time logical cores on 2 xCORE tiles
• Cores share up to 1000 MIPS
— Up to 2000 MIPS in dual issue mode
• Each logical core has:
— Guaranteed throughput of between 1/5 and 1/8 of tile MIPS
— 16x32bit dedicated registers
• 167 high-density 16/32-bit instructions
— All have single clock-cycle execution (except for divide)
— 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic functions
· USB PHY, fully compliant with USB 2.0 specification
· RGMII support, compliant with RGMII v1.3 specification
· Programmable I/O
• 128 general-purpose I/O pins, configurable as input or output
— Up to 32 x 1bit port, 12 x 4bit port, 8 x 8bit port, 4 x 16bit port, 2 x 32bit port
— 8 xCONNECT links
• Port sampling rates of up to 60 MHz with respect to an external clock
• 64 channel ends (32 per tile) for communication with other cores, on or off-chip
· Memory
• 512KB internal single-cycle SRAM (max 256KB per tile) for code and data storage
• 16KB internal OTP (max 8KB per tile) for application boot code
• 2MB internal flash for application code and overlays
· Hardware resources
• 12 clock blocks (6 per tile)
• 20 timers (10 per tile)
• 8 locks (4 per tile)
· JTAG Module for On-Chip Debug
· Security Features
• Programming lock disables debug and prevents read-back of memory contents
• AES bootloader ensures secrecy of IP held on external flash memory
· Ambient Temperature Range
• -40 °C to 85 °C
· Speed Grade
• 24: 1200 MIPS
• 20: 1000 MIPS
· Power Consumption
• 570 mA (typical)
· 236-pin FBGA package 0.5 mm pitch

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 XEF216-512-FB236 Datasheet

3 Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

4F 4F 8D 4F
A GND VDDIOL VDDIOL TCK CLK X1D31 X1D29 X1D41 OTP_ NC MODE[0] X0D29 VDDIOR GND
rx1 rx_ctl tx2
VCC

1M 4E 4E 4F 4E 8D 4E 4E
B X0D36 VDDIOL VDDIOL TDO TMS TRST_ X1D33 X1D32 X1D28 X1D26 X1D42 OTP_ NC NC MODE[1] X0D33 X0D32 VDDIOR VDDIOR
N rx3 rx2 rx_clk tx_clk tx1
VCC

1N 1O 1C 1D 4F 4E 8D 8D 4F 4F 4F 4E 4E
C X0D37 X0D38 VDDIOL TDI DEBUG_ RST_N X1D10 X1D11 X1D30 X1D27 X1D43 X1D40 NC NC X0D31 X0D30 X0D28 X0D26 X0D27
X0 Li40 X0 Li30
N rx0 tx_ctl tx0 tx3 X0 Lo3 X0 Lo4
7 7

1P 8D 1K 1L
D X0D39 X0D40 X0D34 X0D35
X0 Li20 X0 Li10 X0 Lo1
7 X0 Lo2
7

8D 8D 8D 1J 1I 1B
E X0D43 X0D42 X0D41 X0D25 X0D24 X1D01
X0 Lo1
0 X0 Lo0
0 X0 Li00 X0 Lo0
7 X0 Li07 X0 Li17

1K 1L 1M 4A 4A 1A
F X1D34 X1D35 X1D36 NC VDD VDD VDDIOT VDD VDD PLL_ PLL_ X1D08 X1D09 X1D00
X0 Lo2 X0 Lo3 X0 Lo4
AVDD AGND X0 Li47 X0 Li37 X0 Li27
0 0 0

32A 32A 32A 32A

G X1D49 X1D50 VDD GND GND GND VDD X0D69 X0D70
X0 Li41 X0 Li31 X0 Lo3
6 X0 Lo4
6

32A 32A 32A 32A 32A 32A

H X1D53 X1D52 X1D51 VDD GND GND GND GND GND GND GND VDD X0D68 X0D67 X0D66
X0 Li01 X0 Li11 X0 Li21 X0 Lo2
6 X0 Lo1
6 X0 Lo0
6

32A 32A 32A 32A 32A 32A

J X1D54 X1D55 X1D56 VDD GND GND GND VDD X0D63 X0D64 X0D65
X0 Lo0
1 X0 Lo1
1 X0 Lo2
1 X0 Li26 X0 Li16 X0 Li06

32A 32A 32A 32A

K X1D58 X1D57 VDD GND GND GND GND GND GND GND VDD X0D62 X0D61
X0 Lo4
1 X0 Lo3
1 X0 Li36 X0 Li46

32A 32A 32A 32A 32A 32A

L X1D63 X1D62 X1D61 VDD GND GND GND VDD X0D58 X0D57 X0D56
X0 Li22 X0 Li32 X0 Li42 X0 Lo4
5 X0 Lo3
5 X0 Lo2
5

32A 32A 32A 32A 32A 32A

M X1D64 X1D65 X1D66 VDD GND GND GND GND GND GND GND VDD X0D53 X0D54 X0D55
X0 Li12 X0 Li02 X0 Lo0
2 X0 Li05 X0 Lo0
5 X0 Lo1
5

32A 32A 32A 32A

N X1D67 X1D68 VDD GND GND GND VDD X0D51 X0D52
X0 Lo1
2 X0 Lo2
2 X0 Li25 X0 Li15

32A 32A 1N 4B 32A 32A

P X1D70 X1D69 X1D37 VDD VDD VDD USB_ USB_ VDD VDD VDD NC X1D07 X0D50 X0D49
X0 Lo4 X0 Lo3 X0 Li43
VDD VDD X0 Lo4 X0 Li35 X0 Li45
2 2 4

1O 1P 4D 4A 4B 4B
R X1D38 X1D39 X1D17 X1D03 X1D05 X1D06
X0 Li33 X0 Li23 X0 Li03 X0 Lo0
4 X0 Lo2
4 X0 Lo3
4

4D 4D 4A 4B
T X1D16 X1D18 X1D02 X1D04
X0 Li13 X0 Lo0
3 X0 Li04 X0 Lo1
4

1C 1B 4D 1A 1D 4B 1E 1I 1G 1F 1H 4D 4D 4D
U X0D10 X0D01 X1D19 X0D00 X0D11 X0D07 X1D12 USB_ USB_ USB_ USB_ NC X1D24 X0D22 X0D13 X0D23 X0D19 X0D18 X0D17
X0 Lo3 X0 Lo2 X0 Lo1
VDD33 VBUS ID VSSAC X0 Li14 X0 Li24 X0 Li34
3 3 3

1G 4B 4B 4A 4A 4A 4C 4C 1J 4C 4C 1E 4D
V X1D22 VDDIOL VDDIOL X0D04 X0D06 X0D03 X0D08 X0D09 USB_ USB_ X1D21 X1D14 X1D25 X0D21 X0D14 X0D12 VDDIOR VDDIOR X0D16
X0 Lo4
DM DP X0 Li44
3

1H 4B 4A 1F 4C 4C 4C 4C
W GND VDDIOL X1D23 X0D05 X0D02 USB_
X1D13 RTUNE X1D20 X1D15 X0D20 X0D15 VDDIOR VDDIOR GND

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 XEF216-512-FB236 Datasheet

4 Signal Description
This section lists the signals and I/O pins available on the XEF216-512-FB236. The device
provides a combination of 1bit, 4bit, 8bit and 16bit ports, as well as wider ports that are
fully or partially (gray) bonded out. All pins of a port provide either output or input, but
signals in different directions cannot be mapped onto the same port.

Pins may have one or more of the following properties:

· PD/PU: The IO pin has a weak pull-down or pull-up resistor. The resistor is enabled
during and after reset. Enabling a link or port that uses the pin disables the resistor.
Thereafter, the resistor can be enabled or disabled under software control. The resistor
is designed to ensure defined logic input state for unconnected pins. It should not be
used to pull external circuitry. Note that the resistors are highly non-linear and only a
maximum pull current is specified in Section 14.3.

· ST: The IO pin has a Schmitt Trigger on its input.

· IOL/IOT/IOR: The IO pin is powered from VDDIOL, VDDIOT, and VDDIOR respectively

Power pins (11)

Signal Function Type Properties
GND Digital ground GND
OTP_VCC OTP power supply PWR
PLL_AGND Analog ground for PLL PWR
PLL_AVDD Analog power for PLL PWR
USB_VDD Digital tile power PWR
USB_VDD33 USB Analog power PWR
USB_VSSAC USB analog ground GND
VDD Digital tile power PWR
VDDIOL Digital I/O power (left) PWR
VDDIOR Digital I/O power (right) PWR
VDDIOT Digital I/O power (top) PWR

JTAG pins (6)

Signal Function Type Properties
RST_N Global reset input, active low Input IOL, PU, ST
TCK Test clock Input IOL, PD, ST
TDI Test data input Input IOL, PU
TDO Test data output Output IOL, PD
TMS Test mode select Input IOL, PU
TRST_N Test reset input, active low Input IOL, PU, ST

6
 XEF216-512-FB236 Datasheet

I/O pins (128)

Signal Function Type Properties
X0D00 1A0 I/O IOL, PD
X0D01 X0 L32out 1B0 I/O— IOL, PD
X0D02 4A0 8A0 16A0 32A20 I/O IOL, PD
X0D03 4A1 8A1 16A1 32A21 I/O IOL, PD
X0D04 4B0 8A2 16A2 32A22 I/O— IOL, PD
X0D05 4B1 8A3 16A3 32A23 I/O— IOL, PD
X0D06 4B2 8A4 16A4 32A24 I/O— IOL, PD
X0D07 4B3 8A5 16A5 32A25 I/O— IOL, PD
X0D08 4A2 8A6 16A6 32A26 I/O IOL, PD
X0D09 4A3 8A7 16A7 32A27 I/O IOL, PD
X0D10 X0 L33out 1C0 I/O— IOL, PD
X0D11 1D0 I/O IOL, PD
X0D12 1E0 I/O IOR, PD
X0D13 1F0 I/O IOR, PD
X0D14 4C0 8B0 16A8 32A28 I/O IOR, PD
X0D15 4C1 8B1 16A9 32A29 I/O IOR, PD
X0D16 X0 L44in 4D0 8B2 16A10 I/O IOR, PD
X0D17 X0 L43in 4D1 8B3 16A11 I/O IOR, PD
X0D18 X0 L42in 4D2 8B4 16A12 I/O IOR, PD
X0D19 X0 L41in 4D3 8B5 16A13 I/O IOR, PD
X0D20 4C2 8B6 16A14 32A30 I/O IOR, PD
X0D21 4C3 8B7 16A15 32A31 I/O IOR, PD
X0D22 1G0 I/O IOR, PD
X0D23 1H0 I/O IOR, PD
X0D24 X0 L70in 1I0 I/O IOR, PD
X0D25 X0 L70out 1J0 I/O IOR, PD
X0D26 X0 L73out 4E0 8C0 16B0 I/O IOR, PD
X0D27 X0 L74out 4E1 8C1 16B1 I/O IOR, PD
X0D28 4F0 8C2 16B2 I/O IOR, PD
X0D29 4F1 8C3 16B3 I/O IOR, PD
X0D30 4F2 8C4 16B4 I/O IOR, PD
X0D31 4F3 8C5 16B5 I/O IOR, PD
X0D32 4E2 8C6 16B6 I/O IOR, PD
X0D33 4E3 8C7 16B7 I/O IOR, PD
X0D34 X0 L71out 1K0 I/O IOR, PD
X0D35 X0 L72out 1L0 I/O IOR, PD
X0D36 1M0 8D0 16B8 I/O IOL, PD
X0D37 X0 L04in 1N0 8D1 16B9 I/O IOL, PD
X0D38 X0 L03in 1O0 8D2 16B10 I/O IOL, PD
X0D39 X0 L02in 1P0 8D3 16B11 I/O IOL, PD
X0D40 X0 L01in 8D4 16B12 I/O IOL, PD
(continued)

7
 XEF216-512-FB236 Datasheet

Signal Function Type Properties

X0D41 X0 L00in 8D5 16B13 I/O IOL, PD
X0D42 X0 L00out 8D6 16B14 I/O IOL, PD
X0D43 X0 L01out 8D7 16B15 I/O IOL, PD
X0D49 X0 L54in 32A0 I/O IOR, PD
X0D50 X0 L53in 32A1 I/O IOR, PD
X0D51 X0 L52in 32A2 I/O IOR, PD
X0D52 X0 L51in 32A3 I/O IOR, PD
X0D53 X0 L50in 32A4 I/O IOR, PD
X0D54 X0 L50out 32A5 I/O IOR, PD
X0D55 X0 L51out 32A6 I/O IOR, PD
X0D56 X0 L52out 32A7 I/O IOR, PD
X0D57 X0 L53out 32A8 I/O IOR, PD
X0D58 X0 L54out 32A9 I/O IOR, PD
X0D61 X0 L64in 32A10 I/O IOR, PD
X0D62 X0 L63in 32A11 I/O IOR, PD
X0D63 X0 L62in 32A12 I/O IOR, PD
X0D64 X0 L61in 32A13 I/O IOR, PD
X0D65 X0 L60in 32A14 I/O IOR, PD
X0D66 X0 L60out 32A15 I/O IOR, PD
X0D67 X0 L61out 32A16 I/O IOR, PD
X0D68 X0 L62out 32A17 I/O IOR, PD
X0D69 X0 L63out 32A18 I/O IOR, PD
X0D70 X0 L64out 32A19 I/O IOR, PD
X1D00 X0 L72in 1A0 I/O IOR, PD
X1D01 X0 L71in 1B0 I/O IOR, PD
X1D02 X0 L40in 4A0 8A0 16A0 32A20 I/O IOR, PD
X1D03 X0 L40out 4A1 8A1 16A1 32A21 I/O IOR, PD
X1D04 X0 L41out 4B0 8A2 16A2 32A22 I/O IOR, PD
X1D05 X0 L42out 4B1 8A3 16A3 32A23 I/O IOR, PD
X1D06 X0 L43out 4B2 8A4 16A4 32A24 I/O IOR, PD
X1D07 X0 L44out 4B3 8A5 16A5 32A25 I/O IOR, PD
X1D08 X0 L74in 4A2 8A6 16A6 32A26 I/O IOR, PD
X1D09 X0 L73in 4A3 8A7 16A7 32A27 I/O IOR, PD
X1D10 1C0 I/O IOT, PD
X1D11 1D0 I/O IOT, PD
X1D12 1E0 I/O IOL, PD
X1D13 1F0 I/O IOL, PD
X1D14 4C0 8B0 16A8 32A28 I/O IOR, PD
X1D15 4C1 8B1 16A9 32A29 I/O IOR, PD
X1D16 X0 L31in 4D0 8B2 16A10 I/O IOL, PD
X1D17 X0 L30in 4D1 8B3 16A11 I/O IOL, PD
X1D18 X0 L30out 4D2 8B4 16A12 I/O IOL, PD
X1D19 X0 L31out 4D3 8B5 16A13 I/O IOL, PD
(continued)

8
 XEF216-512-FB236 Datasheet

Signal Function Type Properties

X1D20 4C2 8B6 16A14 32A30 I/O IOR, PD
X1D21 4C3 8B7 16A15 32A31 I/O IOR, PD
X1D22 X0 L34out 1G0 I/O IOL, PD
X1D23 1H0 I/O IOL, PD
X1D24 1I0 I/O IOR, PD
X1D25 1J0 I/O IOR, PD
X1D26 tx_clk (rgmii) 4E0 8C0 16B0 I/O IOT, PD
X1D27 tx_ctl (rgmii) 4E1 8C1 16B1 I/O IOT, PD
X1D28 rx_clk (rgmii) 4F0 8C2 16B2 I/O IOT, PD
X1D29 rx_ctl (rgmii) 4F1 8C3 16B3 I/O IOT, PD
X1D30 rx0 (rgmii) 4F2 8C4 16B4 I/O IOT, PD
X1D31 rx1 (rgmii) 4F3 8C5 16B5 I/O IOT, PD
X1D32 rx2 (rgmii) 4E2 8C6 16B6 I/O IOT, PD
X1D33 rx3 (rgmii) 4E3 8C7 16B7 I/O IOT, PD
X1D34 X0 L02out 1K0 I/O IOL, PD
X1D35 X0 L03out 1L0 I/O IOL, PD
X1D36 X0 L04out 1M0 8D0 16B8 I/O IOL, PD
X1D37 X0 L34in 1N0 8D1 16B9 I/O IOL, PD
X1D38 X0 L33in 1O0 8D2 16B10 I/O IOL, PD
X1D39 X0 L32in 1P0 8D3 16B11 I/O IOL, PD
X1D40 tx3 (rgmii) 8D4 16B12 I/O IOT, PD
X1D41 tx2 (rgmii) 8D5 16B13 I/O IOT, PD
X1D42 tx1 (rgmii) 8D6 16B14 I/O IOT, PD
X1D43 tx0 (rgmii) 8D7 16B15 I/O IOT, PD
X1D49 X0 L14in 32A0 I/O IOL, PD
X1D50 X0 L13in 32A1 I/O IOL, PD
X1D51 X0 L12in 32A2 I/O IOL, PD
X1D52 X0 L11in 32A3 I/O IOL, PD
X1D53 X0 L10in 32A4 I/O IOL, PD
X1D54 X0 L10out 32A5 I/O IOL, PD
X1D55 X0 L11out 32A6 I/O IOL, PD
X1D56 X0 L12out 32A7 I/O IOL, PD
X1D57 X0 L13out 32A8 I/O IOL, PD
X1D58 X0 L14out 32A9 I/O IOL, PD
X1D61 X0 L24in 32A10 I/O IOL, PD
X1D62 X0 L23in 32A11 I/O IOL, PD
X1D63 X0 L22in 32A12 I/O IOL, PD
X1D64 X0 L21in 32A13 I/O IOL, PD
X1D65 X0 L20in 32A14 I/O IOL, PD
X1D66 X0 L20out 32A15 I/O IOL, PD
X1D67 X0 L21out 32A16 I/O IOL, PD
X1D68 X0 L22out 32A17 I/O IOL, PD
X1D69 X0 L23out 32A18 I/O IOL, PD
(continued)

9
 XEF216-512-FB236 Datasheet

Signal Function Type Properties

X1D70 X0 L24out 32A19 I/O IOL, PD

System pins (3)

Signal Function Type Properties
CLK PLL reference clock Input IOL, PD, ST
DEBUG_N Multi-chip debug, active low I/O IOL, PU
MODE[1:0] Boot mode select Input PU

usb pins (5)

Signal Function Type Properties
USB_DM USB Data- I/O
USB_DP USB Data+ I/O
USB_ID USB Identification I/O
USB_RTUNE USB resistor I/O
USB_VBUS USB Power Detect Pin I/O

10
 XEF216-512-FB236 Datasheet

5 Example Application Diagram

JACK /
MAGNETIC

IN 2V5 OUT

IN 1V0 OUT
RGMII
PHY

IN 3V3
OUT

RESET
SUPERVISOR

VDD

VDDIOT
USB_VDD

X1D11
X1D10
X1D33
X1D32
X1D31
X1D30
X1D29
X1D28
X1D27
X1D26
X1D43
X1D42
X1D41
X1D40
PLL_AVDD

PLL_AGND
RST_N
TRST_N
OSCILLATOR
CLK
25
24 MHz
X0D01 XnDnn GPIO
OTP_VCC
xCORE200

VDDIOL

VDDIOR
USB_RTUNE

USB_VBUS

USB_DM
USB_DP

USB_ID

USB_VDD33
GND
Figure 2:
Simplified
Reference
Schematic USB

· see Section 10 for details on the USB PHY

· see Section 11 for details on RGMII integration

· see Section 13 for details on the power supplies and PCB design

11
 XEF216-512-FB236 Datasheet

6 Product Overview
The XEF216-512-FB236 is a powerful device that consists of two xCORE Tiles, each com-
prising a flexible logical processing cores with tightly integrated I/O and on-chip memory.

6.1 Logical cores

Each tile has 8 active logical cores, which issue instructions down a shared five-stage
pipeline. Instructions from the active cores are issued round-robin. If up to five logical
cores are active, each core is allocated a fifth of the processing cycles. If more than five
logical cores are active, each core is allocated at least 1/n cycles (for n cores). Figure 3
shows the guaranteed core performance depending on the number of cores used.

Figure 3: Speed MIPS Frequency Minimum MIPS per core (for n cores)
Logical core grade 1 2 3 4 5 6 7 8
performance
10 1000 MIPS 500 MHz 100 100 100 100 100 83 71 63

There is no way that the performance of a logical core can be reduced below these pre-
dicted levels (unless priority threads are used: in this case the guaranteed minimum per-
formance is computed based on the number of priority threads as defined in the architec-
ture manual). Because cores may be delayed on I/O, however, their unused processing
cycles can be taken by other cores. This means that for more than five logical cores,
the performance of each core is often higher than the predicted minimum but cannot be
guaranteed.

The logical cores are triggered by events instead of interrupts and run to completion. A
logical core can be paused to wait for an event.

6.2 xTIME scheduler

The xTIME scheduler handles the events generated by xCORE Tile resources, such as
channel ends, timers and I/O pins. It ensures that all events are serviced and synchro-
nized, without the need for an RTOS. Events that occur at the I/O pins are handled by the
Hardware-Response ports and fed directly to the appropriate xCORE Tile. An xCORE Tile
can also choose to wait for a specified time to elapse, or for data to become available on
a channel.

Tasks do not need to be prioritised as each of them runs on their own logical xCORE. It
is possible to share a set of low priority tasks on a single core using cooperative multi-
tasking.

6.3 Hardware Response Ports

Hardware Response ports connect an xCORE tile to one or more physical pins and as
such define the interface between hardware attached to the XEF216-512-FB236, and the
software running on it. A combination of 1bit, 4bit, 8bit, 16bit and 32bit ports are available.
All pins of a port provide either output or input. Signals in different directions cannot be
mapped onto the same port.

12
 XEF216-512-FB236 Datasheet

reference clock clock port

clock
block
readyOut readyIn port

port counter
conditional port
value logic
stamp/time
PORT
FIFO
port transfer
PINS SERDES CORE
value register

Figure 4:
Port block output (drive) input (sample)
diagram

The port logic can drive its pins high or low, or it can sample the value on its pins, option-
ally waiting for a particular condition. Ports are accessed using dedicated instructions
that are executed in a single processor cycle. xCORE200 IO pins can be used as open
collector outputs, where signals are driven low if a zero is output, but left high impedance
if a one is output. This option is set on a per-port basis.

Data is transferred between the pins and core using a FIFO that comprises a SERDES
and transfer register, providing options for serialization and buffered data.

Each port has a 16-bit counter that can be used to control the time at which data is trans-
ferred between the port value and transfer register. The counter values can be obtained
at any time to find out when data was obtained, or used to delay I/O until some time in
the future. The port counter value is automatically saved as a timestamp, that can be
used to provide precise control of response times.

The ports and xCONNECT links are multiplexed onto the physical pins. If an xConnect
Link is enabled, the pins of the underlying ports are disabled. If a port is enabled, it
overrules ports with higher widths that share the same pins. The pins on the wider port
that are not shared remain available for use when the narrower port is enabled. Ports
always operate at their specified width, even if they share pins with another port.

6.4 Clock blocks

xCORE devices include a set of programmable clocks called clock blocks that can be
used to govern the rate at which ports execute. Each xCORE tile has six clock blocks:
the first clock block provides the tile reference clock and runs at a default frequency of
100MHz; the remaining clock blocks can be set to run at different frequencies.

A clock block can use a 1-bit port as its clock source allowing external application clocks
to be used to drive the input and output interfaces. xCORE200 clock blocks optionally
divide the clock input from a 1-bit port.

13
 XEF216-512-FB236 Datasheet

100MHz
reference 1-bit port
clock ... ...

divider
readyIn

Figure 5: clock block

Clock block
diagram port counter

In many cases I/O signals are accompanied by strobing signals. The xCORE ports can
input and interpret strobe (known as readyIn and readyOut) signals generated by external
sources, and ports can generate strobe signals to accompany output data.

On reset, each port is connected to clock block 0, which runs from the xCORE Tile refer-
ence clock.

6.5 Channels and Channel Ends

Logical cores communicate using point-to-point connections, formed between two chan-
nel ends. A channel-end is a resource on an xCORE tile, that is allocated by the program.
Each channel-end has a unique system-wide identifier that comprises a unique number
and their tile identifier. Data is transmitted to a channel-end by an output-instruction;
and the other side executes an input-instruction. Data can be passed synchronously or
asynchronously between the channel ends.

6.6 xCONNECT Switch and Links

XMOS devices provide a scalable architecture, where multiple xCORE devices can be con-
nected together to form one system. Each xCORE device has an xCONNECT interconnect
that provides a communication infrastructure for all tasks that run on the various xCORE
tiles on the system.

The interconnect relies on a collection of switches and XMOS links. Each xCORE device
has an on-chip switch that can set up circuits or route data. The switches are connected
by xConnect Links. An XMOS link provides a physical connection between two switches.
The switch has a routing algorithm that supports many different topologies, including
lines, meshes, trees, and hypercubes.

The links operate in either 2 wires per direction or 5 wires per direction mode, depending
on the amount of bandwidth required. Circuit switched, streaming and packet switched
data can both be supported efficiently. Streams provide the fastest possible data rates
between xCORE Tiles (up to 250 MBit/s), but each stream requires a single link to be
reserved between switches on two tiles. All packet communications can be multiplexed
onto a single link.

14
 XEF216-512-FB236 Datasheet

xCONNECT Link to another device switch

CORE CORE CORE CORE

CORE CORE CORE

CORE
xCONNECT
CORE CORE switch CORE

CORE
Figure 6: CORE
CORE CORE CORE
Switch, links
and channel
ends xCORE Tile xCORE Tile

Information on the supported routing topologies that can be used to connect multiple de-
vices together can be found in the XS1-UEF Link Performance and Design Guide, X2999.

7 PLL
The PLL creates a high-speed clock that is used for the switch, tile, and reference clock.
The PLL multiplication value is selected through the two MODE pins, and can be changed
by software to speed up the tile or use less power. The MODE pins are set as shown in
Figure 7:

Oscillator MODE Tile Boot PLL Ratio PLL settings

Frequency 1 0 Frequency OD F R
Figure 7: 3.25-10 MHz 0 0 130-400 MHz 40 1 159 0
PLL multiplier 9-25 MHz 1 1 144-400 MHz 16 1 63 0
values and 25-50 MHz 1 0 167-400 MHz 8 1 31 0
MODE pins
50-100 MHz 0 1 196-400 MHz 4 1 15 0

Figure 7 also lists the values of OD, F and R, which are the registers that define the ratio
of the tile frequency to the oscillator frequency:
F +1 1 1
Fcore = Fosc × × ×
2 R+1 OD + 1
OD, F and R must be chosen so that 0 ≤ R ≤ 63, 0 ≤ F ≤ 4095, 0 ≤ OD ≤ 7, and
260M Hz ≤ Fosc × F 2+1 × R+1 1
≤ 1.3GHz. The OD, F , and R values can be modified
by writing to the digital node PLL configuration register.

The MODE pins must be held at a static value during and after deassertion of the system
reset. If the USB PHY is used, then either a 24 MHz or 12 MHz oscillator must be used.

15
 XEF216-512-FB236 Datasheet

If a different tile frequency is required (eg, 500 MHz), then the PLL must be reprogrammed
after boot to provide the required tile frequency. The XMOS tools perform this operation
by default. Further details on configuring the clock can be found in the xCORE-200 Clock
Frequency Control document.

8 Boot Procedure
The device is kept in reset by driving RST_N low. When in reset, all GPIO pins have a pull-
down enabled. The processor must be held in reset until VDDIOL is in spec for at least
1 ms. When the device is taken out of reset by releasing RST_N the processor starts
its internal reset process. After 15-150 µs (depending on the input clock) the processor
boots.

The device boots from a QSPI flash (IS25LP016D) that is embedded in the device. The
QSPI flash is connected to the ports on Tile 0 as shown in Figure 8. An external 1K
resistor must connect X0D01 to VDDIOL. X0D10 should ideally not be connected. If
X0D10 is connected, then a 150 ohm series resistor close to the device is recommended.
X0D04..X0D07 should be not connected.
VDDIOL
xCORE

1K X0D04..7 PORT_4B
X0D01 PORT_1B
X0D10
PORT_1C
CLK
D[0..3]
CS_N

Figure 8:
QSPI port QSPI Flash
connectivity

The xCORE Tile boot procedure is illustrated in Figure 9. If bit 5 of the security register
(see §9.1) is set, the device boots from OTP. Otherwise, the device boots from the internal
flash.

Start

Boot ROM Primary boot

No
Security Register Bit [5] set

Yes

Copy OTP contents Copy flash contents

OTP
to base of SRAM to base of SRAM
Figure 9:
Boot
procedure Execute program Execute program

16
 XEF216-512-FB236 Datasheet

The boot image has the following format:

· A 32-bit program size s in words.

· Program consisting of s × 4 bytes.

· A 32-bit CRC, or the value 0x0D15AB1E to indicate that no CRC check should be per-
formed.

The program size and CRC are stored least significant byte first. The program is loaded
into the lowest memory address of RAM, and the program is started from that address.
The CRC is calculated over the byte stream represented by the program size and the
program itself. The polynomial used is 0xEDB88320 (IEEE 802.3); the CRC register is
initialized with 0xFFFFFFFF and the residue is inverted to produce the CRC.

8.1 Security register

The security register enables security features on the xCORE tile. The features shown in
Figure 10 provide a strong level of protection and are sufficient for providing strong IP
security.

Feature Bit Description

The JTAG interface is disabled, making it impossible for the
tile state or memory content to be accessed via the JTAG
Disable JTAG 0 interface.
Other tiles are forbidden access to the processor state via the
system switch. Disabling both JTAG and Link access trans-
forms an xCORE Tile into a “secure island” with other tiles free
Disable Link access 1 for non-secure user application code.
The xCORE Tile is forced to boot from address 0 of the OTP,
Secure Boot 5 allowing the xCORE Tile boot ROM to be bypassed (see §8).
Redundant rows 7 Enables redundant rows in OTP.
Sector Lock 0 8 Disable programming of OTP sector 0.
Sector Lock 1 9 Disable programming of OTP sector 1.
Sector Lock 2 10 Disable programming of OTP sector 2.
Sector Lock 3 11 Disable programming of OTP sector 3.
Disable OTP programming completely: disables updates to
OTP Master Lock 12 all sectors and security register.
Disable all (read & write) access from the JTAG interface to
Disable JTAG-OTP 13 this OTP.
Disable Global Debug 14 Disables access to the DEBUG_N pin.
Figure 10: General purpose software accessable security register avail-
Security 21..15 able to end-users.
register
General purpose user programmable JTAG UserID code ex-
features
31..22 tension.

9 Memory

17
 XEF216-512-FB236 Datasheet

9.1 OTP
Each xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with a
security register that configures system wide security features. The OTP holds data in
four sectors each containing 512 rows of 32 bits which can be used to implement se-
cure bootloaders and store encryption keys. Data for the security register is loaded from
the OTP on power up. All additional data in OTP is copied from the OTP to SRAM and
executed first on the processor.

The OTP memory is programmed using three special I/O ports: the OTP address port
is a 16-bit port with resource ID 0x100200, the OTP data is written via a 32-bit port with
resource ID 0x200100, and the OTP control is on a 16-bit port with ID 0x100300. Pro-
gramming is performed through libotp and xburn.

9.2 SRAM

Each xCORE Tile integrates a single 256KB SRAM bank for both instructions and data. All
internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte (8-bit),
half-word (16-bit) or word (32-bit) accesses are supported and are executed within one
tile clock cycle. There is no dedicated external memory interface, although data memory
can be expanded through appropriate use of the ports.

10 USB PHY
The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go function-
ality. The PHY is configured through a set of peripheral registers (Appendix F), and data is
communicated through ports on the digital node. A library, XUD, is provided to implement
USB-device functionality.

The USB PHY is connected to the ports on Tile 0 and Tile 1 as shown in Figure 11. When
the USB PHY is enabled on Tile 0, the ports shown can on Tile 0 only be used with the
USB PHY. When the USB PHY is enabled on Tile 1, then the ports shown can on Tile 1
only be used with the USB PHY. All other IO pins and ports are unaffected. The USB PHY
should not be enabled on both tiles. Two clock blocks can be used to clock the USB
ports. One clock block for the TXDATA path, and one clock block for the RXDATA path.
Details on how to connect those ports are documented in an application note on USB for
xCORE200.
3V3 1V0 3V3 1V0
Regulators USB xCORE
USB_VDD PHY
USB USB_VDD33 PORT_8A TXDATA
connector TXD[0..7]
TXRDYOUT PORT_1K
1-10uF USB_VBUS
VBUS TXRDYIN PORT_1H CLKBLK
USB_DP
DP
USB_DM
DM CLK PORT_1J
USB_ID
ID
USB_RTUNE CLKBLK
GND RXRDY PORT_1I
43R2 RXD[0..7] PORT_8B RXDATA
Figure 11: FLAG0 PORT_1E FLAG0
FLAG1 PORT_1F FLAG1
Bus powered Please note:
ID connection is optional FLAG2 PORT_1G FLAG2
USB-device DM may be marked as DN

18
 XEF216-512-FB236 Datasheet

An external resistor of 43.2 ohm (1% tolerance) should connect USB_RTUNE to ground,
as close as possible to the device.

10.1 USB VBUS

USB_VBUS need not be connected if the device is wholly powered by USB, and the device
is used to implement a USB-device.

If you use the USB PHY to design a self-powered USB-device, then the device must be
able detect the presence of VBus on the USB connector (so the device can disconnect its
pull-up resistors from D+/D- to ensure the device does not have any voltage on the D+/D-
pins when VBus is not present, “USB Back Voltage Test”). This requires USB_VBUS to be
connected to the VBUS pin of the USB connector as is shown in Figure 12.
3V3 1V0 External Supply 3V3 1V0
Regulators 10K USB xCORE
USB_VDD PHY
USB USB_VDD33
connector 1-10 uF 47K 0.1 uF
USB_VBUS
VBUS
USB_DP
DP
USB_DM
DM
USB_ID
ID
USB_RTUNE
Figure 12: GND
Self powered 43R2
USB-device

When connecting a USB cable to the device it is possible an overvoltage transient will be
present on VBus due to the inductance of the USB cable combined with the required input
capacitor on VBus. The circuit in Figure 12 ensures that the transient does not damage
the device. The 10k series resistor and 0.1uF capacitor ensure than any input transient
is filtered and does not reach the device. The 47k resistor to ground is a bleeder resistor
to discharge the input capacitor when VBus is not present. The 1-10uF input capacitor is
required as part of the USB specification. A typical value would be 2.2uF to ensure the
1uF minimum requirement is met even under voltage bias conditions.

In any case, extra components (such as a ferrite bead and diodes) may be required for
EMC compliance and ESD protection. Different wiring is required for USB-host and USB-
OTG.

10.2 Logical Core Requirements

The XMOS XUD software component runs in a single logical core with endpoint and ap-
plication cores communicating with it via a combination of channel communication and
shared memory variables.

Each IN (host requests data from device) or OUT (data transferred from host to device)
endpoint requires one logical core.

11 RGMII
The device has a series of pins that are dedicated to communicate with an RGMII PHY, as
per the RGMII v1.3 spec. This can be used to communicate with GBit Ethernet PHYs. The

19
 XEF216-512-FB236 Datasheet

pins and functions are listed in Figure 13. When RGMII mode is enabled (using processor
status register 2) these pins can no longer be used as GPIO pins, and will instead be
driven directly from an RGMII block that provides DDR to SDR conversion, which in turn
is interfaced to a set of ports on Tile 1.

Pin RGMII Function

X1D40 TX3 Transmit bit 3
X1D41 TX2 Transmit bit 2
X1D42 TX1 Transmit bit 1
X1D43 TX0 Transmit bit 0
X1D26 TX_CLK Receive clock (125 MHz)
X1D27 TX_CTL Transmit data valid/error
X1D28 RX_CLK Receive clock (125 MHz)
X1D29 RX_CTL Receive data valid/error
X1D30 RX0 Receive bit 0
Figure 13: X1D31 RX1 Receive bit 1
RGMII block X1D32 RX2 Receive bit 2
pin functions
X1D33 RX3 Receive bit 3

The RGMII block is connected to the ports on Tile 1 as shown in Figure 14. When the
RGMII block is enabled, the ports shown can only be used with the RGMII block, and IO
pins X1D26..X1D33/X1D40..X1D43 can only be used with the RGMII block. Ports and pins
not used in Figure 14 can be used as normal.

The RGMII block generates a clock (configured using processor status register 2), and
has the facility to delay the outgoing clock edge, putting it out of phase with the data.
The RGMII block translates the double data-rate 4-wire data signals and 1-wire control
signal into single-data rate 8-wire TX and DX signals and two control signals. Figure 14
shows how four clock blocks can be used to clock the RGMII ports. One clock block
for the TXDATA path, one clock block for the RXDATA path, one clock block to delay the
TX_CLK, and one clock block clocked on a negative valid signal to enable mode switching
between 10/100/1000 speeds. Details on how to connect those ports are documented
in an application note on RGMII for xCORE200. The XMOS RGMII software component
runs a MAC layer on Tile 1.

The SMI interface should be connected to two one-bit ports that are configured as open-
drain IOs, using external pull-ups to 2.5V. Ports 1C and 1D are notionally allocated for this,
but any GPIO can be used for this purpose.

The bundles of RX and TX pins should be wired using matched trace-lengths over an
uninterrupted ground-plane. The RGMII pins are supplied through the VDDIOT supply
pins, which should be provided with 2.5V. Decouplers should be placed with a short path
to VDDIOT and ground. If the PHY supports a 3.3V IO voltage, then a 3.3V supply can be
used for VDDIOT.

The RGMII PHY should be configured so that RX_CLK is low during reset of the xCORE.
This may be achieved by putting a pull-down resistor on the reset of the PHY, keeping the
PHY in reset until the RGMII layer on the xCORE takes the PHY out of reset.

20
 XEF216-512-FB236 Datasheet

External xCore TIle 1

RGMII X1D11
PHY SMC PORT_1D SMC
X1D10 PORT_1C SMIO
SMIO
X1D40 RGMII
TX3 Block
X1D41 PORT_8B TXDATA
TX2 TXD0..7
X1D42
TX1 TXDV PORT_1F
X1D43
TX0 CLK PORT_1P CLKBLK
X1D26
TX_CLK TXCLK PORT_1G CLKBLK
X1D27
TX_CTL TXERR PORT_1E TXERROR
X1D28
RX_CLK RXERR PORT_1A RXERROR
X1D29
RX_CTL RXCLK PORT_1O
X1D30 CLKBLK
RX0 RXDV PORT_1B
Figure 14: X1D31
RX1 RXD0..7 PORT_8A RXDATA
RGMII port X1D32
PORT_1K CLKBLK
RX2
functions on RX3
X1D33
PORT_4E MODE
Tile 1

12 JTAG
The JTAG module can be used for loading programs, boundary scan testing, in-circuit
source-level debugging and programming the OTP memory.

BS TAP
TDI TDI TDO TDO

TCK
TMS
Figure 15: TRST_N
JTAG chain DEBUG_N
structure

The JTAG chain structure is illustrated in Figure 15. It comprises a single 1149.1 compliant
TAP that can be used for boundary scan of the I/O pins. It has a 4-bit IR and 32-bit DR.
It also provides access to a chip TAP that in turn can access the xCORE Tile for loading
code and debugging.

The TRST_N pin must be asserted low during and after power up for 100 ns. If JTAG is
not required, the TRST_N pin can be tied to ground to hold the JTAG module in reset.

The DEBUG_N pin is used to synchronize the debugging of multiple xCORE Tiles. This
pin can operate in both output and input mode. In output mode and when configured
to do so, DEBUG_N is driven low by the device when the processor hits a debug break
point. Prior to this point the pin will be tri-stated. In input mode and when configured to
do so, driving this pin low will put the xCORE Tile into debug mode. Software can set the

21
 XEF216-512-FB236 Datasheet

behavior of the xCORE Tile based on this pin. This pin should have an external pull up of
4K7-47K Ω or left not connected in single core applications.

The JTAG device identification register can be read by using the IDCODE instruction. Its
contents are specified in Figure 16.

Bit31 Device Identification Register Bit0

Figure 16:
Version Part Number Manufacturer Identity 1
IDCODE return 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 1
value
0 0 0 0 5 6 3 3

The JTAG usercode register can be read by using the USERCODE instruction. Its contents
are specified in Figure 17. The OTP User ID field is read from bits [22:31] of the security
register on xCORE Tile 0, see §9.1 (all zero on unprogrammed devices).

Bit31 Usercode Register Bit0

Figure 17:
OTP User ID Unused Silicon Revision
USERCODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
return value
0 0 0 2 8 0 0 0

13 Board Integration
The device has the following power supply pins:

· VDD pins for the xCORE Tile, including a USB_VDD pin that powers the USB PHY

· VDDIO pins for the I/O lines. Separate I/O supplies are provided for the left, top, and
right side of the package; different I/O voltages may be supplied on those. The sig-
nal description (Section 4) specifies which I/O is powered from which power-supply
VDDIOT powers the RGMII IO pins, and must be provided with 2.5V.

· PLL_AVDD pins for the PLL

· OTP_VCC pins for the OTP

· A USB_VDD33 pin for the analogue supply to the USB-PHY

Several pins of each type are provided to minimize the effect of inductance within the
package, all of which must be connected. The power supplies must be brought up mono-
tonically and input voltages must not exceed specification at any time.

VDDIO/OTP_VCC and VDD can ramp up independently. In order to reduce stresses on

the device, it is preferable to make them ramp up in a short time frame of each other, no
more than 50 ms apart. RST_N and TRST_N should be kept low until all power supplies
are stable and within tolerances of their final voltage. If your design is powered by VBUS,
then RST_N should go high within 10 ms of attaching to VBUS in order to ensure that USB
timings are met. RST_N should be at least 1 ms after VDDIO good to enable the built-in
flash to settle. Power sequencing is summarised in Figure 18

The PLL_AVDD supply should be separated from the other noisier supplies on the board.
The PLL requires a very clean power supply, and a low pass filter (for example, a 4.7 Ω
resistor and 100 nF multi-layer ceramic capacitor) is recommended on this pin.

22
 XEF216-512-FB236 Datasheet

Bring up System
in short dependent
succession timing
1.0
VDD
0
3.3
VDDIO,
V

OTP_VCC
Figure 18: 0
Sequencing of 3.3
power RST_N
supplies and 0
RST_N Time

The following ground pins are provided:

· PLL_AGND for PLL_AVDD

· GND for all other supplies

All ground pins must be connected directly to the board ground.

The VDD and VDDIO supplies should be decoupled close to the chip by several 100 nF low
inductance multi-layer ceramic capacitors between the supplies and GND (for example,
100nF 0402 for every other supply pin). The ground side of the decoupling capacitors
should have as short a path back to the GND pins as possible. A bulk decoupling capac-
itor of at least 10 uF should be placed on each of these supplies.

RST_N is an active-low asynchronous-assertion global reset signal. Following a reset,

the PLL re-establishes lock after which the device boots up according to the boot mode
(see §8). RST_N and must be asserted low during and after power up for 100 ns.

13.1 USB connections

USB_VBUS should be connected to the VBUS pin of the USB connector. A 2.2 uF capacitor
to ground is required on the VBUS pin. A ferrite bead may be used to reduce HF noise.

For self-powered systems, a bleeder resistor may be required to stop VBUS from floating
when no USB cable is attached.

USB_DP and USB_DN should be connected to the USB connector. USB_ID does not need
to be connected.

13.2 USB signal routing and placement

The USB_DP and USB_DN lines are the positive and negative data polarities of a high
speed USB signal respectively. Their high-speed differential nature implies that they must
be coupled and properly isolated. The board design must ensure that the board traces
for USB_DP and USB_DN are tightly matched. In addition, according to the USB 2.0 spec-
ification, the USB_DP and USB_DN differential impedance must be 90 Ω.

23
 XEF216-512-FB236 Datasheet

Figure 19:
USB trace
separation
showing a low Low-speed High-speed
speed signal, non-periodic periodic
signal USB_DP0 USB_DN0 USB_DP1 USB_DN1 signal
two
differential
pairs and a
high-speed 20 mils 3.9 mils 20 mils 3.9 mils 50 mils
clock (0.51mm) (0.10mm) (0.51mm) (0.10mm - calculated (1.27mm)
on the stack up)

13.2.1 General routing and placement guidelines

The following guidelines will help to avoid signal quality and EMI problems on high speed
USB designs. They relate to a four-layer (Signal, GND, Power, Signal) PCB.

0.12 mm 0.10 mm 0.12 mm

USB_DP USB_DN

0.1 mm

GND

1.0 mm
FR4 Dielectric

Power
Figure 20:
0.1 mm
Example USB
board stack

For best results, most of the routing should be done on the top layer (assuming the
USB connector and XEF216-512-FB236 are on the top layer) closest to GND. Reference
planes should be below the transmission lines in order to maintain control of the trace
impedance.

We recommend that the high-speed clock and high-speed USB differential pairs are routed
first before any other routing. When routing high speed USB signals, the following guide-
lines should be followed:

· High speed differential pairs should be routed together.

· High-speed USB signal pair traces should be trace-length matched. Maximum trace-
length mismatch should be no greater than 4mm.

· Ensure that high speed signals (clocks, USB differential pairs) are routed as far away
from off-board connectors as possible.

24
 XEF216-512-FB236 Datasheet

· High-speed clock and periodic signal traces that run parallel should be at least 1.27mm
away from USB_DP/USB_DN (see Figure 19).

· Low-speed and non-periodic signal traces that run parallel should be at least 0.5mm
away from USB_DP/USB_DN (see Figure 19).

· Route high speed USB signals on the top of the PCB wherever possible.

· Route high speed USB traces over continuous power planes, with no breaks. If a trade-
off must be made, changing signal layers is preferable to crossing plane splits.

· Follow the 20 × h rule; keep traces 20 × h (the height above the power plane) away
from the edge of the power plane.

· Use a minimum of vias in high speed USB traces.

· Avoid corners in the trace. Where necessary, rather than turning through a 90 degree
angle, use two 45 degree turns or an arc.

· DO NOT route USB traces near clock sources, clocked circuits or magnetic devices.

· Avoid stubs on high speed USB signals.

13.3 Land patterns and solder stencils

The package is a 236 ball Fine Ball Grid Array (FBGA) on a 0.5 mm pitch. We recommend
you use HDI or better PCB technology. The missing balls in the outer rows can be used
to route the first inner row out over the top layer. The missing balls in the center can be
used for ground vias. The missing rows four and five can be used for VDD vias if required.

The land patterns and solder stencils will depend on the PCB manufacturing process. We
recommend you design them with using the IPC specifications “Generic Requirements
for Surface Mount Design and Land Pattern Standards” IPC-7351B. This standard aims
to achieve desired targets of heel, toe and side fillets for solder-joints. The mechanical
drawings in Section 15 specify the dimensions and tolerances.

13.4 Ground and Thermal Vias

Vias from the ground balls into the ground plane of the PCB are recommended for a low
inductance ground connection and good thermal performance. Typical designs could
use 16 vias in a 4 x 4 grid, equally spaced amongst the ground balls.

13.5 Moisture Sensitivity

XMOS devices are, like all semiconductor devices, susceptible to moisture absorption.
When removed from the sealed packaging, the devices slowly absorb moisture from the
surrounding environment. If the level of moisture present in the device is too high during
reflow, damage can occur due to the increased internal vapour pressure of moisture.
Example damage can include bond wire damage, die lifting, internal or external package
cracks and/or delamination.

25
 XEF216-512-FB236 Datasheet

All XMOS devices are Moisture Sensitivity Level (MSL) 3 - devices have a shelf life of
168 hours between removal from the packaging and reflow, provided they are stored
below 30C and 60% RH. If devices have exceeded these values or an included moisture
indicator card shows excessive levels of moisture, then the parts should be baked as
appropriate before use. This is based on information from Joint IPC/JEDEC Standard
For Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface-Mount
Devices J-STD-020 Revision D.

26
 XEF216-512-FB236 Datasheet

14 Electrical Characteristics
14.1 Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent
damage to the device. Exposure to any Absolute Maximum Rating condition for extended
periods may affect device reliability and lifetime.

Symbol Parameter MIN MAX UNITS Notes

VDD Tile DC supply voltage -0.2 1.1 V
PLL_AVDD PLL analog supply -0.2 1.1 V
VDDIO I/O supply voltage -0.3 3.75 V
OTP_VCC OTP supply voltage -0.3 3.75 V
Tj Junction temperature 125 °C
Tstg Storage temperature -65 150 °C
V(Vin) Voltage applied to any IO pin -0.3 3.75 V
I(XxDxx) GPIO current -30 30 mA
V(X0D03-8) Voltage applied to flash pins -0.3 VDDIO+0.5 V
I(VDDIOL) Current for VDDIOL domain 588 mA A, B, C
I(VDDIOR) Current for VDDIOR domain 686 mA A, B, C
I(VDDIOT) Current for VDDIOT domain 98 mA A, C
USB_VDD USB tile DC supply voltage -0.2 1.1 V
USB_VDD33 USB tile analog supply voltage -0.3 3.75 V
Figure 21: USB_VBUS USB VBUS voltage -0.3 5.75 V
Absolute USB_DP USB DP voltage -0.3 5.5 V
maximum USB_DM USB DM voltage -0.3 5.5 V
ratings
USB_ID USB ID voltage -0.3 2.75 V
A Exceeding these current limits will result in premature aging and reduced lifetime.
B This current consumption must be evenly distributed over all VDDIO pins.
C All main power (VDD, VDDIO) and ground (VSS) pins must always be connected.

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 XEF216-512-FB236 Datasheet

14.2 Operating Conditions

Symbol Parameter MIN TYP MAX UNITS Notes
VDD Tile DC supply voltage 0.95 1.00 1.05 V
VDDIOL I/O supply voltage 3.135 3.30 3.465 V
VDDIOR I/O supply voltage 3.135 3.30 3.465 V
VDDIOT 3v3 I/O supply voltage 3.135 3.30 3.465 V
VDDIOT 2v5 I/O supply voltage 2.375 2.50 2.625 V
USB_VDD USB tile DC supply voltage 0.95 1.00 1.05 V
VDD33 Peripheral supply 3.135 3.30 3.465 V
PLL_AVDD PLL analog supply 0.95 1.00 1.05 V
Cl xCORE Tile I/O load capacitance 25 pF
Ambient operating temperature
() 0 70 °C
Figure 22: Ta
Ambient operating temperature
Operating () -40 85 °C
conditions
Tj Junction temperature 125 °C

14.3 DC Characteristics, VDDIO=3V3

Symbol Parameter MIN TYP MAX UNITS Notes

V(IH) Input high voltage 2.00 3.60 V A
V(IL) Input low voltage -0.30 0.70 V A
V(OH) Output high voltage 2.20 V B, C
V(OL) Output low voltage 0.40 V B, C
Figure 23: I(PU) Internal pull-up current (Vin=0V) -100 µA D
DC character- I(PD) Internal pull-down current (Vin=3.3V) 100 µA D
istics
I(LC) Input leakage current -10 10 µA
A All pins except power supply pins.
Pins X1D40, X1D41, X1D42, X1D43, X1D26, and X1D27 are nominal 8 mA drivers, the remainder of the
B general-purpose I/Os are 4 mA.
C Measured with 4 mA drivers sourcing 4 mA, 8 mA drivers sourcing 8 mA.
Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs should not be
used to pull external circuitry. In order to pull the pin to the opposite state, a 4K7 resistor is recommended to
D overome the internal pull current.

3.0 3.0
IO Pin Voltage, V

IO Pin Voltage, V

2.0 2.0
Figure 24:
Typical
1.0 1.0
internal
pull-down and
pull-up 0.0 0.0
0 20 40 60 80 100 -100 -80 -60 -40 -20 0
currents
I(PD) current, uA I(PU) current, uA

28
 XEF216-512-FB236 Datasheet

14.4 ESD Stress Voltage

Figure 25: Symbol Parameter MIN TYP MAX UNITS Notes

ESD stress HBM Human body model -2.00 2.00 KV
voltage
CDM Charged Device Model -500 500 V

14.5 Reset Timing

Symbol Parameters MIN TYP MAX UNITS Notes

Figure 26: T(RST) Reset pulse width 5 µs
Reset timing
T(INIT) Initialization time 150 µs A
A Shows the time taken to start booting after RST_N has gone high.

14.6 Power Consumption

Symbol Parameter MIN TYP MAX UNITS Notes

I(DDCQ) Quiescent VDD current 45 mA A, B, C
PD Tile power dissipation 325 µW/MIPS A, D, E, F
IDD Active VDD current 570 700 mA A, G
Figure 27: I(ADDPLL) PLL_AVDD current 5 7 mA H
xCORE Tile I(VDD33) VDD33 current 26.7 mA I
currents
I(USB_VDD) USB_VDD current 8.27 mA J
A Use for budgetary purposes only.
B Assumes typical tile and I/O voltages with no switching activity.
C Includes PLL current.
D Assumes typical tile and I/O voltages with nominal switching activity.
E Assumes 1 MHz = 1 MIPS.
F PD(TYP) value is the usage power consumption under typical operating conditions.
G Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 500 MHz, average device resource usage.
H PLL_AVDD = 1.0 V
HS mode transmitting while driving all 0’s data (constant JKJK on DP/DM). Loading of 10 pF. Transfers do not
I include any interpacket delay.
J HS receive mode; no traffic.

The tile power consumption of the device is highly application dependent and should be
used for budgetary purposes only.

More detailed power analysis can be found in the xCORE-200 Power Consumption doc-
ument,

29
 XEF216-512-FB236 Datasheet

14.7 Clock
Symbol Parameter MIN TYP MAX UNITS Notes
f Frequency 3.25 24 100 MHz
SR Slew rate 0.10 V/ns
Figure 28: TJ(LT) Long term jitter (pk-pk) 2 % A
Clock
f(MAX) Processor clock frequency 500 MHz B
A Percentage of CLK period.
B Assumes typical tile and I/O voltages with nominal activity.

Further details can be found in the xCORE-200 Clock Frequency Control document,

14.8 xCORE Tile I/O AC Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes
T(XOVALID) Input data valid window 8 ns
Figure 29: T(XOINVALID) Output data invalid window 9 ns
I/O AC charac-
Rate at which data can be sampled with
teristics
T(XIFMAX) respect to an external clock 60 MHz

The input valid window parameter relates to the capability of the device to capture data
input to the chip with respect to an external clock source. It is calculated as the sum of
the input setup time and input hold time with respect to the external clock as measured
at the pins. The output invalid window specifies the time for which an output is invalid
with respect to the external clock. Note that these parameters are specified as a win-
dow rather than absolute numbers since the device provides functionality to delay the
incoming clock with respect to the incoming data.

Information on interfacing to high-speed synchronous interfaces can be found in the Port

I/O Timing document, X5821.

14.9 xConnect Link Performance

Symbol Parameter MIN TYP MAX UNITS Notes
B(2blinkP) 2b link bandwidth (packetized) 87 MBit/s A, B
Figure 30: B(5blinkP) 5b link bandwidth (packetized) 217 MBit/s A, B
Link B(2blinkS) 2b link bandwidth (streaming) 100 MBit/s B
performance
B(5blinkS) 5b link bandwidth (streaming) 250 MBit/s B
Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header and
A payload.
B 7.5 ns symbol time.

The asynchronous nature of links means that the relative phasing of CLK clocks is not
important in a multi-clock system, providing each meets the required stability criteria.

30
 XEF216-512-FB236 Datasheet

14.10 JTAG Timing

Symbol Parameter MIN TYP MAX UNITS Notes
f(TCK_D) TCK frequency (debug) 18 MHz
f(TCK_B) TCK frequency (boundary scan) 10 MHz
T(SETUP) TDO to TCK setup time 5 ns A
Figure 31: T(HOLD) TDO to TCK hold time 5 ns A
JTAG timing
T(DELAY) TCK to output delay 15 ns B
A Timing applies to TMS and TDI inputs.
B Timing applies to TDO output from negative edge of TCK.

All JTAG operations are synchronous to TCK apart from the global asynchronous reset
TRST_N.

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 XEF216-512-FB236 Datasheet

15 Package Information

32
 XEF216-512-FB236 Datasheet

15.1 Part Marking

F - Product family
X - Reserved
CC - Number of logical cores
R - RAM [in log2(kbytes)]
N - Flash size [in log2(Mbytes)+1]
T - Temperature grade
FXCCRNTMM MM - Speed grade

MC - Manufacturer
MCYYWWXX YYWW - Date
Figure 32: XX - Reserved [variable length]
Part marking
LLLLLL.LL
scheme Wafer lot code

16 Ordering Information

Figure 33: Product Code Marking Qualification Speed Grade

Orderable part XEF216-512-FB236-C20A E01692C20 Commercial 1000 MIPS
numbers
XEF216-512-FB236-I20A E01692I20 Industrial 1000 MIPS

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 XEF216-512-FB236 Datasheet

Appendices
A Configuration of the XEF216-512-FB236
The device is configured through banks of registers, as shown in Figure 34.

X0Dxx xTIME xTIME X1Dxx

scheduler
PLL scheduler
I/O pins I/O pins
Hardware response ports JTAG Hardware response ports

xCORE logical core xCORE logical core

xCORE logical core xCORE logical core

Node configuration
Tile configuration

Tile configuration
Processor status

Processor status
xCORE logical core xCORE logical core

Switch
xCORE logical core xCORE logical core FLASH

xCORE logical core xCONNECT xCORE logical core

xCORE logical core xCORE logical core
xCORE logical core xCORE logical core
xCORE logical core xCORE logical core
Figure 34:
USB
Link 8

Registers USB
config SRAM OTP OTP SRAM RGMII

The following communication sequences specify how to access those registers. Any
messages transmitted contain the most significant 24 bits of the channel-end to which
a response is to be sent. This comprises the node-identifier and the channel number
within the node. if no response is required on a write operation, supply 24-bits with the
last 8-bits set, which suppresses the reply message. Any multi-byte data is sent most
significant byte first.

A.1 Accessing a processor status register

The processor status registers are accessed directly from the processor instruction set.
The instructions GETPS and SETPS read and write a word. The register number should
be translated into a processor-status resource identifier by shifting the register number
left 8 places, and ORing it with 0x0B. Alternatively, the functions getps(reg) and setps(
,→ reg,value) can be used from XC.

A.2 Accessing an xCORE Tile configuration register

xCORE Tile configuration registers can be accessed through the interconnect using the
functions write_tile_config_reg(tileref, ...) and read_tile_config_reg(tile ref,
,→ ...), where tileref is the name of the xCORE Tile, e.g. tile[1]. These functions
implement the protocols described below.

Instead of using the functions above, a channel-end can be allocated to communicate

with the xCORE tile configuration registers. The destination of the channel-end should
be set to 0xnnnnC20C where nnnnnn is the tile-identifier.

A write message comprises the following:

control-token 24-bit response 16-bit 32-bit control-token

192 channel-end identifier register number data 1

34
 XEF216-512-FB236 Datasheet

The response to a write message comprises either control tokens 3 and 1 (for success),
or control tokens 4 and 1 (for failure).

A read message comprises the following:

control-token 24-bit response 16-bit control-token

193 channel-end identifier register number 1

The response to the read message comprises either control token 3, 32-bit of data, and
control-token 1 (for success), or control tokens 4 and 1 (for failure).

A.3 Accessing node configuration

Node configuration registers can be accessed through the interconnect using the func-
tions write_node_config_reg(device, ...) and read_node_config_reg(device, ...), where
device is the name of the node. These functions implement the protocols described be-
low.

Instead of using the functions above, a channel-end can be allocated to communicate

with the node configuration registers. The destination of the channel-end should be set
to 0xnnnnC30C where nnnn is the node-identifier.

A write message comprises the following:

control-token 24-bit response 16-bit 32-bit control-token

192 channel-end identifier register number data 1

The response to a write message comprises either control tokens 3 and 1 (for success),
or control tokens 4 and 1 (for failure).

A read message comprises the following:

control-token 24-bit response 16-bit control-token

193 channel-end identifier register number 1

The response to a read message comprises either control token 3, 32-bit of data, and
control-token 1 (for success), or control tokens 4 and 1 (for failure).

A.4 Accessing a register of an analogue peripheral

Peripheral registers can be accessed through the interconnect using the functions write_periph_32
,→ (device, peripheral, ...), read_periph_32(device, peripheral, ...), write_periph_8
,→ (device, peripheral, ...), and read_periph_8(device, peripheral, ...); where de-
vice is the name of the analogue device, and peripheral is the number of the peripheral.
These functions implement the protocols described below.

A channel-end should be allocated to communicate with the configuration registers. The

destination of the channel-end should be set to 0xnnnnpp02 where nnnn is the node-identifier
and pp is the peripheral identifier.

A write message comprises the following:

35
 XEF216-512-FB236 Datasheet

control-token 24-bit response 8-bit 8-bit data control-token

36 channel-end identifier register number size 1

The response to a write message comprises either control tokens 3 and 1 (for success),
or control tokens 4 and 1 (for failure).

A read message comprises the following:

control-token 24-bit response 8-bit 8-bit control-token

37 channel-end identifier register number size 1

The response to the read message comprises either control token 3, data, and control-
token 1 (for success), or control tokens 4 and 1 (for failure).

36
 XEF216-512-FB236 Datasheet

B Processor Status Configuration

The processor status control registers can be accessed directly by the processor using
processor status reads and writes (use getps(reg) and setps(reg,value) for reads and
writes).

The identifiers for the registers needs a prefix “XS1_PS_” and a postfix “_NUM”, and are
declared in “xs1.h”

Number Perm Description Register identifier

0x00 RW RAM base address RAM_BASE

0x01 RW Vector base address VECTOR_BASE

0x02 RW xCORE Tile control XCORE_CTRL0

0x03 RO xCORE Tile boot status BOOT_CONFIG

0x05 RW Security configuration SECURITY_CONFIG

0x06 RW Ring Oscillator Control RING_OSC_CTRL

0x07 RO Ring Oscillator Value RING_OSC_DATA0

0x08 RO Ring Oscillator Value RING_OSC_DATA1

0x09 RO Ring Oscillator Value RING_OSC_DATA2

0x0A RO Ring Oscillator Value RING_OSC_DATA3

0x0C RO RAM size RAM_SIZE

0x10 DRW Debug SSR DBG_SSR

0x11 DRW Debug SPC DBG_SPC

0x12 DRW Debug SSP DBG_SSP

0x13 DRW DGETREG operand 1 DBG_T_NUM

0x14 DRW DGETREG operand 2 DBG_T_REG

0x15 DRW Debug interrupt type DBG_TYPE

0x16 DRW Debug interrupt data DBG_DATA

0x18 DRW Debug core control DBG_RUN_CTRL

0x20 .. 0x27 DRW Debug scratch DBG_SCRATCH

0x30 .. 0x33 DRW Instruction breakpoint address DBG_IBREAK_ADDR

0x40 .. 0x43 DRW Instruction breakpoint control DBG_IBREAK_CTRL

0x50 .. 0x53 DRW Data watchpoint address 1 DBG_DWATCH_ADDR1

Figure 35: 0x60 .. 0x63 DRW Data watchpoint address 2 DBG_DWATCH_ADDR2

Summary 0x70 .. 0x73 DRW Data breakpoint control register DBG_DWATCH_CTRL

37
 XEF216-512-FB236 Datasheet

Number Perm Description Register identifier

0x80 .. 0x83 DRW Resources breakpoint mask DBG_RWATCH_ADDR1
Figure 36:
Summary 0x90 .. 0x93 DRW Resources breakpoint value DBG_RWATCH_ADDR2

(continued) 0x9C .. 0x9F DRW Resources breakpoint control register DBG_RWATCH_CTRL

B.1 RAM base address RAM_BASE 0x00

This register contains the base address of the RAM. It is initialized to 0x00040000.

Bits Perm Init Description Identifier

0x00:
RAM base 31:2 RW Most significant 16 bits of all addresses. WORD_ADDRESS_BITS

address 1:0 RO - Reserved

B.2 Vector base address VECTOR_BASE 0x01

Base address of event vectors in each resource. On an interrupt or event, the 16 most sig-
nificant bits of the destination address are provided by this register; the least significant
16 bits come from the event vector.

Bits Perm Init Description Identifier

0x01:
Vector base 31:18 RW The event and interrupt vectors. VECTOR_BASE

address 17:0 RO - Reserved

B.3 xCORE Tile control XCORE_CTRL0 0x02

Register to control features in the xCORE tile

38
 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:26 RO - Reserved
RGMII TX data delay value (in PLL output cycle increments)
25:18 RW 0 XCORE_CTRL0_RGMII_DELAY

RGMII TX clock divider value. TX clk rises when counter (clocked

by PLL output) reaches this value and falls when counter reaches
(value»1). Value programmed into this field should be actual divide
17:9 RW 0 value required minus 1 XCORE_CTRL0_RGMII_DIVIDE

8 RW 0 Enable RGMII interface periph ports XCORE_CTRL0_RGMII_ENABLE

7:6 RO - Reserved
Select the dynamic mode (1) for the clock divider when the clock divider
is enabled. In dynamic mode the clock divider is only activated when
all active threads are paused. In static mode the clock divider is always
5 RW 0 enabled. XCORE_CTRL0_CLK_DIVIDER_DYN

Enable the clock divider. This divides the output of the PLL to facilitate
4 RW 0 one of the low power modes. XCORE_CTRL0_CLK_DIVIDER_EN

3 RO - Reserved
2 RW Select between UTMI (1) and ULPI (0) mode. XCORE_CTRL0_USB_MODE
0x02:
xCORE Tile 1 RW Enable the ULPI Hardware support module XCORE_CTRL0_USB_ENABLE

control 0 RO - Reserved

B.4 xCORE Tile boot status BOOT_CONFIG 0x03

This read-only register describes the boot status of the xCORE tile.

Bits Perm Init Description Identifier

31:24 RO - Reserved
23:16 RO Processor number. BOOT_CONFIG_PROCESSOR

15:9 RO - Reserved
8 RO Overwrite BOOT_MODE. BOOT_CONFIG_SECURE_BOOT

7:6 RO - Reserved
5 RO Indicates if core1 has been powered off BOOT_CONFIG_CORE1_POWER_DOWN_N

Cause the ROM to not poll the OTP for correct read levels
4 RO BOOT_CONFIG_DISABLE_OTP_POLL

3 RO Boot ROM boots from RAM BOOT_CONFIG_BOOT_FROM_RAM

0x03:
xCORE Tile 2 RO Boot ROM boots from JTAG BOOT_CONFIG_BOOT_FROM_JTAG

boot status 1:0 RO The boot PLL mode pin value. BOOT_CONFIG_PLL_MODE_PINS

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 XEF216-512-FB236 Datasheet

B.5 Security configuration SECURITY_CONFIG 0x05

Copy of the security register as read from OTP.

Bits Perm Init Description Identifier

31 RW Disables write permission on this register SECUR_CFG_DISABLE_ACCESS

30:15 RO - Reserved
14 RW Disable access to XCore’s global debug SECUR_CFG_DISABLE_GLOBAL_DEBUG

13 RO - Reserved
12 RW lock all OTP sectors SECUR_CFG_OTP_MASTER_LOCK

11:8 RW lock bit for each OTP sector SECUR_CFG_OTP_SECTOR_LOCK

7 RW Enable OTP reduanacy SECUR_CFG_OTP_REDUANACY_ENABLE

6 RO - Reserved
5 RW Override boot mode and read boot image from OTP SECUR_CFG_SECURE_BOOT

Disable JTAG access to the PLL/BOOT configuration registers

4 RW SECUR_CFG_DISABLE_PLL_JTAG
0x05:
Security 3:1 RO - Reserved
configuration 0 RW Disable access to XCore’s JTAG debug TAP SECUR_CFG_DISABLE_XCORE_JTAG

B.6 Ring Oscillator Control RING_OSC_CTRL 0x06

There are four free-running oscillators that clock four counters. The oscillators can be
started and stopped using this register. The counters should only be read when the ring
oscillator has been stopped for at least 10 core clock cycles (this can be achieved by
inserting two nop instructions between the SETPS and GETPS). The counter values can
be read using four subsequent registers. The ring oscillators are asynchronous to the
xCORE tile clock and can be used as a source of random bits.

Bits Perm Init Description Identifier

31:2 RO - Reserved
0x06:
Ring Oscillator 1 RW 0 Core ring oscillator enable. RING_OSC_CORE_ENABLE

Control 0 RW 0 Peripheral ring oscillator enable. RING_OSC_PERPH_ENABLE

B.7 Ring Oscillator Value RING_OSC_DATA0 0x07

This register contains the current count of the xCORE Tile Cell ring oscillator. This value
is not reset on a system reset.

40
 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

0x07:
Ring Oscillator 31:16 RO - Reserved
Value 15:0 RO 0 Ring oscillator Counter data. RING_OSC_DATA

B.8 Ring Oscillator Value RING_OSC_DATA1 0x08

This register contains the current count of the xCORE Tile Wire ring oscillator. This value
is not reset on a system reset.

Bits Perm Init Description Identifier

0x08:
Ring Oscillator 31:16 RO - Reserved
Value 15:0 RO 0 Ring oscillator Counter data. RING_OSC_DATA

B.9 Ring Oscillator Value RING_OSC_DATA2 0x09

This register contains the current count of the Peripheral Cell ring oscillator. This value
is not reset on a system reset.

Bits Perm Init Description Identifier

0x09:
Ring Oscillator 31:16 RO - Reserved
Value 15:0 RO 0 Ring oscillator Counter data. RING_OSC_DATA

B.10 Ring Oscillator Value RING_OSC_DATA3 0x0A

This register contains the current count of the Peripheral Wire ring oscillator. This value
is not reset on a system reset.

Bits Perm Init Description Identifier

0x0A:
Ring Oscillator 31:16 RO - Reserved
Value 15:0 RO 0 Ring oscillator Counter data. RING_OSC_DATA

B.11 RAM size RAM_SIZE 0x0C

The size of the RAM in bytes

Bits Perm Init Description Identifier

0x0C: 31:2 RO Most significant 16 bits of all addresses. WORD_ADDRESS_BITS

RAM size 1:0 RO - Reserved

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 XEF216-512-FB236 Datasheet

B.12 Debug SSR DBG_SSR 0x10

This register contains the value of the SSR register when the debugger was called.

Bits Perm Init Description Identifier

31:11 RO - Reserved
10 DRW Address space indentifier SR_QUEUE

Determines the issue mode (DI bit) upon Kernel Entry after Exception
9 DRW or Interrupt. SR_KEDI

8 RO Determines the issue mode (DI bit). SR_DI

7 DRW When 1 the thread is in fast mode and will continually issue. SR_FAST

When 1 the thread is paused waiting for events, a lock or another

6 DRW resource. SR_WAITING

5 RO - Reserved
4 DRW 1 when in kernel mode. SR_INK

3 DRW 1 when in an interrupt handler. SR_ININT

2 DRW 1 when in an event enabling sequence. SR_INENB

0x10: 1 DRW When 1 interrupts are enabled for the thread. SR_IEBLE

Debug SSR 0 DRW When 1 events are enabled for the thread. SR_EEBLE

B.13 Debug SPC DBG_SPC 0x11

This register contains the value of the SPC register when the debugger was called.

0x11: Bits Perm Init Description Identifier

Debug SPC 31:0 DRW Value. ALL_BITS

B.14 Debug SSP DBG_SSP 0x12

This register contains the value of the SSP register when the debugger was called.

0x12: Bits Perm Init Description Identifier

Debug SSP 31:0 DRW Value. ALL_BITS

B.15 DGETREG operand 1 DBG_T_NUM 0x13

The resource ID of the logical core whose state is to be read.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

0x13:
DGETREG 31:8 RO - Reserved
operand 1 7:0 DRW Thread number to be read DBG_T_NUM_NUM

B.16 DGETREG operand 2 DBG_T_REG 0x14

Register number to be read by DGETREG

Bits Perm Init Description Identifier

0x14:
DGETREG 31:5 RO - Reserved
operand 2 4:0 DRW Register number to be read DBG_T_REG_REG

B.17 Debug interrupt type DBG_TYPE 0x15

Register that specifies what activated the debug interrupt.

Bits Perm Init Description Identifier

31:18 RO - Reserved
Number of the hardware breakpoint/watchpoint which caused the
interrupt (always 0 for =HOST= and =DCALL=). If multiple break-
points/watchpoints trigger at once, the lowest number is taken.
17:16 DRW DBG_TYPE_HW_NUM

Number of thread which caused the debug interrupt (always 0 in the

15:8 DRW case of =HOST=). DBG_TYPE_T_NUM

7:3 RO - Reserved
Indicates the cause of the debug interrupt
1: Host initiated a debug interrupt through JTAG
2: Program executed a DCALL instruction
0x15: 3: Instruction breakpoint
Debug 4: Data watch point
interrupt type 2:0 DRW 0 5: Resource watch point DBG_TYPE_CAUSE

B.18 Debug interrupt data DBG_DATA 0x16

On a data watchpoint, this register contains the effective address of the memory oper-
ation that triggered the debugger. On a resource watchpoint, it countains the resource
identifier.

0x16:
Debug Bits Perm Init Description Identifier
interrupt data 31:0 DRW Value. ALL_BITS

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 XEF216-512-FB236 Datasheet

B.19 Debug core control DBG_RUN_CTRL 0x18

This register enables the debugger to temporarily disable logical cores. When returning
from the debug interrupts, the cores set in this register will not execute. This enables
single stepping to be implemented.

Bits Perm Init Description Identifier

31:8 RO - Reserved
0x18: 1-hot vector defining which threads are stopped when not in debug
Debug core mode. Every bit which is set prevents the respective thread from
control 7:0 DRW running. DBG_RUN_CTRL_STOP

B.20 Debug scratch DBG_SCRATCH 0x20 .. 0x27

A set of registers used by the debug ROM to communicate with an external debugger,
for example over JTAG. This is the same set of registers as the Debug Scratch registers
in the xCORE tile configuration.

0x20 .. 0x27: Bits Perm Init Description Identifier

Debug scratch 31:0 DRW Value. ALL_BITS

B.21 Instruction breakpoint address DBG_IBREAK_ADDR 0x30 .. 0x33

This register contains the address of the instruction breakpoint. If the PC matches this
address, then a debug interrupt will be taken. There are four instruction breakpoints that
are controlled individually.

0x30 .. 0x33:
Instruction
breakpoint Bits Perm Init Description Identifier
address 31:0 DRW Value. ALL_BITS

B.22 Instruction breakpoint control DBG_IBREAK_CTRL 0x40 .. 0x43

This register controls which logical cores may take an instruction breakpoint, and under
which condition.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:24 RO - Reserved
A bit for each thread in the machine allowing the breakpoint to be en-
abled individually for each thread.
23:16 DRW 0 BRK_THREADS

15:2 RO - Reserved
0x40 .. 0x43:
Instruction When 0 break when PC == IBREAK_ADDR. When 1 = break when PC !=
breakpoint 1 DRW 0 IBREAK_ADDR. IBRK_CONDITION

control 0 DRW 0 When 1 the instruction breakpoint is enabled. BRK_ENABLE

B.23 Data watchpoint address 1 DBG_DWATCH_ADDR1 0x50 .. 0x53

This set of registers contains the first address for the four data watchpoints.

0x50 .. 0x53:
Data
watchpoint Bits Perm Init Description Identifier
address 1 31:0 DRW Value. ALL_BITS

B.24 Data watchpoint address 2 DBG_DWATCH_ADDR2 0x60 .. 0x63

This set of registers contains the second address for the four data watchpoints.

0x60 .. 0x63:
Data
watchpoint Bits Perm Init Description Identifier
address 2 31:0 DRW Value. ALL_BITS

B.25 Data breakpoint control register DBG_DWATCH_CTRL 0x70 .. 0x73

This set of registers controls each of the four data watchpoints.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:24 RO - Reserved
A bit for each thread in the machine allowing the breakpoint to be en-
abled individually for each thread.
23:16 DRW 0 BRK_THREADS

0x70 .. 0x73: 15:3 RO - Reserved

Data 2 DRW 0 When 1 the breakpoints will be be triggered on loads. BRK_LOAD
breakpoint
control 1 DRW 0 Determines the break condition: 0 = A AND B, 1 = A OR B. DBRK_CONDITION

register 0 DRW 0 When 1 the instruction breakpoint is enabled. BRK_ENABLE

B.26 Resources breakpoint mask DBG_RWATCH_ADDR1 0x80 .. 0x83

This set of registers contains the mask for the four resource watchpoints.

0x80 .. 0x83:
Resources
breakpoint Bits Perm Init Description Identifier
mask 31:0 DRW Value. ALL_BITS

B.27 Resources breakpoint value DBG_RWATCH_ADDR2 0x90 .. 0x93

This set of registers contains the value for the four resource watchpoints.

0x90 .. 0x93:
Resources
breakpoint Bits Perm Init Description Identifier
value 31:0 DRW Value. ALL_BITS

B.28 Resources breakpoint control register DBG_RWATCH_CTRL 0x9C ..

0x9F
This set of registers controls each of the four resource watchpoints.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:24 RO - Reserved
A bit for each thread in the machine allowing the breakpoint to be en-
abled individually for each thread.
23:16 DRW 0 BRK_THREADS

0x9C .. 0x9F: 15:2 RO - Reserved

Resources
breakpoint When 0 break when condition A is met. When 1 = break when condition
control 1 DRW 0 B is met. RBRK_CONDITION

register 0 DRW 0 When 1 the instruction breakpoint is enabled. BRK_ENABLE

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 XEF216-512-FB236 Datasheet

C Tile Configuration
The xCORE Tile control registers can be accessed using configuration reads and writes
(use write_tile_config_reg(tileref, ...) and read_tile_config_reg(tileref, ...) for
reads and writes).

The identifiers for the registers needs a prefix “XS1_PSWITCH_” and a postfix “_NUM”, and
are declared in “xs1.h”

Number Perm Description Register identifier

0x00 CRO Device identification DEVICE_ID0

0x01 CRO xCORE Tile description 1 DEVICE_ID1

0x02 CRO xCORE Tile description 2 DEVICE_ID2

0x04 CRW Control PSwitch permissions to debug registers DBG_CTRL

0x05 CRW Cause debug interrupts DBG_INT

0x06 CRW xCORE Tile clock divider PLL_CLK_DIVIDER

0x07 CRO Security configuration SECU_CONFIG

0x20 .. 0x27 CRW Debug scratch DBG_SCRATCH

0x40 CRO PC of logical core 0 T0_PC

0x41 CRO PC of logical core 1 T1_PC

0x42 CRO PC of logical core 2 T2_PC

0x43 CRO PC of logical core 3 T3_PC

0x44 CRO PC of logical core 4 T4_PC

0x45 CRO PC of logical core 5 T5_PC

0x46 CRO PC of logical core 6 T6_PC

0x47 CRO PC of logical core 7 T7_PC

0x60 CRO SR of logical core 0 T0_SR

0x61 CRO SR of logical core 1 T1_SR

0x62 CRO SR of logical core 2 T2_SR

0x63 CRO SR of logical core 3 T3_SR

0x64 CRO SR of logical core 4 T4_SR

0x65 CRO SR of logical core 5 T5_SR

Figure 37: 0x66 CRO SR of logical core 6 T6_SR

Summary 0x67 CRO SR of logical core 7 T7_SR

C.1 Device identification DEVICE_ID0 0x00

This register identifies the xCORE Tile

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:24 CRO Processor ID of this XCore. DEVICE_ID0_PID

23:16 CRO Number of the node in which this XCore is located. DEVICE_ID0_NODE
0x00:
Device 15:8 CRO XCore revision. DEVICE_ID0_REVISION

identification 7:0 CRO XCore version. DEVICE_ID0_VERSION

C.2 xCORE Tile description 1 DEVICE_ID1 0x01

This register describes the number of logical cores, synchronisers, locks and channel
ends available on this xCORE tile.

Bits Perm Init Description Identifier

31:24 CRO Number of channel ends. DEVICE_ID1_NUM_CHANENDS

23:16 CRO Number of the locks. DEVICE_ID1_NUM_LOCKS

0x01:
xCORE Tile 15:8 CRO Number of synchronisers. DEVICE_ID1_NUM_SYNCS

description 1 7:0 RO - Reserved

C.3 xCORE Tile description 2 DEVICE_ID2 0x02

This register describes the number of timers and clock blocks available on this xCORE
tile.

Bits Perm Init Description Identifier

31:16 RO - Reserved
0x02:
xCORE Tile 15:8 CRO Number of clock blocks. DEVICE_ID2_NUM_CLKBLKS

description 2 7:0 CRO Number of timers. DEVICE_ID2_NUM_TIMERS

C.4 Control PSwitch permissions to debug registers DBG_CTRL 0x04

This register can be used to control whether the debug registers (marked with permission
CRW) are accessible through the tile configuration registers. When this bit is set, write
-access to those registers is disabled, preventing debugging of the xCORE tile over the
interconnect.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

0x04: When 1 the PSwitch is restricted to RO access to all CRW registers from
Control 31 CRW 0 SSwitch, XCore(PS_DBG_Scratch) and JTAG DBG_CTRL_PSWITCH_RO
PSwitch
permissions 30:1 RO - Reserved
to debug When 1 the PSwitch is restricted to RO access to all CRW registers from
registers 0 CRW 0 SSwitch DBG_CTRL_PSWITCH_RO_EXT

C.5 Cause debug interrupts DBG_INT 0x05

This register can be used to raise a debug interrupt in this xCORE tile.

Bits Perm Init Description Identifier

31:2 RO - Reserved
0x05:
Cause debug 1 CRW 0 1 when the processor is in debug mode. DBG_INT_IN_DBG

interrupts 0 CRW 0 Request a debug interrupt on the processor. DBG_INT_REQ_DBG

C.6 xCORE Tile clock divider PLL_CLK_DIVIDER 0x06

This register contains the value used to divide the PLL clock to create the xCORE tile
clock. The divider is enabled under control of the tile control register

Bits Perm Init Description Identifier

31 CRW 0 Clock disable. Writing ’1’ will remove the clock to the tile. PLL_CLK_DISABLE
0x06:
xCORE Tile 30:16 RO - Reserved
clock divider 15:0 CRW 0 Clock divider. PLL_CLK_DIVIDER

C.7 Security configuration SECU_CONFIG 0x07

Copy of the security register as read from OTP.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31 CRO Disables write permission on this register SECUR_CFG_DISABLE_ACCESS

30:15 RO - Reserved
14 CRO Disable access to XCore’s global debug SECUR_CFG_DISABLE_GLOBAL_DEBUG

13 RO - Reserved
12 CRO lock all OTP sectors SECUR_CFG_OTP_MASTER_LOCK

11:8 CRO lock bit for each OTP sector SECUR_CFG_OTP_SECTOR_LOCK

7 CRO Enable OTP reduanacy SECUR_CFG_OTP_REDUANACY_ENABLE

6 RO - Reserved
5 CRO Override boot mode and read boot image from OTP SECUR_CFG_SECURE_BOOT

Disable JTAG access to the PLL/BOOT configuration registers

4 CRO SECUR_CFG_DISABLE_PLL_JTAG
0x07:
Security 3:1 RO - Reserved
configuration 0 CRO Disable access to XCore’s JTAG debug TAP SECUR_CFG_DISABLE_XCORE_JTAG

C.8 Debug scratch DBG_SCRATCH 0x20 .. 0x27

A set of registers used by the debug ROM to communicate with an external debugger, for
example over the switch. This is the same set of registers as the Debug Scratch registers
in the processor status.

0x20 .. 0x27: Bits Perm Init Description Identifier

Debug scratch 31:0 CRW Value. ALL_BITS

C.9 PC of logical core 0 T0_PC 0x40

Value of the PC of logical core 0.

0x40:
PC of logical Bits Perm Init Description Identifier
core 0 31:0 CRO Value. ALL_BITS

C.10 PC of logical core 1 T1_PC 0x41

Value of the PC of logical core 1.

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 XEF216-512-FB236 Datasheet

0x41:
PC of logical Bits Perm Init Description Identifier
core 1 31:0 CRO Value. ALL_BITS

C.11 PC of logical core 2 T2_PC 0x42

Value of the PC of logical core 2.

0x42:
PC of logical Bits Perm Init Description Identifier
core 2 31:0 CRO Value. ALL_BITS

C.12 PC of logical core 3 T3_PC 0x43

Value of the PC of logical core 3.

0x43:
PC of logical Bits Perm Init Description Identifier
core 3 31:0 CRO Value. ALL_BITS

C.13 PC of logical core 4 T4_PC 0x44

Value of the PC of logical core 4.

0x44:
PC of logical Bits Perm Init Description Identifier
core 4 31:0 CRO Value. ALL_BITS

C.14 PC of logical core 5 T5_PC 0x45

Value of the PC of logical core 5.

0x45:
PC of logical Bits Perm Init Description Identifier
core 5 31:0 CRO Value. ALL_BITS

C.15 PC of logical core 6 T6_PC 0x46

Value of the PC of logical core 6.

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 XEF216-512-FB236 Datasheet

0x46:
PC of logical Bits Perm Init Description Identifier
core 6 31:0 CRO Value. ALL_BITS

C.16 PC of logical core 7 T7_PC 0x47

Value of the PC of logical core 7.

0x47:
PC of logical Bits Perm Init Description Identifier
core 7 31:0 CRO Value. ALL_BITS

C.17 SR of logical core 0 T0_SR 0x60

Value of the SR of logical core 0

0x60:
SR of logical Bits Perm Init Description Identifier
core 0 31:0 CRO Value. ALL_BITS

C.18 SR of logical core 1 T1_SR 0x61

Value of the SR of logical core 1

0x61:
SR of logical Bits Perm Init Description Identifier
core 1 31:0 CRO Value. ALL_BITS

C.19 SR of logical core 2 T2_SR 0x62

Value of the SR of logical core 2

0x62:
SR of logical Bits Perm Init Description Identifier
core 2 31:0 CRO Value. ALL_BITS

C.20 SR of logical core 3 T3_SR 0x63

Value of the SR of logical core 3

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 XEF216-512-FB236 Datasheet

0x63:
SR of logical Bits Perm Init Description Identifier
core 3 31:0 CRO Value. ALL_BITS

C.21 SR of logical core 4 T4_SR 0x64

Value of the SR of logical core 4

0x64:
SR of logical Bits Perm Init Description Identifier
core 4 31:0 CRO Value. ALL_BITS

C.22 SR of logical core 5 T5_SR 0x65

Value of the SR of logical core 5

0x65:
SR of logical Bits Perm Init Description Identifier
core 5 31:0 CRO Value. ALL_BITS

C.23 SR of logical core 6 T6_SR 0x66

Value of the SR of logical core 6

0x66:
SR of logical Bits Perm Init Description Identifier
core 6 31:0 CRO Value. ALL_BITS

C.24 SR of logical core 7 T7_SR 0x67

Value of the SR of logical core 7

0x67:
SR of logical Bits Perm Init Description Identifier
core 7 31:0 CRO Value. ALL_BITS

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 XEF216-512-FB236 Datasheet

D Node Configuration
The digital node control registers can be accessed using configuration reads and writes
(use write_node_config_reg(device, ...) and read_node_config_reg(device, ...) for
reads and writes).

The identifiers for the registers needs a prefix “XS1_SSWITCH_” and a postfix “_NUM”, and
are declared in “xs1.h”

Number Perm Description Register identifier

0x00 RO Device identification DEVICE_ID0

0x01 RO System switch description DEVICE_ID1

0x04 RW Switch configuration NODE_CONFIG

0x05 RW Switch node identifier NODE_ID

0x06 RW PLL settings PLL_CTL

0x07 RW System switch clock divider CLK_DIVIDER

0x08 RW Reference clock REF_CLK_DIVIDER

0x09 R System JTAG device ID register JTAG_DEVICE_ID

0x0A R System USERCODE register JTAG_USERCODE

0x0C RW Directions 0-7 DIMENSION_DIRECTION0

0x0D RW Directions 8-15 DIMENSION_DIRECTION1

0x10 RW DEBUG_N configuration, tile 0 XCORE0_GLOBAL_DEBUG_CONFIG

0x11 RW DEBUG_N configuration, tile 1 XCORE1_GLOBAL_DEBUG_CONFIG

0x1F RO Debug source GLOBAL_DEBUG_SOURCE

0x20 .. 0x28 RW Link status, direction, and network SLINK

0x40 .. 0x47 RO PLink status and network PLINK

Figure 38: 0x80 .. 0x88 RW Link configuration and initialization XLINK

Summary 0xA0 .. 0xA7 RW Static link configuration XSTATIC

D.1 Device identification DEVICE_ID0 0x00

This register contains version and revision identifiers and the mode-pins as sampled at
boot-time.

Bits Perm Init Description Identifier

31:24 RO - Reserved
23:16 RO Sampled values of BootCtl pins on Power On Reset. SS_DEVICE_ID0_BOOT_CTRL
0x00:
Device 15:8 RO SSwitch revision. SS_DEVICE_ID0_REVISION

identification 7:0 RO SSwitch version. SS_DEVICE_ID0_VERSION

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 XEF216-512-FB236 Datasheet

D.2 System switch description DEVICE_ID1 0x01

This register specifies the number of processors and links that are connected to this
switch.

Bits Perm Init Description Identifier

31:24 RO - Reserved
23:16 RO Number of SLinks on the SSwitch. SS_DEVICE_ID1_NUM_SLINKS
0x01:
System switch 15:8 RO Number of processors on the SSwitch. SS_DEVICE_ID1_NUM_PROCESSORS

description 7:0 RO Number of processors on the device. SS_DEVICE_ID1_NUM_PLINKS_PER_PROC

D.3 Switch configuration NODE_CONFIG 0x04

This register enables the setting of two security modes (that disable updates to the PLL
or any other registers) and the header-mode.

Bits Perm Init Description Identifier

0 = SSCTL registers have write access. 1 = SSCTL registers can not be
31 RW 0 written to. SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE

30:9 RO - Reserved
0 = PLL_CTL_REG has write access. 1 = PLL_CTL_REG can not be writ-
ten to.
8 RW 0 SS_NODE_CONFIG_DISABLE_PLL_CTL_REG
0x04:
Switch 7:1 RO - Reserved
configuration 0 RW 0 0 = 2-byte headers, 1 = 1-byte headers (reset as 0). SS_NODE_CONFIG_HEADERS

D.4 Switch node identifier NODE_ID 0x05

This register contains the node identifier.

Bits Perm Init Description Identifier

0x05:
Switch node 31:16 RO - Reserved
identifier 15:0 RW 0 The unique ID of this node. SS_NODE_ID_ID

D.5 PLL settings PLL_CTL 0x06

An on-chip PLL multiplies the input clock up to a higher frequency clock, used to clock
the I/O, processor, and switch, see Oscillator. Note: a write to this register will cause the
tile to be reset.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31 RW If set to 1, the chip will not be reset SS_PLL_CTL_NRESET

If set to 1, the chip will not wait for the PLL to re-lock. Only use this if a
30 RW gradual change is made to the PLL SS_PLL_CTL_NLOCK

29 DW If set to 1, set the PLL to be bypassed SS_TEST_MODE_PLL_BYPASS

28 DW If set to 1, set the boot mode to boot from JTAG SS_TEST_MODE_BOOT_JTAG

27:26 RO - Reserved
Output divider value range from 0 (8’h0) to 7 (8’h7). OD value.
25:23 RW SS_PLL_CTL_POST_DIVISOR

22:21 RO - Reserved
Feedback multiplication ratio, range from 0 (8’h0) to 4095 (8’h3FF). F
20:8 RW value. SS_PLL_CTL_FEEDBACK_MUL

7 RO - Reserved
0x06: Oscilator input divider value range from 0 (8’h0) to 63 (8’h3F). R value.
PLL settings 6:0 RW SS_PLL_CTL_INPUT_DIVISOR

D.6 System switch clock divider CLK_DIVIDER 0x07

Sets the ratio of the PLL clock and the switch clock.

Bits Perm Init Description Identifier

0x07:
System switch 31:16 RO - Reserved
clock divider 15:0 RW 0 SSwitch clock generation SS_CLK_DIVIDER_CLK_DIV

D.7 Reference clock REF_CLK_DIVIDER 0x08

Sets the ratio of the PLL clock and the reference clock used by the node.

Bits Perm Init Description Identifier

0x08:
Reference 31:16 RO - Reserved
clock 15:0 RW 3 Software ref. clock divider SS_SSWITCH_REF_CLK_DIV

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 XEF216-512-FB236 Datasheet

D.8 System JTAG device ID register JTAG_DEVICE_ID 0x09

Bits Perm Init Description Identifier

31:28 RO SS_JTAG_DEVICE_ID_VERSION

0x09: 27:12 RO SS_JTAG_DEVICE_ID_PART_NUM

System JTAG
device ID 11:1 RO SS_JTAG_DEVICE_ID_MANU_ID

register 0 RO SS_JTAG_DEVICE_ID_CONST_VAL

D.9 System USERCODE register JTAG_USERCODE 0x0A

0x0A: Bits Perm Init Description Identifier

System
USERCODE 31:18 RO JTAG USERCODE value programmed into OTP SR SS_JTAG_USERCODE_OTP

register 17:0 RO metal fixable ID code SS_JTAG_USERCODE_MASKID

D.10 Directions 0-7 DIMENSION_DIRECTION0 0x0C

This register contains eight directions, for packets with a mismatch in bits 7..0 of the
node-identifier. The direction in which a packet will be routed is goverened by the most
significant mismatching bit.

Bits Perm Init Description Identifier

31:28 RW 0 The direction for packets whose dimension is 7. DIM7_DIR

27:24 RW 0 The direction for packets whose dimension is 6. DIM6_DIR

23:20 RW 0 The direction for packets whose dimension is 5. DIM5_DIR

19:16 RW 0 The direction for packets whose dimension is 4. DIM4_DIR

15:12 RW 0 The direction for packets whose dimension is 3. DIM3_DIR

11:8 RW 0 The direction for packets whose dimension is 2. DIM2_DIR

0x0C: 7:4 RW 0 The direction for packets whose dimension is 1. DIM1_DIR

Directions 0-7 3:0 RW 0 The direction for packets whose dimension is 0. DIM0_DIR

D.11 Directions 8-15 DIMENSION_DIRECTION1 0x0D

This register contains eight directions, for packets with a mismatch in bits 15..8 of the
node-identifier. The direction in which a packet will be routed is goverened by the most
significant mismatching bit.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:28 RW 0 The direction for packets whose dimension is F. DIMF_DIR

27:24 RW 0 The direction for packets whose dimension is E. DIME_DIR

23:20 RW 0 The direction for packets whose dimension is D. DIMD_DIR

19:16 RW 0 The direction for packets whose dimension is C. DIMC_DIR

15:12 RW 0 The direction for packets whose dimension is B. DIMB_DIR

11:8 RW 0 The direction for packets whose dimension is A. DIMA_DIR

0x0D:
Directions 7:4 RW 0 The direction for packets whose dimension is 9. DIM9_DIR

8-15 3:0 RW 0 The direction for packets whose dimension is 8. DIM8_DIR

D.12 DEBUG_N configuration, tile 0 XCORE0_GLOBAL_DEBUG_CONFIG 0x10

Configures the behavior of the DEBUG_N pin.

Bits Perm Init Description Identifier

31:2 RO - Reserved
0x10:
DEBUG_N Set 1 to enable GlobalDebug to generate debug request to XCore.
configuration, 1 RW 0 GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ

tile 0 0 RW 0 Set 1 to enable inDebug bit to drive GlobalDebug. GLOBAL_DEBUG_ENABLE_INDEBUG

D.13 DEBUG_N configuration, tile 1 XCORE1_GLOBAL_DEBUG_CONFIG 0x11

Configures the behavior of the DEBUG_N pin.

Bits Perm Init Description Identifier

31:2 RO - Reserved
0x11:
DEBUG_N Set 1 to enable GlobalDebug to generate debug request to XCore.
configuration, 1 RW 0 GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ

tile 1 0 RW 0 Set 1 to enable inDebug bit to drive GlobalDebug. GLOBAL_DEBUG_ENABLE_INDEBUG

D.14 Debug source GLOBAL_DEBUG_SOURCE 0x1F

Contains the source of the most recent debug event.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:5 RO - Reserved
If set, external pin, is the source of last GlobalDebug event.
4 RW GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG

3:2 RO - Reserved
If set, XCore1 is the source of last GlobalDebug event.
1 RW GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG

0x1F: If set, XCore0 is the source of last GlobalDebug event.

Debug source 0 RW GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG

D.15 Link status, direction, and network SLINK 0x20 .. 0x28

These registers contain status information for low level debugging (read-only), the net-
work number that each link belongs to, and the direction that each link is part of. The
registers control links 0..7.

Bits Perm Init Description Identifier

31:26 RO - Reserved
Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 -
25:24 RO Undefine. SLINK_SRC_TARGET_TYPE

When the link is in use, this is the destination link number to which all
23:16 RO packets are sent. SLINK_SRC_TARGET_ID

15:12 RO - Reserved
11:8 RW 0 The direction that this link operates in. LINK_DIRECTION

7:6 RO - Reserved
Determines the network to which this link belongs, reset as 0.
5:4 RW 0 LINK_NETWORK

3 RO - Reserved
1 when the current packet is considered junk and will be thrown away.
0x20 .. 0x28: 2 RO LINK_JUNK
Link status,
direction, and 1 RO 1 when the dest side of the link is in use. LINK_DST_INUSE

network 0 RO 1 when the source side of the link is in use. LINK_SRC_INUSE

D.16 PLink status and network PLINK 0x40 .. 0x47

These registers contain status information and the network number that each processor-
link belongs to.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:26 RO - Reserved
Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 -
25:24 RO Undefine. PLINK_SRC_TARGET_TYPE

When the link is in use, this is the destination link number to which all
23:16 RO packets are sent. PLINK_SRC_TARGET_ID

15:6 RO - Reserved
Determines the network to which this link belongs, reset as 0.
5:4 RW 0 LINK_NETWORK

3 RO - Reserved
1 when the current packet is considered junk and will be thrown away.
2 RO LINK_JUNK
0x40 .. 0x47:
PLink status 1 RO 1 when the dest side of the link is in use. LINK_DST_INUSE

and network 0 RO 1 when the source side of the link is in use. LINK_SRC_INUSE

D.17 Link configuration and initialization XLINK 0x80 .. 0x88

These registers contain configuration and debugging information specific to external
links. The link speed and width can be set, the link can be initialized, and the link sta-
tus can be monitored. The registers control links 0..7.

Bits Perm Init Description Identifier

Write to this bit with ’1’ will enable the XLink, writing ’0’ will disable it.
This bit controls the muxing of ports with overlapping xlinks.
31 RW XLINK_ENABLE

30 RW 0 0: operate in 2 wire mode; 1: operate in 5 wire mode XLINK_WIDE

29:28 RO - Reserved
27 RO Rx buffer overflow or illegal token encoding received. XLINK_RX_ERROR

This end of the xlink has issued credit to allow the remote end to
26 RO 0 transmit RX_CREDIT

25 RO 0 This end of the xlink has credit to allow it to transmit. TX_CREDIT

24 WO Clear this end of the xlink’s credit and issue a HELLO token. XLINK_HELLO

Reset the receiver. The next symbol that is detected will be the first
23 WO symbol in a token. XLINK_RX_RESET

22 RO - Reserved
0x80 .. 0x88:
Link Specify min. number of idle system clocks between two continuous
configuration 21:11 RW 0 symbols witin a transmit token -1. XLINK_INTRA_TOKEN_DELAY

and Specify min. number of idle system clocks between two continuous
initialization 10:0 RW 0 transmit tokens -1. XLINK_INTER_TOKEN_DELAY

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 XEF216-512-FB236 Datasheet

D.18 Static link configuration XSTATIC 0xA0 .. 0xA7

These registers are used for static (ie, non-routed) links. When a link is made static, all
traffic is forwarded to the designated channel end and no routing is attempted. The
registers control links C, D, A, B, G, H, E, and F in that order.

Bits Perm Init Description Identifier

31 RW 0 Enable static forwarding. XSTATIC_ENABLE

30:9 RO - Reserved
The destination processor on this node that packets received in static
8 RW 0 mode are forwarded to. XSTATIC_DEST_PROC

0xA0 .. 0xA7: 7:5 RO - Reserved

Static link The destination channel end on this node that packets received in static
configuration 4:0 RW 0 mode are forwarded to. XSTATIC_DEST_CHAN_END

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 XEF216-512-FB236 Datasheet

E USB Node Configuration

The USB node control registers can be accessed using configuration reads and writes
(use write_node_config_reg(device, ...) and read_node_config_reg(device, ...) for
reads and writes).

Number Perm Description Register identifier

0x00 RO Device identification register DEV_ID

0x04 RW Node configuration register NODE_CFG

0x05 RW Node identifier NODE_ID_SCTH

Figure 39: 0x51 RW System clock frequency SYS_CLK_FREQ

Summary 0x80 RW Link Control and Status LINK_CTRL

E.1 Device identification register DEV_ID 0x00

This register contains version information, and information on power-on behavior.

Bits Perm Init Description Identifier

31:24 RO 0x0F Chip identifier GLX_CFG_CHIP_ID

0x00: 23:16 RO - Reserved

Device
identification 15:8 RO 0x02 Revision number of the USB block GLX_CFG_REVISION

register 7:0 RO 0x00 Version number of the USB block GLX_CFG_VERSION

E.2 Node configuration register NODE_CFG 0x04

This register is used to set the communication model to use (1 or 3 byte headers), and
to prevent any further updates.

Bits Perm Init Description Identifier

Set to 1 to disable further updates to the node configuration and link
0x04: 31 RW 0 control and status registers. GLX_CFG_DISABLE_UPDATES
Node
configuration 30:1 RO - Reserved
register 0 RW 0 Header mode. 0: 3-byte headers; 1: 1-byte headers. GLX_CFG_HDR_MODE

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 XEF216-512-FB236 Datasheet

E.3 Node identifier NODE_ID_SCTH 0x05

Bits Perm Init Description Identifier

31:16 RO - Reserved
0x05: 16-bit node identifier. This does not need to be set, and is present for
Node identifier 15:0 RW 0 compatibility with XS1-switches. GLX_CFG_NODE_ID_SCTH

E.4 System clock frequency SYS_CLK_FREQ 0x51

Bits Perm Init Description Identifier

31:7 RO - Reserved
Oscillator clock frequency in MHz rounded up to the nearest integer
value. Only values between 5 and 100 MHz are valid - writes outside
this range are ignored and will be NACKed.
This field must be set on start up of the device and any time that the
0x51: input oscillator clock frequency is changed. It must contain the system
System clock clock frequency in MHz rounded up to the nearest integer value.
frequency 6:0 RW 25 GLX_CFG_SYS_CLK_FREQ

E.5 Link Control and Status LINK_CTRL 0x80

Bits Perm Init Description Identifier

31:28 RO - Reserved
27 RO Rx buffer overflow or illegal token encoding received. XLINK_RX_ERROR

This end of the xlink has issued credit to allow the remote end to
26 RO 0 transmit RX_CREDIT

25 RO 0 This end of the xlink has credit to allow it to transmit. TX_CREDIT

24 WO Clear this end of the xlink’s credit and issue a HELLO token. XLINK_HELLO

Reset the receiver. The next symbol that is detected will be the first
23 WO symbol in a token. XLINK_RX_RESET

22 RO - Reserved
Specify min. number of idle system clocks between two continuous
0x80: 21:11 RW 1 symbols witin a transmit token -1. XLINK_INTRA_TOKEN_DELAY

Link Control Specify min. number of idle system clocks between two continuous
and Status 10:0 RW 1 transmit tokens -1. XLINK_INTER_TOKEN_DELAY

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 XEF216-512-FB236 Datasheet

F USB PHY Configuration

The USB PHY is connected to the ports shown in section 10.

The USB PHY is peripheral 1. The control registers are accessed using 32-bit reads and
writes (use write_periph_32(device, 1, ...) and read_periph_32(device, 1, ...) for
reads and writes).

Number Perm Description Register identifier

0x00 WO UIFM reset GLX_PER_UIFM_RESET

0x04 RW UIFM IFM control GLX_PER_UIFM_CONTROL

0x08 RW UIFM Device Address GLX_PER_UIFM_DEVICE_ADDRESS

0x0C RW UIFM functional control GLX_PER_UIFM_FUNC_CONTROL

0x10 RW UIFM on-the-go control GLX_PER_UIFM_OTG_CONTROL

0x14 RO UIFM on-the-go flags GLX_PER_UIFM_OTG_FLAGS

0x18 RW UIFM Serial Control GLX_PER_UIFM_SERIAL_MODE

0x1C RW UIFM signal flags GLX_PER_UIFM_IFM_FLAGS

0x20 RW UIFM Sticky flags GLX_PER_UIFM_FLAGS_STICKY

0x24 RW UIFM port masks GLX_PER_UIFM_MASK

0x28 RW UIFM SOF value GLX_PER_UIFM_SOFCOUNT

0x2C RO UIFM PID GLX_PER_UIFM_PID

0x30 RO UIFM Endpoint GLX_PER_UIFM_ENDPOINT

0x34 RW UIFM Endpoint match GLX_PER_UIFM_ENDPOINT_MATCH

0x38 RW OTG Flags mask GLX_PER_UIFM_OTG_FLAGS_MASK

Figure 40: 0x3C RW UIFM power signalling GLX_PER_UIFM_PWRSIG

Summary 0x40 RW UIFM PHY control GLX_PER_UIFM_PHY_CONTROL

F.1 UIFM reset GLX_PER_UIFM_RESET 0x00

A write to this register with any data resets all UIFM state, but does not otherwise affect
the phy.

0x00: Bits Perm Init Description Identifier

UIFM reset 31:0 WO Value. ALL_BITS

F.2 UIFM IFM control GLX_PER_UIFM_CONTROL 0x04

General settings of the UIFM IFM state machine.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:8 RO - Reserved
7 RW 0 Set to 1 to enable XEVACKMODE mode. UIFM_IFM_CONTROL_XEVACKMODE

6 RW 0 Set to 1 to enable SOFISTOKEN mode. UIFM_IFM_CONTROL_SOFISTOKEN

5 RW 0 Set to 1 to enable UIFM power signalling mode. UIFM_IFM_CONTROL_PWRSIGMODE

4 RW 0 Set to 1 to enable IF timing mode. UIFM_IFM_CONTROL_IFTIMINGMODE

3 RO - Reserved
2 RW 0 Set to 1 to enable UIFM linestate decoder. UIFM_IFM_CONTROL_DECODELINESTATE
0x04:
UIFM IFM 1 RW 0 Set to 1 to enable UIFM CHECKTOKENS mode. UIFM_IFM_CONTROL_CHECKTOKENS

control 0 RW 0 Set to 1 to enable UIFM DOTOKENS mode. UIFM_IFM_CONTROL_DOTOKENS

F.3 UIFM Device Address GLX_PER_UIFM_DEVICE_ADDRESS 0x08

The device address whose packets should be received. 0 until enumeration, it should be
set to the assigned value after enumeration.

Bits Perm Init Description Identifier

0x08: 31:7 RO - Reserved

UIFM Device The enumerated USB device address must be stored here. Only packets
Address 6:0 RW 0 to this address are passed on. UIFM_DEVICE_ADDRESS_ADDRESS

F.4 UIFM functional control GLX_PER_UIFM_FUNC_CONTROL 0x0C

Bits Perm Init Description Identifier

31:5 RO - Reserved
4:2 RW 1 Set to 0 to disable UIFM to UTMI+ OPMODE mode. UIFM_FUNC_CONTROL_OPMODE

0x0C: Set to 1 to switch UIFM to UTMI+ TERMSELECT mode.

UIFM 1 RW 1 UIFM_FUNC_CONTROL_TERMSELECT

functional Set to 1 to switch UIFM to UTMI+ XCVRSELECT mode.

control 0 RW 1 UIFM_FUNC_CONTROL_XCVRSELECT

F.5 UIFM on-the-go control GLX_PER_UIFM_OTG_CONTROL 0x10

This register is used to negotiate an on-the-go connection.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

31:8 RO - Reserved
7 RW 0 Set to 1 to switch UIFM to EXTVBUSIND mode. UIFM_OTG_CONTROL_EXTVBUSIND

6 RW 0 Set to 1 to switch UIFM to DRVVBUSEXT mode. UIFM_OTG_CONTROL_DRVVBUSEXT

5 RO - Reserved
Set to 1 to switch UIFM to UTMI+ CHRGVBUS mode.
4 RW 0 UIFM_OTG_CONTROL_CHRGVBUS

Set to 1 to switch UIFM to UTMI+ DISCHRGVBUS mode.

3 RW 0 UIFM_OTG_CONTROL_DISCHRGVBUS

Set to 1 to switch UIFM to UTMI+ DMPULLDOWN mode.

2 RW 0 UIFM_OTG_CONTROL_DMPULLDOWN
0x10:
UIFM Set to 1 to switch UIFM to UTMI+ DPPULLDOWN mode.
on-the-go 1 RW 0 UIFM_OTG_CONTROL_DPPULLDOWN

control 0 RW 0 Set to 1 to switch UIFM to IDPULLUP mode. UIFM_OTG_CONTROL_IDPULLUP

F.6 UIFM on-the-go flags GLX_PER_UIFM_OTG_FLAGS 0x14

Status flags used for on-the-go negotiation

Bits Perm Init Description Identifier

31:6 RO - Reserved
5 RO 0 Value of UTMI+ Bvalid flag. UIFM_OTG_FLAGS_SESSVLDB

4 RO 0 Value of UTMI+ IDGND flag. UIFM_OTG_FLAGS_NIDGND

3 RO 0 Value of UTMI+ HOSTDIS flag. UIFM_OTG_FLAGS_HOSTDIS

0x14: 2 RO 0 Value of UTMI+ VBUSVLD flag. UIFM_OTG_FLAGS_VBUSVLD

UIFM
on-the-go 1 RO 0 Value of UTMI+ SESSVLD flag. UIFM_OTG_FLAGS_SESSVLD

flags 0 RO 0 Value of UTMI+ SESSEND flag. UIFM_OTG_FLAGS_SESSEND

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 XEF216-512-FB236 Datasheet

F.7 UIFM Serial Control GLX_PER_UIFM_SERIAL_MODE 0x18

Bits Perm Init Description Identifier

31:7 RO - Reserved
6 RO 0 1 if UIFM is in UTMI+ RXRCV mode. UIFM_SERIAL_MODE_RXRCV

5 RO 0 1 if UIFM is in UTMI+ RXDM mode. UIFM_SERIAL_MODE_RXDM

4 RO 0 1 if UIFM is in UTMI+ RXDP mode. UIFM_SERIAL_MODE_RXDP

3 RW 0 Set to 1 to switch UIFM to UTMI+ TXSE0 mode. UIFM_SERIAL_MODE_TXSE0

2 RW 0 Set to 1 to switch UIFM to UTMI+ TXDATA mode. UIFM_SERIAL_MODE_TXDAT

0x18: 1 RW 1 Set to 0 to switch UIFM to UTMI+ TXENABLE mode. UIFM_SERIAL_MODE_TXENN

UIFM Serial Set to 1 to switch UIFM to UTMI+ FSLSSERIAL mode.

Control 0 RW 0 UIFM_SERIAL_MODE_FSLSMODE

F.8 UIFM signal flags GLX_PER_UIFM_IFM_FLAGS 0x1C

Set of flags that monitor line and error states. These flags normally clear on the next
packet, but they may be made sticky by using PER_UIFM_FLAGS_STICKY, in which they
must be cleared explicitly.

Bits Perm Init Description Identifier

31:7 RO - Reserved
Set to 1 when the UIFM decodes a token successfully (e.g. it passes
6 RW 0 CRC5, PID check and has matching device address). UIFM_IFM_FLAGS_NEWTOKEN
5 RW 0 Set to 1 when linestate indicates an SE0 symbol. UIFM_IFM_FLAGS_SE0

4 RW 0 Set to 1 when linestate indicates a K symbol. UIFM_IFM_FLAGS_K

3 RW 0 Set to 1 when linestate indicates a J symbol. UIFM_IFM_FLAGS_J

Set to 1 if an incoming datapacket fails the CRC16 check.

2 RW 0 UIFM_IFM_FLAGS_CRC16FAIL
0x1C:
UIFM signal 1 RW 0 Set to the value of the UTMI_RXACTIVE input signal. UIFM_IFM_FLAGS_RXACTIVE

flags 0 RW 0 Set to the value of the UTMI_RXERROR input signal UIFM_IFM_FLAGS_RXERROR

F.9 UIFM Sticky flags GLX_PER_UIFM_FLAGS_STICKY 0x20

These bits define the sticky-ness of the bits in the UIFM IFM FLAGS register. A 1 means
that bit will be sticky (hold its value until a 1 is written to that bitfield), or normal, in which
case signal updates to the UIFM IFM FLAGS bits may be over-written by subsequent
changes in those signals.

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 XEF216-512-FB236 Datasheet

Bits Perm Init Description Identifier

0x20:
UIFM Sticky 31:7 RO - Reserved
flags 6:0 RW 0 Stickyness for each flag. UIFM_FLAGS_STICKY_STICKY

F.10 UIFM port masks GLX_PER_UIFM_MASK 0x24

Set of masks that identify how port 1N, port 1O and port 1P are affected by changes to
the flags in FLAGS

Bits Perm Init Description Identifier

Bit mask that determines which flags in UIFM_IFM_FLAG[6:0] con-
tribute to port 1?. If any flag listed in this bitmask is high, port 1? will be
31:24 RW 0 high. UIFM_FLAGS_MASK_MASK3

Bit mask that determines which flags in UIFM_IFM_FLAG[6:0] con-

tribute to port 1P. If any flag listed in this bitmask is high, port 1P will be
23:16 RW 0 high. UIFM_FLAGS_MASK_MASK2

Bit mask that determines which flags in UIFM_IFM_FLAG[6:0] con-

tribute to port 1O. If any flag listed in this bitmask is high, port 1O will
15:8 RW 0 be high. UIFM_FLAGS_MASK_MASK1

0x24: Bit mask that determines which flags in UIFM_IFM_FLAG[6:0] con-

UIFM port tribute to port 1N. If any flag listed in this bitmask is high, port 1N will
masks 7:0 RW 0 be high. UIFM_FLAGS_MASK_MASK0

F.11 UIFM SOF value GLX_PER_UIFM_SOFCOUNT 0x28

USB Start-Of-Frame counter

Bits Perm Init Description Identifier

31:11 RO - Reserved
0x28:
UIFM SOF 10:8 RW 0 Most significant 3 bits of SOF counter UIFM_SOFCOUNT_COUNT2

value 7:0 RW 0 Least significant 8 bits of SOF counter UIFM_SOFCOUNT_COUNT1

F.12 UIFM PID GLX_PER_UIFM_PID 0x2C

The last USB packet identifier received

Bits Perm Init Description Identifier

0x2C: 31:4 RO - Reserved

UIFM PID 3:0 RO 0 Value of the last received PID. UIFM_PID_PID

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 XEF216-512-FB236 Datasheet

F.13 UIFM Endpoint GLX_PER_UIFM_ENDPOINT 0x30

The last endpoint seen

Bits Perm Init Description Identifier

31:5 RO - Reserved
0x30:
UIFM 4 RO 0 1 if endpoint contains a valid value. UIFM_ENDPOINT_MATCH

Endpoint 3:0 RO 0 A copy of the last received endpoint. UIFM_ENDPOINT_ENDPOINT

F.14 UIFM Endpoint match GLX_PER_UIFM_ENDPOINT_MATCH 0x34

This register can be used to mark UIFM endpoints as special.

Bits Perm Init Description Identifier

0x34: 31:16 RO - Reserved

UIFM This register contains a bit for each endpoint. If its bit is set, the end-
Endpoint point will be supplied on the RX port when ORed with 0x10.
match 15:0 RW 0 UIFM_ENDPOINT_MATCH_MATCH

F.15 OTG Flags mask GLX_PER_UIFM_OTG_FLAGS_MASK 0x38

0x38:
OTG Flags Bits Perm Init Description Identifier
mask 31:0 RW 0 Data OTG_FLAGS_MASK_DEFINED

F.16 UIFM power signalling GLX_PER_UIFM_PWRSIG 0x3C

Bits Perm Init Description Identifier

31:9 RO - Reserved
0x3C:
UIFM power 8 RW 0 Valid UIFM_PWRSIG_VALID

signalling 7:0 RW 0 Data UIFM_PWRSIG_DATA

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 XEF216-512-FB236 Datasheet

F.17 UIFM PHY control GLX_PER_UIFM_PHY_CONTROL 0x40

Bits Perm Init Description Identifier

31:19 RO - Reserved
Set to 1 to disable pulldowns on ports 8A and 8B.
18 RW 0 UIFM_PHY_CONTROL_PULLDOWN_DISABLE

17:14 RO - Reserved
After an auto-resume, this bit is set to indicate that the resume sig-
nalling was for reset (se0). Set to 0 to clear.
13 RW 0 UIFM_PHY_CONTROL_RESUMESE0

After an auto-resume, this bit is set to indicate that the resume sig-
nalling was for resume (K). Set to 0 to clear.
12 RW 0 UIFM_PHY_CONTROL_RESUMEK

Log-2 number of clocks before any linestate change is propagated.

11:8 RW 0 UIFM_PHY_CONTROL_SE0FILTVAL

Set to 1 to use the suspend controller handle to resume from sus-

pend. Otherwise, the program has to poll the linestate_filt field in
7 RW 0 phy_teststatus. UIFM_PHY_CONTROL_AUTORESUME
0x40:
UIFM PHY 6:4 RW 0 Control the the conf1,2,3 input pins of the PHY. UIFM_PHY_CONTROL_PHYCONF

control 3:0 RO - Reserved

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 XEF216-512-FB236 Datasheet

G JTAG, xSCOPE and Debugging

If you intend to design a board that can be used with the XMOS toolchain and xTAG de-
bugger, you will need an xSYS header on your board. Figure 41 shows a decision diagram
which explains what type of xSYS connectivity you need. The three subsections below
explain the options in detail.

YES NO
Is debugging
required?

YES NO YES Does the SPI NO

Is xSCOPE flash need to be
required programmed?

YES NO
Is fast printf
required ?
Figure 41:
Decision
diagram for
the xSYS Use full xSYS header Use JTAG xSYS header No xSYS header required
header See section 3 See section 2 See section 1

G.1 No xSYS header

The use of an xSYS header is optional, and may not be required for volume production
designs. However, the XMOS toolchain expects the xSYS header; if you do not have an
xSYS header then you must provide your own method for writing to flash/OTP and for
debugging.

G.2 JTAG-only xSYS header

The xSYS header connects to an xTAG debugger, which has a 20-pin 0.1" female IDC
header. The design will hence need a male IDC header. We advise to use a boxed header
to guard against incorrect plug-ins. If you use a 90 degree angled header, make sure that
pins 2, 4, 6, ..., 20 are along the edge of the PCB.

Connect pins 4, 8, 12, 16, 20 of the xSYS header to ground, and then connect:

· TDI to pin 5 of the xSYS header

· TMS to pin 7 of the xSYS header

· TCK to pin 9 of the xSYS header

· DEBUG_N to pin 11 of the xSYS header

· TDO to pin 13 of the xSYS header

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 XEF216-512-FB236 Datasheet

The RST_N net should be open-drain, active-low, and have a pull-up to VDDIO.

G.3 Full xSYS header

For a full xSYS header you will need to connect the pins as discussed in Section G.2, and
then connect a 2-wire xCONNECT Link to the xSYS header. The links can be found in
the Signal description table (Section 4): they are labelled XL0, XL1, etc in the function
column. The 2-wire link comprises two inputs and outputs, labelled 1out , 0out , 0in , and 1in .
For example, if you choose to use XL0 for xSCOPE I/O, you need to connect up XL01out ,
XL00out , XL00in , XL01in as follows:

· XL01out (X0D43) to pin 6 of the xSYS header with a 33R series resistor close to the
device.

· XL00out (X0D42) to pin 10 of the xSYS header with a 33R series resistor close to the
device.

· XL00in (X0D41) to pin 14 of the xSYS header.

· XL01in (X0D40) to pin 18 of the xSYS header.

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 XEF216-512-FB236 Datasheet

H Schematics Design Check List

This section is a checklist for use by schematics designers using the
XEF216-512-FB236. Each of the following sections contains items to check
for each design.

H.1 Power supplies

The VDD (core) supply ramps monotonically (rises constantly) from 0V to

its final value (0.95V - 1.05V) within 10ms (Section 13).

The VDD (core) supply is capable of supplying 700 mA (Section 13 and Fig-
ure 23).

PLL_AVDD is filtered with a low pass filter, for example an RC filter, see Sec- .
tion 13

H.2 Power supply decoupling

The design has multiple decoupling capacitors per supply, for example at
least four0402 or 0603 size surface mount capacitors of 100nF in value, per
supply (Section 13).

A bulk decoupling capacitor of at least 10uF is placed on each supply (Sec-

tion 13).

H.3 Power on reset

The RST_N and TRST_N pins are asserted (low) until all supplies are good.
There is enough time between VDDIO power good and RST_N to allow any
boot flash to settle. RST_N is fast enough to meet USB timings.

H.4 Clock

The CLK input pin is supplied with a clock with monotonic rising edges and
low jitter.

Pins MODE0 and MODE1 are set to the correct value for the chosen oscilla-
tor frequency. The MODE settings are shown in the Oscillator section, Sec-
tion 7. If you have a choice between two values, choose the value with the
highest multiplier ratio since that will boot faster.

H.5 RGMII interface

This section can be skipped if you do not have any device connected to the RGMII inter-
face.

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 XEF216-512-FB236 Datasheet

RX_CLK will be low when the xCORE comes out of reset (see Section 11).

VDDIOT has a 2.5V or 3.3V supply as appropriate.

RGMII signals are connected to the appropriate RGMII pins of the xCORE
device.

H.6 Boot

X0D01 has a 1K pull-up to VDDIOL (Section 8).

The device is kept in reset for at least 1 ms after VDDIOL has reached its
minimum level (Section 8).

H.7 JTAG, XScope, and debugging

You have decided as to whether you need an XSYS header or not (Section G)

If you have not included an XSYS header, you have devised a method to
program the SPI-flash or OTP (Section G).

H.8 GPIO

You have not mapped both inputs and outputs to the same multi-bit port.

Pins X0D04, X0D05, X0D06, and X0D07 are output only and are, during and
after reset, pulled low or not connected (Section 8)

H.9 Multi device designs

Skip this section if your design only includes a single XMOS device.

One device is connected to a QSPI or SPI flash for booting.

Devices that boot from link have, for example, X0D06 pulled high and have
link XL0 connected to a device to boot from (Section 8).

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 XEF216-512-FB236 Datasheet

I PCB Layout Design Check List

This section is a checklist for use by PCB designers using the XS2-UEF16B-
512-FB236. Each of the following sections contains items to check for each
design.

I.1 Ground Plane

Each ground ball has a via to minimize impedance and conduct heat away
from the device. (Section 13.4)

Other than ground vias, there are no (or only a few) vias underneath or
closely around the device. This create a good, solid, ground plane.

I.2 RGMII interface

This section can be skipped if you do not have any device connected to the RGMII inter-
face.

The RGMII traces are length and impedance matched.

I.3 Power supply decoupling

The decoupling capacitors are all placed close to a supply pin (Section 13).

The decoupling capacitors are spaced around the device (Section 13).

The ground side of each decoupling capacitor has a direct path back to the
center ground of the device.

I.4 PLL_AVDD

The PLL_AVDD filter (especially the capacitor) is placed close to the

PLL_AVDD pin (Section 13).

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 XEF216-512-FB236 Datasheet

J Associated Design Documentation

Document Title Information Document
Estimating Power Consumption For
XS1-UEF Devices Power consumption
Timers, ports, clocks, cores and
XMOS Programming Guide channels Link
Compilers, assembler and
xTIMEcomposer User Guide linker/mapper Link
Timing analyzer, xScope, debugger
Flash and OTP programming utilities

K Related Documentation

Document Title Information Document

xCORE200: the XMOS XS2 Architecture ISA manual Link
I/O timings for xCORE200 Port timings Link
xCONNECT Architecture Link, switch and system information Link
XS1-UEF Link Performance and Design
Guidelines Link timings
xCORE-200 Clock Frequency Control Advanced clock control Link

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 XEF216-512-FB236 Datasheet

L Revision History

Date Description
2015-03-20 Preliminary release
2015-04-14 Added RST to pins to be pulled hard, and removed reference to TCK from Errata
Removed TRST_N references in packages that have no TRST_N
New diagram for boot from embedded flash showing ports
Pull up requirements for shared clock and external resistor for QSPI
2015-05-06 Removed references to DEBUG_N
2015-07-09 Updated electrical characteristics - Section 14
2015-08-19 Added I(USB_VDD) - Section 14
Added USB layout guidelines - Section 13
2015-08-27 Updated part marking - Section 16
2016-04-20 Typical internal pull-up and pull down current diagrams added - Section 14
Updated USB VBUS wiring description with bus-powered usb-device instructions - Sec-
2017-02-02 tion 10
Clarified available RGMII ports/pins - Section 11
2017-09-19 Added Absolute Maximum Ratings - Section 14.1
Reference document links updated - Section J
2018-03-23 Incorrect IDCODE return value updated - Section 12
Incorrect VBUS signal name updated to GND in USB diagrams - Section 10
2020-10-05 Released documentation for A revision that uses different flash - Section 8

Copyright © 2020, All Rights Reserved.

Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing
it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos
Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any
claims of infringement and again, shall have no liability in relation to any such claims.

XMOS, xCore, xcore.ai, and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other
countries and may not be used without written permission. Company and product names mentioned in this document
are the trademarks or registered trademarks of their respective owners.

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