ISSCC 2024 / SESSION 1 / PLENARY / 1.

1
1.1 Semiconductor Industry: Present & Future substantially improving the electrostatics of the transistor. Today, the industry continues
the scaling of transistor dimensions by transitioning to nanosheet devices. This
Kevin Zhang progression in lithography and device architecture, new materials, integration schemes,
and novel features will continue to drive the scaling of future products in power,
performance, and area (PPA) for each technology generation.
Senior Vice President of Business Development & Overseas Operations Office
Looking into the future, vertically stacking an nFET and a pFET to create what is known
TSMC, Hsinchu, Taiwan as CFET could provide significant density scaling benefits. Beyond CFET, low dimensional
channel materials could enhance further dimensional and energy efficiency scaling
Abstract (Figure 1.1.3).
Semiconductors are the foundation of today’s digital economy and powering innovations
that will shape the trajectory of human history. This paper highlights the latest progress
2024 IEEE International Solid-State Circuits Conference (ISSCC) | 979-8-3503-0620-0/24/$31.00 ©2024 IEEE | DOI: 10.1109/ISSCC49657.2024.10454358

In addition to process innovations, DTCO has become a key to extracting maximum

of the semiconductor industry to support a vast spectrum of applications that have values by tailoring technology definition to address specific product design optimization.
forever changed our lives. It gives insight into the paths of continued advanced As shown in Figure 1.1.4, using fin depopulation to reduce the standard logic cell height
technology scaling, the essential role of design-technology co-optimization (DTCO), and is an effective approach to improve product PPA [6][7][8]. After fin depopulation reached
how system-level integration will elevate system performance to new heights. The 2-fin per standard cell [9], one further step was taken by creating a hybrid architecture
advancements of semiconductors will enable many new innovations in artificial by interweaving 2-fin and 1-fin standard cells to push for PPA optimization [10][11].
intelligence (AI), high-performance computing (HPC), wireless connectivity, and These techniques help to scale the vertical dimension of a standard cell. To scale the
autonomous driving. The paper also provides the trend of technologies ranging from horizontal dimension, in addition to contact poly pitch (CPP) reduction, the white space
low-power and Edge AI devices to cloud based computing. By harnessing the new between standard cells has been a key focus, moving from double diffusion break [6] to
capabilities of semiconductors, these innovations will greatly improve productivity, continuous diffusion [9] to single diffusion break [11]. Gate contact over active region
efficiency, safety, as well as sustainability. The semiconductor industry is indeed is another effective way to reduce the horizontal dimension of complex standard cells
experiencing a “golden era” in spurring remarkable economic growth and unleashing by allowing more flexible gate pick-up locations and signal connections [9].
innovations to create a better future for society.
The on-die static random-access memory (SRAM) cache has always been a key to
1.0 Introduction support growing compute performance in mobile, CPU, GPU, AI, and HPC. CMOS scaling
The semiconductor industry is the bedrock of modern technological advancements, over the past two decades has reduced SRAM bit cell area by nearly 100 times, from
powering devices and systems that are integral to modern life. With continuous 130nm to 3nm nodes, as shown in Figure 1.1.5.
innovations, the industry today is progressing forward to create new technologies that
power the rapid growth for future applications. DTCO has played a key role in enhancing the 3nm SRAM performance. For example, the
negative bit-line (NBL) write-assist technique is applied to lower SRAM Vmin by over
1.1 Market Outlook 300mV for HD SRAM (Figure 1.1.6). To address the increasing memory performance
The long-term growth trajectory of semiconductor demand, underpinned by multi-year demands in future compute workloads, system-technology co-optimization (STCO) of
5G, AI, and HPC megatrends, remains strong and undeterred by cyclical and SRAM design and cache memory architecture has become essential. A 3D-chip stacking
macroeconomic challenges. It is projected that the following four segments account for technology attaching cache memory on top of high-performance processors offers
95% of this near trillion-dollar business: HPC accounts for 40% of demand, followed by significant bandwidth and power benefits and has been employed in HPC products [12].
smartphones at 30%, automotive at 15%, and Internet of Things (IoT) at 10% (Figure
1.1.1). With continuous technology advances as described above, great strides have been made
to improve PPA over the past decade. Using power efficiency as the metric and 28nm
1.2 Emerging Applications planar technology as a reference, FinFET technology, starting from 16nm to the latest
For HPC applications, AI has rapidly emerged as the key growth driver forward. The 3nm generation, has provided more than 10× improvement as shown on the left chart in
complexity of leading-edge large language models (LLMs) for generative AI is increasing Figure 1.1.7. If density benefits are included, then the technology advancement from
rapidly, and its computing requirements are going up exponentially: >10,000× in less 28nm to 3nm brings over 80× improvement in Perf/Watt/mm2 in just slightly over a
than 2 years [1]. The energy requirements and carbon footprint to train and run these decade, as shown on the right chart in Figure 1.1.7. This has enabled product innovations
models are becoming very significant [2]. Clearly, AI advances in the energy efficiency to flourish in AI/HPC, mobile, IoT, and automotive applications as detailed in the next
of computing hardware are vital to enable future growth. few sections.

Wireless communications continue to evolve across several parameters. Faster speeds 3.0 Technologies for HPC and AI
and larger bandwidth support growing demand for data-intensive applications such as Beside process innovations being discussed in the previous section, there are domain-
video streaming, online gaming, and virtual reality (VR). Advanced protocols and specific process optimizations that can further improve the HPC computing platform.
standards improve wireless network reliability and coverage. Lower latency enables real- For CPUs, for example, overdrive or increasing VDD has been an effective technique for
time communication, such as autonomous vehicles and telemedicine. All the above will pushing higher performance. However, significant power increases occur to achieve
drive both high-performance radio frequency (RF) capabilities and low-power computing single-digit percent frequency improvement. By optimizing transistor design for higher
needs. voltages than nominal conditions beyond the baseline technology, an HPC-optimized
N4X process [13] demonstrated significant speed improvement at overdrive with very
Four megatrends (Connected, Autonomous, Shared & Services, and Electrification) are limited leakage increase.
driving the semiconductor growth in the automotive industry. The digital transformation
is enabling smarter, safer, and greener cars. The next generation of central compute and Beyond advanced process technology development at the chip level, advanced packaging
zonal electrical/electronic architecture will also play a vital role in software-defined and integration have become increasingly important to achieve system-level
vehicles that require high-performance compute SoCs, sensors, networking, and RF performance. Figure 1.1.8 illustrates an overall view of what the most important elements
connectivity [3]. are for HPC system optimization. These include advanced packaging technologies for
the integration of more compute resources, memory and logic integration to address
For IoT, more diversified wireless connectivity technologies for various types of memory bandwidth, power delivery optimization beyond on-die capacitors, as well as
connected devices, covering both short- and long-range radios are required, while low- addressing the I/O bottleneck with silicon photonics and co-packaged optics (CPO).
leakage and switching power put more stringent requirements on underlying
semiconductor technologies. Various advanced packaging and chip-level integration solutions have been developed
over the years, including CoWoS® [14], InFO [15], and SoIC [16]. These integration
2.0 Advanced Technology Scaling schemes can integrate over 500 billion transistors in a packaged system [17]. 3D SoIC
Semiconductor process technology has undergone a significant evolution over the past and CoWoS® technologies have enabled a state-of-the-art advanced AI accelerator
decades, a trend that will continue well into the future, as summarized in Figure 1.1.2. product that has been recently introduced by AMD, MI300X, with 153 billion transistors
Lithography progressed from single-pattern immersion to double-patterning, to double- (Figure 1.1.9) [18].
patterning with self-aligned features, in order to print increasingly smaller critical
dimensions (CD). Now lithography has well entered the EUV era where the pitch scaling To achieve future system scaling and performance, it is critical to improve 3D chip-to-
continues. Device architecture migrated from planar [4] to FinFET at the 16nm node [5], chip interconnect density [19]. Over the past decades, interconnect density among chips
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 ISSCC 2024 / February 19, 2024 / 8:50 AM
within a package has advanced rapidly. Advanced silicon stacking and packaging 5.0 Automotive and MCU
technologies, including SoIC, InFO, and CoWoS®, continue to aggressively scale down Automotives is going through some fundamental transformations enabled by many 1
the chip-to-chip interconnect pitch, offering the potential to improve 3D interconnect underlying semiconductor technologies, ranging from powerful processors, more
density by another six orders of magnitude. These advanced integration capabilities advanced microcontrollers (MCUs), and a new class of power devices.
enhance data transfer rates, reduce latency, optimize power consumption, and elevate
the overall performance of computing systems (Figure 1.1.10). Automotive processors have emerged as a distinct class of ICs as system requirements
have evolved from simple MCUs to sophisticated SoCs inside a car. Such SoCs are for
Efficient power delivery is another crucial factor in enabling high-performance infotainment, advanced driving assistance systems (ADAS), and Al-workload intensive
applications. Power delivery technologies have been developed to enable efficient autonomous driving (AD) systems. These SoCs require more powerful CPUs, GPUs,
distribution across the die and across the package. A SHDMiM (super high-density and NPUs, while meeting stringent power consumption requirements to limit cooling
metal-insulator-metal) capacitor can be integrated on-die or embedded within the and extend EV driving range. At the same time, the mission profile requires these SoCs
CoWoS® interposers to improve power delivery within the package. Other technologies to operate for a longer period, at higher temperatures, and at a quality level with “zero
such as embedded deep trench capacitor (eDTC) in larger (2,500mm2 interposer size) defect” [33]. Consequently, efficient computing at automotive grade reliability is a
CoWoS® modules [20][21][22], capacitors over active logic layers, and integrated paramount characteristic of automotive processors. As a result, they require specific
voltage regulators improve power delivery and reduce noise to enhance the process technology tailored to meet the performance, power, and reliability
performance of next-generation systems or modules. requirements for auto applications. Automotive grade advanced logic technologies have
been developed in 16nm, 7nm, and 5nm, meeting automotive Grade-1 reliability and
Finally, many HPC workloads can be I/O bounded. The demand for HPC and data- automotive’s low defect parts per million (DPPM) requirements. And the adoption of
intensive applications continues to grow. High-speed SerDes designs are essential for advanced nodes is being accelerated at 3nm as more products require higher
transmitting large amount of data efficiently. High speed signaling for data center performance and more energy efficient compute [34].
applications will require a data rate of higher than 224Gbits/s [23][24]. However,
achieving high-speed links at this rate poses two primary challenges: power efficiency MCUs have served many critical auto functions for generations. The key technology
and signal integrity, especially when dealing with an insertion loss up to 35-40dB. To requirement for MCU is embedded non-volatile memory (eNVM). With the continuous
maintain power efficiency better than 5pJ/bit, equalization requires complex circuits. technology scaling, the conventional floating-gate based eNVM has run out of room in
CPO is expected to offer better bandwidth density and energy efficiency beyond 224Gb/s both cost and complexity. Now the new eNVM technologies based on MRAM [35] and
[25]. With CPO, photonics can be integrated close to the computing SoC, providing RRAM [36] have emerged as the replacement with the full compatibility with advanced
energy efficiency comparable to electrical I/O, but with a longer reach. CPO is expected logic. The new eNVMs shall help accelerate the technology scaling to address the new
to bring over 170× speed but only consume 20% of copper wire interconnect power architecture requirements for future automotives.
(Figure 1.1.11). Additionally, optical channels are more scalable than electrical ones,
as data can be carried in multi-wavelengths or multi-mode fibers and then multiplexed 6.0 Technologies for Sensors and Display
into a signal fiber [26][27][28]. Image sensors and display have fundamentally changed how people communicate and
share information. The integration of the digital camera with the smartphone has
4.0 Technologies for Mobile
revolutionized the way we document our lives. People can now capture precious
Moving into the fifth decade since the wireless revolution of the 1980s, wireless
moments in their lives and share them with their loved ones instantly. Billions of image
connectivity has become a standard feature for mobile devices and most IoT devices.
sensors are being built annually, with trillions of photos taken by these sensors. There
According to Cisco’s analysis [29], 71% of the edge IP traffic came from wireless
were about 1.5 trillion photos taken worldwide in 2022 (Figure 1.1.13) [37] [38].
connection in 2022 and this ratio will continue to grow. With constrained battery
capacity, energy efficiency continues to be the paramount requirement in technology
What makes this possible is the advancements in sensing technologies, from single
optimizations for mobile applications to extend battery life, a critical user experience
backside illuminated sensor to multi-wafer stacked backside illuminated sensor (Figure
factor.
1.1.14).
4.1. Mobile SoC
By separating photodiodes (PDs) and pixel transistors on various silicon layers or
Mobile SoC with integrated application processors (AP) and cellular modem continues
wafers, designers have more room to optimize pixel performance, while pixel size gets
to evolve. While achieving faster link speeds, lower latency, and better energy efficiency
scaled down further. The 2-layer pixel structure increases full well capacity (FWC) and
remain essential, the rise of Edge AI technologies for AI-assisted 5G and potentially AI-
native 6G inspires the integration of dedicated AI accelerators or neural processing reduces readout noise (RN) by accessing more silicon area in a limited pixel size (Figure
units (NPUs) in mobile SoCs to bring user experience to the next level with features 1.1.15) [39]. Also, the 3-wafer stacked backside illuminated structure significantly
such as facial recognition, photo enhancement, language processing, and real-time improves the voltage-domain global shutter (VDGS) sensor footprint with a better
scene analysis. All the new and growing compute needs continue to drive product integration of pixel, storage, readout, and processing circuits (Figure 1.1.16). This
technology migration to more advanced process nodes. small-footprint CMOS image sensor (CIS) is critical for augmented reality (AR)/VR
applications [40].
4.2 Cellular RF
Mobile RF TRX chip architecture is experiencing an evolution in recent years. To AR/VR are designed to provide an immersive experience. They require near-eye display
accommodate the growing number of 5G-NR bands globally with wider bandwidth and technology with much higher resolution over several thousand pixels per inch. μDisplay-
the corresponding complex carrier aggregation combinations, the recent TRX chip on-Silicon technology can deliver up to 10× pixel density to achieve the high resolution
described in [30] integrates 3 transmitters and 20 receivers. The significantly increased needed for near-eye display. Display technology and silicon are merging for future
buffer/driver power consumption in mobile RF TRX due to the growth of interface ports applications. To achieve ultra-low power needs and smaller pixel sizes, the driver or
between RF TRX and mobile SoC drove the mobile architecture innovations. As shown high voltage (HV) technology is now being scaled down to more advanced nodes to
in Figure 1.1.12, data converters located in 4G mobile SoC were moved to the 5G-NR address this new class of application.
RF TRX and Serdes PHY supporting fast data rate were added to consolidate and
simplify the connection interface digitally. This architecture change led to a significant 7.0 Summary
digital content growth of mobile RF TRX, which led the technology migration of mobile We are at the start of the next golden age of semiconductor innovation. From the
RF TRX from 28nm technology to 12nm FinFET in order to harvest digital PPA scaling economics perspective, semiconductor technology has a multiplier effect on various
benefit for power-sensitive 5G devices [30][31]. Moving to the next generation, 6G is sectors, amplifying the value chain and propelling the continued growth of the world
expected to deliver further application expansion with better power efficiency, faster economy (Figure 1.1.17). It is expected that the total foundry revenue will reach around
and more stable data speed under broader usage conditions [32]. The growing trend US$250 billion by 2030, driving an approaching US$1 trillion semiconductor market,
of TRX die area and power consumption tends to continue for 6G TRX with more TRX and supporting a US$3 trillion electronics market and a US$12 trillion information
channels to cover increasing frequency bands, especially in FR3 (7-24GHz) and with technology industry [41][42].
more digital contents to perform instant connection controls (for example, complex
carrier aggregation for data speed and fine duty cycling for power reduction). Further The semiconductor industry will push digital transformation through innovative IC
technology migration for 6G TRX to advanced RF technology (for example, 6nm RF designs that unleash amazing features and enhance powerful computation in a faster,
technology), with superior RF and analog device performance and excellent digital PPA more power- and cost-efficient way. Innovation and continuous advancement in
scaling, will be an essential step for market leaders to capture the business opportunity semiconductors are vital to solving our challenges, enriching our lives, and creating a
at the coming transition. better world in the future.
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DIGEST OF TECHNICAL PAPERS • 11
ISSCC 2024 / SESSION 1 / PLENARY / 1.1
Acknowledgement: [21] S. Y. Hou, C. H. Lee, T. -D. Wang, H. C. Hou and H. -P. Hu, “Supercarrier
Many of my TSMC colleagues have contributed to this paper. I would like to extend my Redistribution Layers to Realize Ultra Large 2.5D Wafer Scale Packaging by CoWoS,”
deep gratitude to George Chang, Bryan Chen, Richard Chung, Kenny Hsieh, Bryan Hsu, 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando,
Cheng-I Huang, Y.T. Kuo, Weiyen Kuo, Yujun Li, Jimmy Lin, Cho-Ying Lu, Eric Pan, Jie FL, USA, 2023, pp. 510-514
Jay Sun, Michael I-Shan Sun, Jammy Swee-Han Teh, Jerry Tzou, Michael Wang, Yih [22] Yu-Chen Hu et al., “CoWoS Architecture Evolution for Next Generation HPC on 2.5D
Wang, Jason C.C. Wang, Ann Yiyun Yang, and Lipen Yuan. System in Package“, 2023 IEEE 73rd Electronic Components and Technology Conference
(ECTC), pp. 1022-1026
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12 • 2024 IEEE International Solid-State Circuits Conference 979-8-3503-0620-0/24/$31.00 ©2024 IEEE
 ISSCC 2024 / February 19, 2024 / 8:50 AM


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Figure 1.1.5: SRAM bit cell area is reduced by ~100× through extensive design-technology Figure 1.1.6: Negative bit-line write-assist technique lowers VMIN of 3nm HD SRAM by
co-optimization (DTCO) in the last two decades. 300mV.
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DIGEST OF TECHNICAL PAPERS • 13
 ISSCC 2024 / SESSION 1 / PLENARY / 1.1

       


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Figure 1.1.7: Technology advancement enables energy-efficient compute. Figure 1.1.8: Holistic system-level optimization.

 

 




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Figure 1.1.10: 3D silicon stacking and advanced packaging technologies can enable another
Figure 1.1.9: Innovation beyond chip level is a must. 106 X I/O density increase.

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Figure 1.1.11: Silicon photonics is the best option for co-packaged optics (CPO). Figure 1.1.12: 5G evolution driving system architecture renovation and technology migration.
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14 • 2024 IEEE International Solid-State Circuits Conference 979-8-3503-0620-0/24/$31.00 ©2024 IEEE
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Figure 1.1.13: Number of photos taken per year. Figure 1.1.14: CMOS image sensor (CIS) evolution.

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Figure 1.1.15: Single layer pixel vs. 2-layer pixel. (CIS).

   



 
    




  
  
 


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Figure 1.1.17: Semiconductor: The enabler to power global economy.

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DIGEST OF TECHNICAL PAPERS • 15