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TD Digital Synthesis of Basic Component Using VHDL-Enoncé+Solution

The document outlines various VHDL exercises including the implementation of basic logic gates (AND, OR, NOT), half adder, full adder, 4-bit binary adder, and multiplexers. It provides detailed VHDL code for each component and describes their architectures, including data flow and structural descriptions. Additionally, it covers decoder implementation and a 7-segment display decoder.

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28 views10 pages

TD Digital Synthesis of Basic Component Using VHDL-Enoncé+Solution

The document outlines various VHDL exercises including the implementation of basic logic gates (AND, OR, NOT), half adder, full adder, 4-bit binary adder, and multiplexers. It provides detailed VHDL code for each component and describes their architectures, including data flow and structural descriptions. Additionally, it covers decoder implementation and a 7-segment display decoder.

Uploaded by

mobilepub610
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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TD Digital Synthesis of basic component using VHDL

Exercise 1: Basic Gates Implementation


Implement basic logic gates (AND, OR, NOT) using VHDL. Write a VHDL module for each gate
with two inputs and one output.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NON is
Port ( INA1 : in STD_LOGIC; -- NOT gate input
OA : out STD_LOGIC; -- NOT gate output
end NON;

architecture Behavioral of NON is


begin
OA <= not(INA1);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ET_2 is
Port ( A1 : in STD_LOGIC; -- AND gate input
A2 : in STD_LOGIC; -- AND gate input
X1 : out STD_LOGIC; -- AND gate output
end ET_2;

architecture Behavioral of ET_2 is


begin
OA <= A1 and A2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ou_2 is
Port ( B1 : in STD_LOGIC; -- OR gate input
B2 : in STD_LOGIC; -- OR gate input
Y1 : out STD_LOGIC; -- OR gate output
end OU_2;

architecture Behavioral of ou_2 is


1
begin
Y1 <= B1 or B2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NON_ET_2 is
Port ( A1 : in STD_LOGIC; -- NAND gate input
A2 : in STD_LOGIC; -- NAND gate input
X1 : out STD_LOGIC; -- NAND gate output
end NON_ET_2;

architecture Behavioral of NON_ET_2 is


begin
X1<= A1 nand A2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EXLUS_2 is
Port ( INA1 : in STD_LOGIC; -- XOR gate input
INA2 : in STD_LOGIC; -- XOR gate input

OA : out STD_LOGIC; -- XOR gate output


end EXLUS_2;

architecture Behavioral of EXLUS_2 is


begin
X1 <= A1 xor A2;
end Behavioral;

Exercise 2: Half Adder Circuit


Design a half adder circuit in VHDL. The full adder should have two inputs (A, B) and two
2
outputs (Sum and Cout).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder is
port ( a,b : in std_logic;
sum,cout: out std_logic
);
end half_adder;
architecture adder_arch of half_adder is
begin
sum <= a xor b;
cout <= a and b;
end adder_arch;

Exercise 3: Full Adder Circuit


Design a full adder circuit in VHDL. The full adder should have three inputs (A, B, and Carry-
in) and two outputs (Sum and Carry-out).
a- using data flow description
b- Using Structural description (with gates).
c- Using Structural description (with half_adder).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder is
port ( a,b : in std_logic;
sum,cout: out std_logic
);
end half_adder;
architecture adder_arch of half_adder is
begin
sum <= a xor b;
cout <= a and b;
end adder_arch;

b-
library IEEE;
Use IEEE. STD_LOGIC_1164.all;

entity fulladder IS
port (a,b,cin :in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladder;

3
——————————architecture of full adder——————-
architecture structural1 of fulladder is
———————OR gate component————————-
component OU-3 is
port (a,b,c : in STD_LOGIC; z: out STD_LOGIC); -- à décrire en utilisant z <= a or b or c;
end component;
———————Xor gate component————————-
component EX-2 is
port (a,b : in STD_LOGIC; z: out STD_LOGIC); -- décrit et compile déjà exercice 1
end component;
———————AND gate component————————-
component ET-2 is
port (a,b : in STD_LOGIC; z: out STD_LOGIC); -- décrit et compile déjà exercice 1
end component;
——————————-
signal x1,x2,x3,x4 : STD_LOGIC;
begin
w1: Ex_2 port map (a,b,x1);
w2: Ex_2 port map (cin,x1,sum);
w3: ET_2 port map (a,b,x2);
w3: ET_2 port map (a,cin,x3);
w4: ET_2 port map (b,cin,x4);
w5: OU_3 port map (x2,x3,x4, cout);
end structural1;

c-
library IEEE;
Use IEEE. STD_LOGIC_1164.all;

entity fulladder IS
port (a,b,cin :in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladder;

architecture structural2 of fulladder is

component half_adder is
port (a,b :in STD_LOGIC; -- décrit déjà exercice-1
sum,cout: out STD_LOGIC);
end component;

component OU_2 is
port (b1,b2 :in STD_LOGIC; -- décrit déjà exercice-1
y1: out STD_LOGIC);
end component;

signal s1,c1,c2 : STD_LOGIC;


begin
stage0: half_adder port map (s1,cin,sum,c2);
stage1: half_adder port map (a,b,s1,c1);
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stage2: OU_2 port map (c1,c2,carry);

end structural2;

Exercise 4: 4-bit Binary Adder


Design a 4-bit binary adder in VHDL. The adder should take two 4-bit inputs (A and B) and
produce a 4-bit sum output (S) and a carry-out (C_out).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Adder_4bits is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (4 downto 0));
end Adder_4bits;

architecture structural of Adder_4bits is

-- Full Adder VHDL Code Component Decalaration


component fulladder
Port ( A, B, Cin: in STD_LOGIC;
sum,carry: out STD_LOGIC);
end component;

-- Intermediate Carry declaration


signal c1,c2,c3: STD_LOGIC;

5
begin

-- Port Mapping Full Adder 4 times


FA1: fulladder port map( A(0), B(0), Cin, S(0), c1);
FA2: fulladder port map( A(1), B(1), c1, S(1), c2);
FA3: fulladder port map( A(2), B(2), c2, S(2), c3);
FA4: fulladder port map( A(3), B(3), c3, S(3), S(4));

end structural;

Exercise 5: Multiplexer Design

Create a 2-to-1 multiplexer using VHDL. The multiplexer should have

two data inputs, two select lines, and one output.


a- Data flow description
b- using when...else
c- Using with.....select

⦁
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux2x1 is
port( A,B,S: in std_logic; F: out std_logic);
end Mux2x1;

architecture Dataflow of Mux2x1 is


begin
F <= ((not S) and A) or (S and B);
end Dataflow;

⦁
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2to1 is
Port ( SEL : in STD_LOGIC;

6
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
X : out STD_LOGIC_VECTOR (3 downto 0));
end mux_2to1;

architecture Behavioral of mux_2to1 is


begin
X <= A when (SEL = '1') else B;
end Behavioral;

⦁
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2to1 is
Port ( SEL : in STD_LOGIC_VECTOR; -- select input
A , B : in STD_LOGIC; -- inputs
X : out STD_LOGIC); -- output
end mux_2to1;

architecture Behavioral of mux_2to1is


begin
with SEL select
X <= A when ‘0’,
'0' when others;
end Behavioral;

Create a 4-to-1 multiplexer using VHDL. The multiplexer should have four data inputs, two
select lines, and one output.
⦁ using when...else

entity Mux4x1 is
port( A,B,C,D: in std_logic;
S: in std_logic_vector(1 downto 0);
F: out std_logic);
end Mux4x1;

architecture when_else of Mux4x1 is

Begin
F<= A WHEN S = "00"
else B WHEN S = "01"
else C WHEN S = "10"
else D when S = "10"
else ‘z’ when others;
end when_else;

7
⦁ Using with.....select

entity Mux4x1 is
port( A,B,C,D: in std_logic;
S: in std_logic_vector(1 downto 0);
F: out std_logic);
end Mux4x1;

architecture with_select of Mux4x1 is

Begin
with S select
F <= A when ”00”,
B when ”01”,
C when ”10”,
D when ”11”,
'z' when others;
end when_else;

⦁ Using Structural description ( 2-to-1multiplxer).

f-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux4x1 is
port( A,B,C,D: in std_logic;
S: in std_logic_vector(1 downto 0);
F: out std_logic);
end Mux4x1;

architecture Structural of Mux4x1 is


component Mux_2to1 is port( SEL, A,B: in std_logic; x: out std_logic);
end component;

8
Signal F1, F2: std_logic;
Begin
M1: mux_2to1 port map(S(0),A,B,F1);
M2: mux_2to1 port map(S(0),C,D,F2);
M3: mux_2to1 port map(S(1),F1,F2,F);
end Structural;
Exercise 6: Decoder Implementation
Implement a 2-to-4 decoder in VHDL. The decoder should have two input bits and four
output lines, where each output line corresponds to one of the possible input combinations.

Library ieee;
Use ieee.std_logic_1164.all;
ENTITY Decode2to4 is
PORT ( S : OUT STD_LOGIC_VECTOR (3 downto 0);
E : IN STD_LOGIC_VECTOR (1 downto 0));
END Decode2to;
ARCHITECTURE combinatoire OF Decode2to4 IS
BEGIN
S <= "0001" WHEN E = "00"
else "0010" WHEN E = "01"
else "0100" WHEN E = "10"
else "1000" when others;
END combinatoire;

Exercise 7: 7-Segment Display Decoder


Develop a VHDL module for a 7-segment display decoder. The module should take a 4-bit
binary input and output the corresponding 7-bit code to display the number on a 7-segment
LED display.
a- using when...else
b- Using with.....select

VOIR REPONSE SUR LE MANUEL DU TP


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2to1 is
Port ( SEL : in STD_LOGIC; -- select input
A , B : in STD_LOGIC; -- inputs
X : out STD_LOGIC); -- output
end mux_2to1;

architecture Behavioral of mux_2to1 is


begin
with SEL select
X <= A when '0',

9
b when '1' ;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux2x1 is
port( A,B,S: in std_logic; F: out std_logic);
end Mux2x1;

architecture Dataflow of Mux2x1 is


begin
F <= ((not S) and A) or (S and B);
end Dataflow;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2to1_vecteur is
Port ( SEL : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
X : out STD_LOGIC_VECTOR (3 downto 0));
end mux_2to1_vecteur;

architecture Behavioral of mux_2to1_vecteur is


begin
X <= A when (SEL = '1') else B;
end Behavioral;

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