2024 Second International Conference on Networks, Multimedia and Information Technology (NMITCON)

Design Of Analog Comparator For Low Power

2024 Second International Conference on Networks, Multimedia and Information Technology (NMITCON) | 979-8-3503-7289-2/24/$31.00 ©2024 IEEE | DOI: 10.1109/NMITCON62075.2024.10698830

Application Utilizing 250nm Technology

1st Kiran Kumar V.G. 2nd Harshith Poojary 3rd Prashanth S.M
A J Institute of Engineering and A J Institute of Engineering and A J Institute of Engineering and
Technology Technology Technology
Mangalore, India Mangalore, India Mangalore, India
[email protected] [email protected] [email protected]

4th Amal Dominic 5th Muhammed Rabeeh Rahman

A J Institute of Engineering and A J Institute of Engineering and
Technology Technology
Mangalore, India Mangalore, India
[email protected] [email protected]

Abstract— Analog comparators play a crucial role in electronic regard, optimizing analog comparators for low power
systems by facilitating accurate voltage comparisons, enabling becomes critical, particularly in the era of energy-efficient
various functions from simple voltage detection to complex electronics and battery-operated gadgets. It becomes
analog-to-digital conversion. The transition to smaller process imperative to employ tactics like sub-threshold operation,
nodes like 250nm CMOS presents both opportunities and dynamic voltage scaling (DVS) [6], and cautious biasing in
challenges in analog comparator design, emphasizing the need order to achieve low-power [7] devices without sacrificing
for low-power optimization. This paper explores the performance. Furthermore, with tools like the Mentor
importance, challenges, and design considerations of analog Graphics suite offering an extensive platform for schematic
comparators, particularly in the context of low-power design
extraction, transistor sizing, biasing optimization, layout
methodologies. Leveraging tools like the Mentor Graphics suite,
designers can implement advanced techniques such as sub-
design, and post-layout verification, considerations for noise
threshold operation and dynamic voltage scaling to achieve immunity, stability, and speed remain crucial throughout the
high-performance, energy-efficient analog comparators. This design process. By combining cutting-edge technology with
paper Comparing other similar papers for the comparison of the rigorous design processes, it is now possible to create high-
avg power consumption. The paper highlights the significance performance, low-power analog comparators [9], which is
of noise immunity, stability, and layout optimization in ensuring essential for the development of contemporary electronics.
reliable circuit operation. Ultimately, the creation of low-power This introduction lays the groundwork for a thorough
analog comparators is essential for meeting the demands of examination of the complex field of analog comparator
modern electronics, and this paper provides a comprehensive design, including its importance, difficulties, and design
overview of the design process within the Mentor Graphics concerns, as well as how to use Mentor Graphics tools to
environment. create circuits that are dependable and efficient.
In electronic systems, analog comparators are widely used
Keywords—CMOS, Low power Comparator, Mentor Graphics. and have a crucial function in situations where accurate
voltage comparisons are necessary to make decisions. To
I. INTRODUCTION
ensure dependable data transmission, analog comparators are
This Analog comparator creation is an important task in the utilized in communication systems for threshold detection
field of analog circuit design, especially when using advanced [10] in routers and demodulators. These comparators are used
design tools like the Mentor Graphics suite [1] and developing for heartbeat detection as well as evaluation in healthcare
semiconductor technologies like 250 nm CMOS. technologies such as ECG monitors [11], demonstrating their
Fundamentally acting as the guardians of voltage levels in importance in life-saving equipment. The comparator in a
electronic systems, analog comparators allow for accurate low-power fully digital multi-level voltage monitor is used to
comparisons of incoming signals and produce digital outputs distinguish between different voltage levels to ensure accurate
in response to these comparisons. Their importance is shown monitoring within a wide voltage range [12], which is
in a wide range of applications, In an Analog to Digital essential for energy-harvesting IoT applications. These varied
Converter (ADC) [2,3,4], the comparator is used to compare uses highlight the adaptability and necessity of analog
the input analog voltage with a reference voltage, facilitating comparators across a range of industries. Analog comparators
the conversion of the analog signal into a corresponding in modern CMOS processes get more complicated as
digital value. Analog comparators are essential components in technology advances and there is a greater demand for faster,
the digital realm that enable functions like edge triggering, smaller, and more energy-efficient [13,14] devices. The
signal conditioning, and event detection in microcontrollers switch to 250 nm CMOS has advantages in terms of speed and
and digital signal processors (DSPs) [5]. The progress of integration, but it also has drawbacks in terms of noise
semiconductor technology towards smaller process nodes, sensitivity and power consumption. In analog comparator
such as 250 nm CMOS, has presented analog design with designs, designers must carefully balance performance, power
novel opportunities as well as obstacles. Smaller process efficiency, and reliability. Adopting low-power design
nodes provide issues with noise and power consumption in methodologies is essential in this dynamic environment
addition to increased integration density and speed. In this because they direct the creation of energy-efficient circuits

979-8-3503-7289-2/24/$31.00 ©2024 IEEE

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that satisfy the demanding specifications of modern necessity for the evolution of modern electronics as the
electronics. At the cutting edge of analog comparator research demand for energy-efficient devices grows. The context for a
are low-power design techniques, which seek to decrease thorough examination of analog comparator design is
energy consumption without sacrificing optimal performance. established by this introduction, which covers the importance,
One important method that comes to light is sub-threshold difficulties, design techniques, and practical implementations
operation, which enables transistors to function at voltages within the Mentor Graphics tool suite.
lower than their threshold, minimizing leakage currents and
preserving energy. Another noteworthy tactic is dynamic II. LITERATURE SURVEY
voltage scaling (DVS), which allows supply voltages to be The advancements in comparator design since 2020 have
changed in response to workload needs. During stages of low focused on enhancing power efficiency and speed, leveraging
activity, power consumption can be optimized without new technologies and innovative techniques. Vallabhuni
sacrificing performance by dynamically scaling voltages. Rajeev Ratna et al. (2020) utilized 18nm FinFET technology
With its collection of sophisticated design tools, Mentor for analog-to-digital converters, highlighting reduced power
Graphics gives designers a strong platform on which to consumption and increased speed. Tejender Singh and
successfully use these low-power strategies. The schematic
Suman Latha Tripathi (2022) reviewed low-power CMOS
capture tool makes it easier to construct analog comparator
circuits by providing an intuitive interface that makes it easier comparators, emphasizing dynamic voltage scaling and
to arrange components and specify important parameters. The advanced materials to achieve power efficiency. Dinesh
Mentor Graphics environment's subsequent simulations Kumar and Florence Sudha (2023) explored CMOS dynamic
enable designers to verify the performance, functionality, and comparators with a charge-sharing technique, achieving
power usage of their designs. significant improvements in power and speed. Hamid
Mahmoodian et al. (2022) introduced an energy-efficient
Beyond schematic capture, precise transistor sizing and dynamic comparator using CNTFETs for SAR ADC
optimization are made possible by Mentor Graphics tools, applications, offering ultra-low power consumption and high
which are essential for producing low-power analog speed. Prasanna and Suresh Kumar (2022) reviewed digital
comparators. The suite's transistor-level design tools enable
comparator architectures for digital signal processing,
designers to precisely adjust transistor size, maximizing low
focusing on power and performance optimization [18]. The
current leakage and lower power consumption. It is possible
to carefully alter strategies like current mirrors and cascade current study compares three 250nm CMOS comparator
biasing to achieve the appropriate balance between designs against these advancements, demonstrating
performance and power efficiency. Furthermore, the practical substantial improvements in power efficiency and
implementation of the circuit is optimized for size, performance metrics. For instance, Design 1 consumes 0.088
performance, and power thanks to Mentor Graphics' layout mW, significantly lower than earlier designs like those by
design capabilities. Component placement and connection Balaji G. Naveen et al. (2017). Additionally, designs 2 and 3
routing may be done precisely with the layout editor, and post- also show considerable advancements in power consumption
layout verification tools check the design against a number of compared to contemporary works. This study contributes to
parameters. Noise immunity and stability are still critical the evolving field by providing optimized designs that are
factors to take into account while searching for low-power validated through comprehensive simulations and layout
analog comparators. Noise in analog circuits can result in processes using Mentor Graphics tools, underscoring the
erroneous comparisons and false triggers. Comparator continuous innovation in achieving low-power, high-speed
designers frequently include hysteresis [15] in their designs to comparator designs for modern electronic applications.
lessen these impacts. By introducing positive feedback,
hysteresis causes the threshold voltage of the comparator to III. METHODOLOGY
change in response to the past history of the input signal. This The design and implementation of analog comparators are
method minimizes misleading triggers in noisy conditions,
crucial for achieving high performance and low power
cuts down on power consumption, and stops quick switching
consumption in modern electronic systems. This paper details
close to the threshold. Furthermore, to preserve signal
integrity and lessen sensitivity to noise, layout strategies that the methodology used to design, simulate, and validate three
limit parasitic capacitances and resistances are crucial. different comparator circuits.
• Comparator Design: The paper involves designing
Within the Mentor Graphics environment, designing three different comparator circuits. Each comparator
analog comparators utilizing 250nm CMOS technology [16] circuit is meticulously designed, considering low
is a complex process that requires an in-depth understanding power consumption and high performance. The design
of analog circuit principles, low-power design techniques, and utilizes 250nm CMOS technology to leverage its
sophisticated tool utilization. The smaller process nodes
advantages in terms of integration density and speed.
brought about by the advancement of semiconductor
technology offer designers both benefits and challenges, • Tool Utilization: The design process extensively
underscoring the importance of effective power management employs the Mentor Graphics suite for various phases,
techniques. Designers can create high-performance analog including schematic extraction, transistor sizing,
comparators with low power [17] consumption by combining biasing optimization, layout design, and post-layout
low-power design techniques, accurate transistor-level verification. These tools facilitate a detailed and
optimizations, and meticulous layout considerations. With the accurate design and analysis process.
ability to learn, simulate, enhance, and validate designs, • Simulation and Testing: The simulation of the
Mentor Graphics' extensive design toolkit is a great resource comparator circuits is carried out using Mentor
for designers. The creation of low-power analog comparators Graphics software [19]. The circuits are tested with a
becomes not just a technological achievement but also a sinusoidal input wave of 1.8V to evaluate their

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 performance metrics such as power consumption, Subsequently, the latching circuit stage comes into play,
noise immunity, stability, and speed. responsible for storing the output of the differential amplifier
• Layout Design: In addition to schematic design and until it's ready to be sampled by the output stage. Finally, the
simulation, the project involves the layout design output stage, crucial for driving the load, can be implemented
phase. This phase addresses component placement, using various transistor configurations like inverters, buffers,
routing, and parasitic effects, aiming to optimize the or amplifiers. Each stage in the comparator's design serves a
physical implementation of the circuits for enhanced specific function, collectively contributing to the overall
performance and functionality of the comparator circuit.
performance and manufacturability. Factors such as
signal integrity and minimizing crosstalk are V. CIRCUIT DESIGN ANALYSIS
considered during layout design.
The two-stage CMOS amplifier functions as a first
• Comparative Analysis: A comparative analysis is
comparator and has three stages. The first stage is a
performed between the proposed designs and existing
differential amplifier, the second is a common-source
literature, focusing on average power consumption, to
amplifier, and the third stage is an inverting buffer. The input
validate their effectiveness and competitiveness. For
bias current has a 1μA design parameter. The suggested
Design 1, with a voltage supply of 1.8V, the average
current mirror of two gain stages has a bias current of 3 μA.
power consumption is 0.088 mW, compared to 4.591
The differential pair is coupled to both of the analog input
μW in Balaji G. Naveen et al. (2017) [20]. Design 2
voltages. In this circuit, the reference voltage is Vim. In circuit
has a voltage supply of 1.8V and an average power
design, speed takes precedence over gain; therefore, a 0.25µm
consumption of 4 mW, compared to 0.953 μW in
transistor's length is ideal. Because an NMOS differential pair
Banu S. Aayisa et al. (2017) [21]. Design 3, also with
can be employed, NMOS transistors have greater mobility
a 1.8V supply, consumes 0.15 mW on average, against
than PMOS transistors. Because of the gain of the amplifier's
6.46 μW reported by Balaji G. Naveen et al. (2017).
first stage, the width of the NMOS-NMOS input differential
This analysis highlights the strengths and potential
pair will be enhanced. The overall gain of the amplifier is
improvement areas of the proposed designs
achieved by the use of a shared-source amplifier. The
concerning power efficiency and operational
objective is to improve the size of the common source
characteristics.
transistor PMOS1 and decrease the high parasitic capacitance
• Evaluation and Validation: The designed circuits are
of the transistor that causes delay in the first input stage. The
evaluated for their robustness against real-world
inverter buffer stage, which adds gain and raises the circuit's
manufacturing constraints. The evaluation process
slew rate, is the third stage.
includes comparing the performance of the proposed
Figure 2 shows the architecture of the first comparator
designs with other similar designs to ensure reliability
circuit.
and effectiveness in practical applications.
This comprehensive methodology ensures that the designed
comparators are optimized for low power consumption and
high performance, making them suitable for modern
electronic applications, particularly in energy-efficient and
battery-operated device.
IV. BLOCK DIAGRAM

Input 1
Output
Input Differential Latching Output
Stage Amplifier Circuit Stage

Input 2

Fig. 2. First Comparator.

Fig. 1. Block diagram for designing comparator.

The block diagram for designing a comparator, as depicted in In the ADCs, a comparator serves as the quantizer. There are
Fig. 1, comprises several key stages, each serving a distinct just two levels in a 1-bit comparator: a 1 or a 0. VDD = 5V is
function. Firstly, the input stage plays a vital role in implied by a 1, while GND is implied by a 0.
amplifying input signals and converting them to a common-
mode voltage, which is essential for ensuring that both input
signals are at the same voltage level for the subsequent stages
to operate effectively. Various transistor configurations,
including common-source, cascade, or folded cascade
amplifiers, can be utilized to implement this stage. Following
the input stage is the differential amplifier stage, which is
tasked with amplifying the difference between the two input
signals. The output from the differential amplifier stage is then
passed on to the output stage, where the final output signal is
generated. Similar to the input stage, the differential amplifier
stage can be realized using different transistor configurations,
such as two-stage, three-stage, or rail-to-rail amplifiers.
Fig. 3. Second Comparator.

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When the comparator's input exceeds the reference voltage, it
must provide an output of 1, and when it falls short of the
reference voltage, it should provide an output of 0. An easy-
to-use comparator can effectively fulfill the necessary
purpose. Given a reference level, a comparator outputs VDD
when the signal exceeds the reference level and GND when
the signal falls below the reference level. Fig. 3 depicts the
second comparator circuit design.

Fig.6: Second Comparator Output

We applied a sinusoidal wave of 1.8V amplitude with a

frequency of 10kHz to the Vin terminal, and a DC source of
0.75V amplitude to the Vref terminal. These inputs are
compared by a comparator, and we obtain a digital response,
as shown in Figure 7.

Fig. 4: Third Comparator.

The third comparator circuit may consist of a two-stage+ [22]
CMOS amplifier with an unbalanced differential pair and an
output inverter. A second differential pair, NMOS-NMOS,
unbalances the input differential pair. The output signals are
connected to the gates of the second differential pair, which
produces hysteresis or positive feedback. The second
differential pair provides hysteresis bias current and serves as
a current mirror for the transistor NMOS. The input
differential amplifier will experience a modest amount of Fig.7: Third Comparator output.
parasitic capacitance from the second differential pair. Fig. 4
VII. LAYOUT FOR COMPARATOR DESIGN
depicts the third comparator circuit's design.
During the layout design process, the schematic was
VI. SIMULATION RESULTS meticulously translated into a physical representation to
The simulation is carried out using Mentor Graphics software ensure optimal component placement and routing. The
and the 250nm technology library. We have applied a arrangement reflects the complexities of the analog
sinusoidal wave of 1.8V amplitude with a frequency of 10 kHz comparator, including crucial concerns for reducing parasitic
to the Vin terminal and a DC source of 0.2V amplitude to the effects and ensuring signal integrity. The physical
Vref terminal. After using a comparator to compare these implementation follows the specifications stated in the
inputs, we were able to get a digital response, as seen in Fig. schematic design, focusing on the compact arrangement of
5 below. circuit parts.

Fig.8: Layout for first comparator.

The layout incorporates industry standards to improve the

analog comparator's overall performance and reliability. The
Fig.5: First Comparator Output chosen layout design promotes effective signal propagation,
reduces potential interference, and ensures accurate
We applied a 1.5 V sinusoidal pulse with a frequency of functionality throughout operation. It was created utilizing
10kHz to the In1 terminal while grounding the other terminal. advanced design tools that work with a 250m technology
These inputs are compared using a comparator, and the library, and the resulting layout promises to provide an
resulting digital response is depicted in Fig. 6. excellent basis for the analog comparator's performance.

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 From the table:
• The first comparator has a power consumption of 0.088
mW.
• The second comparator has a power consumption of 4
mW.
• The third comparator has a power consumption of 0.15
mW.

Fig.9: Layout for second comparator.

Fig.11: Comparison of Comparator

visually represents the comparison of the three comparator

circuits discussed in Table 4.1. This graphical illustration
offers a clear visual depiction of the key parameters or
performance metrics of the comparator designs. By
Fig.10: Layout for third comparator.
examining this figure, it becomes easier to discern the
Figures 8–10 depict the layout for the three comparator differences and similarities between the comparator circuits
designs mentioned above. In addition to paying close in terms of voltage supply, power consumption, and
attention during the layout design process, significant efforts potentially other critical factors. The visual comparison
were undertaken to optimize the layout for manufacturability provided by Fig. 11 enhances the understanding of how the
and scalability. Advanced approaches like design rule checks proposed analog comparator design using 250nm technology
(DRC), parasitic extraction (PEX), and layout versus stands out or differs from existing comparator circuits, aiding
schematic (LVS) verification were used to assure compliance in the assessment of its efficiency and effectiveness in
with fabrication requirements and design standards. practical application.

VIII. COMPARISON IX. CONCLUSION

Table 1 presents a comparative analysis of three different The successful design of the three comparator circuits
comparator circuits from different papers, including Balaji, G. demonstrates the effectiveness of the approach taken in this
Naveen, et al. (2017) [2], Balaji, G. Naveen, et al. (2017) [2],
and the proposed design from this project. The table highlights project. It highlights the importance of utilizing proper design
the voltage supply and average power consumption for each tools and referring to existing literature to inform the design
design. It serves as a valuable reference for evaluating the process. The obtained results validate the chosen design
performance and efficiency of the proposed analog methodology and showcase the potential for achieving
comparator design in the context of power consumption and desired performance characteristics in analog comparators
voltage supply. The comparison aids in identifying the [23].
strengths and potential areas of improvement in the proposed The project contributes to the field of analog circuit
design concerning power efficiency and operational design, particularly in the area of comparator circuits[24]. It
characteristics. provides valuable insights into the practical implementation
The average power consumption in the paper is and simulation of such circuits using the Mentor Graphics
referred to as microwatts (uW) and the proposed system is in tool. The designed circuits can serve as a foundation for
milliwatts (mW) because of the 250 nm technology used. further research and development in the field, allowing for
Comparing the power consumption values, the first the exploration of enhancements and optimization
comparator with a power consumption of 0.088 mW is the techniques.
most suitable for low-power applications, as it consumes the In addition to the schematic design and simulation, the
least amount of power among the three comparators listed in project extended its focus to the layout design phase using the
the table. Mentor Graphics tool. The layout of the three analog
TABLE I. COMPARISON OF COMPARATOR CIRCUITS
comparator circuits was meticulously crafted, considering
factors such as component placement, routing, and parasitic
Balaji, G. Naveen, et Banu, S. Aayisa,
Proposed Design effects. The layout design aimed to optimize the physical
al. (2017) [2] et al. (2017) [3]
Avg. Avg. implementation of the circuits for enhanced performance and
Voltage
power
consumpti
Voltage
Avg.
power
Voltage
power
consump
manufacturability. Through careful layout considerations, the
Supply Supply Supply
(V)
on
(V)
consu
(V)
tion project ensured the proper translation of the schematic
(μW) mption (mW)
(μW) designs into physical form, addressing challenges such as
signal integrity and minimizing crosstalk. The Mentor
Design 1 1.8 4.591 - - 1.8 0.088
Design 2 - - 1 0.953 1.8 4 Graphics tool facilitated an efficient layout design process,
Design 3 1.8 6.46 - - 1.8 0.15

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