Exception/Interrupts

Introduction
•Interrupt: Communication process set up in a
microprocessor or microcontroller in which:
•Internal (exception) or external device requests
the MC to stop current processing
•MC acknowledges the request
•MC Attends to the request
•MC Goes back to processing where it was
interrupted
 Polling vs Interrupts
P
Y
t
e
• Handling internal/external // Polling method s
c
request in ways two ways:
while (1) {
read_button_inpu t; w
if (pushed) a
• Polling: You pick up the { c
phone every few seconds to }
Do something;
In
check whether you are D
getting a call. // Interrupt method
y
d
• Interrupt: Do whatever you interrupt_handle = true; u
r(){
should do and pick up the turn_on_LED;
w
r
phone when it rings. exit; }
 Exception and types..
• Exception is an unexpected event from within the processor.
• Types: Reset, Undefined instruction, Software Interrupt (SWI), Prefetch
Abort, Data Abort, IRQ (Interrupt Requests), FIQ
• 4-types of exception possible
• Interrupt: Interrupt is an unexpected asynchronous event from outside the process
(by I/O). Occur at random times during the execution of a program,
• Faults: An exception that can generally be corrected and that, once corrected,
allows the program to be restarted with no loss of continuity. When a fault is
reported, the processor restores the machine state to the state prior to the
beginning of execution of the faulting instruction. Faults are divide by zero and
undefined opcode.
• Traps: An exception that is reported immediately following the execution of the
trapping instruction. Traps allow execution of a program or task to be continued
without loss of program continuity.
• Aborts: Used only to signal severe system problems, when operation is no longer
possible.
 Interrupt-driven operations
• An interrupt is an event that initiates the automatic transfer of
software execution from one program thread to an interrupt
handler (or interrupt service routine)
• Event types:
• Signal from a “device” (keyboard, data converter, etc.)
• Device external to the CPU (possibly within a microcontroller)
• Signals that a device needs, or is able to provide service (i.e. device goes from
“busy” to “ready”)
• Asynchronous to the current program thread
• Allow CPU to do other work until device needs service!
• An internal event or “exception” caused by an instruction
• Ex. invalid memory address, divide by 0, invalid op code
• A software interrupt instruction
• Ex. ARM Cortex SVC (supervisor call) instruction
 Interrupt interface
Interrupt interface
CPU and device handshake:
• CPU and• device
devicehandshake:
asserts interrupt request to signal the CPU;
• asserts
• Device CPU asserts
interruptinterrupt
request toacknowledge
signal the CPU; when it responds to the
interrupt;
• CPU asserts interrupt(assert a signal
acknowledge whenor itperform
respondssome
to theaction)
interrupt; (assert
a signal or perform
• device some action)
de-asserts interrupt request.
• device de-asserts interrupt request.
intr request
PC
status

mechanism
intr ack reg
CPU
SP data/address data
reg
 Interrupt I/O
• Busy/wait very inefficient.
• CPU can’t do other work while testing device.
• Hard to do simultaneous I/O.
• But – OK if the CPU has nothing else to do, or if the program cannot otherwise
continue
• An interrupt handler is executed if, and only if, a device requires service
Types of Interrupts
 Types of Interrupts
•Hardware interrupts
• Maskable: can be masked or disabled
• Two groups: external and internal interrupts
• Non-maskable: cannot be disabled
•Software interrupts: generally used when the situation
requires stop processing and start all over
• Examples: divide by zero or stack overflow
• Generally, microcontrollers do not include software
interrupts
Example of Interrupt Circuit
 Interrupt Processing
Interrupt Processing
Hardware Busy Done Busy

Hardware
needs
service
Main
Thread Saves
execution Restores
state execution
Interrupt state
Thread
ISR time
provides
service

Bard, Gerstlauer, Valvano, Yerraballi

 MC Response to Interrupts
•When the interrupt process is enabled, the MC, during
execution, checks the interrupt request flag just before
the end of each instruction.
• If the interrupt request is present, the MC:
• Completes the execution of the instruction
• Resets the interrupt flag
• Saves the address of the program counter on the stack
• Some interrupt processes also save contents of MC registers on
the stack.
• Stops the execution
 MC Response to Interrupts
• To restart the execution, the MC needs to be redirected to the
memory location where the interrupt request can be met.
• “What to do if you receive the interrupt!”
• Accomplished by interrupt vectors
• The set of instructions written to meet the request (or to
accomplish the task) is called an interrupt service routine (ISR).
• Once the request is accomplished, the MC should find its way back
to the instruction, next memory location where it was interrupted.
• Accomplished by a specific return instruction
 ARM7TDMI and V7-M Interrupt
• ARM follows two ways to design and handle
interrupts/exceptions
• ARM7TDMI and V7-M (cortex-M cores)
• Notable differences
• ARM7TDMI uses an assembly code wrapper to handle interrupts, while the
Cortex-M processor automatically handles nested interrupts
• ARM7TDMI vector table contains instructions, while the Cortex-M0 vector
table contains the starting address of each interrupt service routine
• ARM7TDMI uses Interrupt Priority Registers (NVIC_IPR) to configure
interrupt priority levels, while the Cortex-M uses a priority level register
where a higher number means a lower priority
• Startup code and vector table are different between the ARM7TDMI and
the Cortex-M
ARM7TDMI Exception/Interrupt
 map does not point to a memory chip or memory block bu
The machine may be programmed to reset itself if somethi
302
ARM7TDMI Interrupts/Exceptions
ARM Assembly Language
Larger applications, such as a cell phone, will have to dea
provide robust methods to recover from them, especially in
0xFFFFFFFF that can change, e.g., if a memory card can be added or rem
Since exception vectors contain instructions at their resp
ory, an exception
Undef handler outside 32MB such as an IRQ, which is a low-priority in
Undef handler kind of
branch instruction change-of-flow instruction in its exception vector
range
0x30008000

SVC exception handler placed on

SVC handler
0x30000000 appropriate address boundary
>32 MB 0x2000000

IRQ handler IRQ handler within 32MB branch 0x1C FIQ

instruction range 0x18 IRQ
0x1000 0x14 (Reserved)
<4 KB Literal pool containing address of 0x10 Data Abort
0x30008000
0xFFC undef handler 0x0C Prefetch Abort
0x08 Software Interrupt
FIQ handler
FIQ handler follows vector table 0x04 Undefined instruction
B IRQ_handler 0x00 Reset
Reserved
Data abort vector
FIGURE 14.2 Exception vector table.
Prefetch abort vector
MOV PC, #0x30000000
LDR PC, [PC, #+0xFF0]
Reset vector
 ARM7TDMI Registers 300 ARM Assembly Language

Mode
• Total 37-registers physically User/System Supervisor Abort Undefined Interrupt Fast Interrupt
R0 R0 R0 R0 R0 R0
• 30 general-purpose registers, i.e., R1 R1 R1 R1 R1 R1
registers which can hold any value R2 R2 R2 R2 R2 R2

• 6 status registers R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
• A Program Counter register R5 R5 R5 R5 R5 R5

• 16-architectural registers R6
R7
R6
R7
R6
R7
R6
R7
R6
R7
R6
R7

• General-purpose registers are 32 R8

R9
R8
R9
R8
R9
R8
R9
R8
R9
R8_FIQ
R9_FIQ
bits wide R10 R10 R10 R10 R10 R10_FIQ

• Each exceptions have own set of R11

R12
R11
R12
R11
R12
R11
R12
R11
R12
R11_FIQ
R12_FIQ
registers to store evicted program R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ

register value R14

PC
R14_SVC
PC
R14_ABORT R14_UNDEF
PC PC
R14_IRQ
PC
R14_FIQ
PC
• Ex: Abort has SPSR_ABORT,
R13_ABORT, R14_ABORT CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ

= banked register
 Exception Handling Sequence
• CPSR is copied into SPSR_<mode>, where <mode> is the new mode
into which the processor is about to change
• CPSR bits are set. The core will switch to ARM state if it was in Thumb
state, as certain instructions do not exist in Thumb that are needed to
access the status registers
• Core will also change to the new exception mode, setting the least
significant 5 bits in the CPSR register
• Return address is stored in LR_<mode>, where <mode> is the new
exception mode
• Program Counter changes to the appropriate vector address in
memory
• Processor begins executing code from an exception handler, which is a
block of code written specifically to deal with the various exceptions
 Return From Exception
• CPSR must be restored from SPSR_<mode>, where <mode>
is the exception mode in which the processor currently
operates
• PC must be restored from LR_<mode>
 Vector Table
• Vector table keeps the exception codes or the address of the
exception
• ARM7TDMI uses actual instructions
• Each type of exception, there is usually a dedicated block of code,
called an exception handler,
• Not all exceptions need handlers, and in some deeply embedded
systems, the processor may not be able to recover.
• Vector table is accessed by change of flow instructions
 Change of Flow Instructions
• These instructions force the processor to begin fetching
instructions from its handler
• Branch instruction: direct branch can be used to jump to your
exception handler; however, the range of a B instruction is only
32 MB
• MOV instruction: can change the PC simply by loading the
register with a value. The value loaded could be created from a
byte rotated by an even number of bits
• MOV PC, #0xEF000000
• LDR instruction: data can be stored in instruction memory and
then accessed by using an offset to the Program Counter
• LDR PC, [PC+offset]
 Vectored Interrupt Controller (VIC)
• Provides a software interface to the interrupt system
• In a system with an interrupt controller, software must determine
the source that is requesting service and where its ISR is loaded.
• ARM7TDMI has only 2-interrupt lines
• Multiple inputs and only two outputs for most cores— the FIQ and IRQ
interrupt lines
• Manage many interrupts through FIQ and IRQ lines
• how would an SoC with dozens of potential interrupt sources compete for the
processor’s time?
• use an external interrupt controller, which is a specialized piece of hardware that
takes in all of the interrupt lines, assigns priorities to them, and often provides
additional information to help the processor,
• processor must first change the Program Counter to either address 0x18 or 0x1C
in memory
 Vectored Interrupt Controller (VIC)
• Incoming lines are wired together or connected to an external interrupt
controller, after the processor jumps to the start of the interrupt handler, the
handler itself still has to determine which device caused the interrupt
• Basic principle behind the VIC is to provide enough information to the processor
so that it doesn’t have to go searching through all of the possible interrupts to
determine the requester
 Exception
TABLE 14.1 Priorities
ARM7TDMI Exception Priorities
Priority Exception Comment
Highest Reset Handler usually branches straight to the main routine.
Data Abort Can sometimes be helped with hardware (MMU).
FIQ Current instruction completes, then the interrupt is acknowledged.
IRQ Current instruction completes, then the interrupt is acknowledged. Used
more often than FIQ.
Prefetch Abort Can sometimes be helped with hardware (MMU).
SVC Execution of the instruction causes the exception.
Lowest Undefined SVC and Undef are actually mutually exclusive, so they have the same
Instruction priority.

A situation could present itself where the processor is already handling an excep-
 Example
• A/D converter sampling, then IRQ exception and undefined memory access
(Data abort) at the same time. Unfortunately, processor is informed that it is
losing power (FIQ) in 2-minutes.
• Sequence will be Undefined mem access (Data abort) resolved first, then FIQ alert the
system the power failure (store information to non-volatile memory), then A/D will
have its turn
• If a higher priority interrupt occurs while a interrupt is on processor,
processor will service the high priority one first then the low priority one.
• Example: FIQ currently servicing in processor and data abort occurs. Processor would
begin exception processing again. CPSR would be stored into SPSR_abort, changing
mode etc. Data abort completes then FIQ will be activated again.
 ARM7TDMI Exception/Interrupt - Reset
• When the processor first receives power/resets
• put the value 0x00000000 on the 32-bit address bus going to memory
• 0x00000000 stores the first instruction (usually a JUMP) to start
• This JUMP takes to the first instruction to the Reset handler
• Initialization of the processor or microcontroller is started.
• Other jobs to reset handler
• Set up exception vectors
• Initialize the memory system (e.g., if a memory management unit [MMU] memory
protection unit [MPU] is present)
• Initialize all required processor mode stacks and registers
• Initialize any critical I/O devices
• Initialize any peripheral registers, control registers, or clocks, such as a phase-locked
loop (PLL)
• Enable interrupts
• Change processor mode and/or state
 Undefined Instructions
• Undefined Instructions exception Occurs if:
• processor doesn’t recognize a bit pattern in memory, OR
• processor encounters an instruction that is intended for a coprocessor
(such as a floating-point unit or other special bit of hardware that was
attached to the coprocessor interface), but the coprocessor either doesn’t
exist or it doesn’t respond. OR,
• Solve with available instructions
• Coprocessor not responding to an instruction
• Happens when coprocessor executing its own instruction, then does not respond to
other processor instruction
• Ex: ector Floating- Point (VFP) coprocessors generates an exception while processing
one of its own instructions (suppose it tried to divide by zero), it will simply not
respond when the integer processor tries to give it another instruction
• Processor sees a legitimate coprocessor instruction but is not in a privileged
mode.
 External Interrupts
• Two interrupt lines—one for a fast interrupt (FIQ) and one
for a low-priority interrupt (IRQ)
• Dozens of potential interrupt sources compete for the
processor’s time with these 2-lines
• How to determine who triggered the interrupt?
• Way 1: Using OR wire – Needs polling the triggering candidate
• Way 2: Use an external interrupt controller, which is a specialized
piece of hardware that takes in all of the interrupt lines, assigns
priorities to them, and often provides additional information to
help the processor
• vectored interrupt controller (VIC)
 Aborts
• 32-bit architecture can support 4GB memory, however physical
memory is much lower (say 128 MB)
• MMU manages the memory
• Processor requests a page that doesn’t exist in memory, the MMU
provides an abort signal back to the processor, and the processor
takes a data or prefetch abort exception.
• MMU can try to swap out pages of memory and the processor will
try again to load or store a value to a memory location
• Prefetch Aborts: processor attempts to fetch an instruction from an
invalid address.
• Data Aborts: Loads and stores can generate data aborts if the
address doesn’t exist or if an area of memory is privileged.
 Solution of Abort
• Prefetching Abort
• If MMU exists: processor will attempt to load the correct memory
page and execute the instruction at the specified address.
• If no MMU: indicative of a fatal error. Reset
• Data Abort
• If MMU exist: Programmer can find the offending address in the
MMU’s Fault Address Register. Fix the problem by swapping in
the correct page of memory, and the processor can reattempt the
access.
• No MMU: Fatal error. Report and exit
 SVC or Software Interrupt
• User program can request services from an operating system by encoding a
request in the 24 bits of the mnemonic for ARM instructions or the 8 bits for
Thumb instruction
• Ex: If requires keypad and LCD for the actual program but no LCD is currently
available the current program can be tested with command prompt printf
statement
• printf statements force the output onto a console window in the tools instead of to a
nonexistent LCD panel
• Processor fetches the instruction at the exception vector address 0x8 after
changing to Supervisor mode.
• SVC handler must locate the instruction and extract the comment field
embedded in the SVC instruction itself
• SVC number in the instruction can then be used to perform whatever tasks are
allowed by the handler
Exception Handling V7-M
 by changing the least significant bit of the CONTROL register, sho
15.2. When the processor takes an exception, it switches to Handler
Operation Modes and Privilege Levelsis always privileged, allowing the system to deal with any issues tha

• 2 operation modes: Thread mode Handler mode

• Handler mode: Exception entry
• Thread mode: Reset
P
• 2 privilege levels:
Exception exit
• Privileged levels: CONTROL
• User levels: register
P P = Privileged
affects U = User
• Cortex-M processors use Handler mode for transition
dealing with exceptions and everything else Exception exit
runs in Thread mode U
• Exception runs in privileged levels Exception entry
• Thread runs in both levels
• processor comes out of reset, it immediately runsCortex-M4
FIGURE 15.1 in operation modes.
privileged Thread mode
• system is configured, the processor can be put into
31 3 2 1 0
non-privileged Thread mode
Reserved FPCA ASP TMPL

FPCA – Floating-point context active

 Interrupt Vector Table
• When interrupt x is triggered, jump to the ISR for interrupt x. (1 ≤ x ≤ 255)
• consists of addresses Interrupt Vector Table
When interrupt x is
• Exception occurs, the processor will push triggered,
informationjump toto thethe
ISR stack, also
reading the address at the appropriate vector in the
for interrupt vector
x. (1 table to start
≤ x ≤ 255)
Address of ISR 1
handling the exception. Interrupt Vector Table
Interrupt Number Memory Address of ISR
(8 bits) (32 bits)
Nested-Vectored Interrupt
Controller (NVIC) 1 Interrupt Service Routine for interrupt 1
PA.3 2 Interrupt Service Routine for interrupt 2

Cortex-
EXTI3

NVIC
3 Interrupt Service Routine for interrupt 3

M4
4 Interrupt Service Routine for interrupt 4
5 Interrupt Service Routine for interrupt 5
EXTI3_IRQHandler
… …
Interrupt
Vector
Table
 Interrupt Vector T
Interrupt Vector Table T
C
• The Nested Vectored Interrupt Controller h
(NVIC), prioritizes and handles all interrupts.
• When we press the push button connected Nested-Vectored Interrupt
c
to the pin PA 3, the hardware generates an Controller (NVIC) g
i
electrical signal, called interrupt request,
PA.3

Cortex-
EXTI3

NVIC

M4
EXTI3. W
r
• When NVIC receives the interrupt request, it EXTI3_IRQHandler
t
forces the processor to jump to, and execute, Interrupt
Vector
c
a special piece of code, called an interrupt Table i

service routine, or an interrupt handler. T

• Then, the processor will execute the function f

named EXTI3 IRQ Handler.

Interrupt and Exception assignments in ARM Cortex-M
Interrupt # Interrupt Memory Location Priority Level
0 Stack Pointer Initial Value 0x00000000
1 Reset 0x00000004 -3 Highest
2 NMI 0x00000008 -2
3 Hard Fault 0x0000000C -1
4 Memory Management Fault 0x00000010 Programmable
5 Bus Fault 0x00000014 Programmable

Usage Fault (undefined instructions, divide by zero, unaligned memory

6 0x00000018 Programmable
access, ....)

7 Reserved 0x0000001C Programmable

8 Reserved 0x00000020 Programmable
9 Reserved 0x00000024 Programmable
10 Reserved 0x00000028 Programmable
11 SVCall 0x0000002C Programmable
12 Debug Moniter 0x00000030 Programmable
13 Reserved 0x00000034 Programmable
14 PendSV 0x00000038 Programmable
15 SysTick 0x0000003C Programmable
16 IRQ for peripherals 0x00000040 Programmable
17 IRQ for peripherals 0x00000044 Programmable
... ... ... ...
255 IRQ for peripherals 0x000003FC Programmable
 Exception Assignments
• Reset.
• NMI. A non-maskable Interrupt (NMI) has the highest priority other than
reset. NMI is permanently enabled and has a fixed priority of -2.
• Hard Fault. Hard faults have a fixed priority of -1, meaning they have higher
priority than any exception with configurable priority.
• Memory Management Fault occurs because of a memory protection related
fault, including access violation and no match. This fault is used to abort
instruction accesses to Execute Never memory regions, even if the MPU is
disabled
• Bus Fault occurs because of a memory-related fault for an instruction or data
memory transaction such as a prefetch fault or a memory access fault.
 Exception Assignments
• Usage Fault occurs because of a fault related to instruction execution.
• Trying to divide by zero,
• Trying to switch the processor into ARM state.
• SVCall A supervisor call (SVC) is an exception that is triggered by the SVC instruction.
• Debug Monitor caused by the debug monitor (when not halting).
• Pend SV is a pendable (priority is hanged), interrupt-driven request for system- level
service.
• Sys Tick – system timer generates when it reaches zero when it is enabled to
generate an interrupt. Software can also generate a SysTick exception using the
Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
• Interrupt(IRQ) - An interrupt, or IRQ, is an exception signaled by a peripheral or
generated by a software request and fed through the NVIC (prioritized). All interrupts
are asynchronous to instruction execution. In the system, peripherals use interrupts
to communicate with the processor.
 Stack Pointer
• SRAM begins at address 0x20000000 and the stack has been
defined to be 256 bytes (0x100) at the top
• Instead of having a dedicated hardware register for different
exceptions, V7-M processors have only 2-stack pointers (r13) only
• Main Stack Pointer (MSP): kernel should use the MSP. Exception
handlers and any code requiring privileged access must use the MSP.
• Process Stack Pointer (PSP):
Thread mode should use the
PSP
• Using appropriate stack
pointer is determined by
CONTROL register
 Cortex CPU registers
Cortex CPU registers
• Two processor modes:
• Thread mode for User tasks
• Handler mode for O/S tasks and exceptions
• Stack-based exception model
• Vector table contains addresses

Process SP, Main SP (selected at reset)

PSR has priority of current process

PRIMASK has intr. enable (I) bit
BASEPRI has allowed intr. priority
 Interrupt signal detected by
Cortex-M Interrupt Processing CPU
•Suspend main
Much of this program
transparent whenexecution
using C Pre-IRQ
finish
• Interrupt current
signal instruction
detected by CPU top of stack
• Suspend
savemain
CPUprogram execution
state (push registers onto stack)
• finish current instruction
setCPU
• save LRstate
to (push
0xFFFFFFF9 (indicates
8-registers onto stack, r0 -interrupt return)
r3, r12, r14, r15,
xPSR)
• setset IPSR
LR to to interrupt
0xFFFFFFF9 number
(EXC_RETURN -- indicates interrupt return)
• setload PCinterrupt
IPSR to with number
ISR address from vector table
• load PC with ISR address from vector table
•Execute interrupt
Execute interrupt service
service routine
routine (ISR) (ISR)
• save other registers to be used in the ISR 1
• save other registers to be used in the
clear the “condition” that requested the interrupt ISR
• clearthe
perform therequested
“condition”
servicethat requested the interrupt
IRQ
• communicate with other routines via global variables
• perform
restore the requested
any registers saved by theservice
ISR top of stack
• Returncommunicate
to and resumewith
mainother routines
program via global
by executing variables
return Branch (B x) when LR = 0xFFFFFFF9
restore
• saved state isany registers
restored from thesaved by the ISR
stack, including PC 1
When LR =
Return to and resume main program by executing BX LR
 Interrupt Return
• The interrupt mechanism detects when the processor has
completed an exception handler.
• EXC_RETURN value (0xFFFFFFF9 ) was loaded into LR on exception
entry (after stacking PC and original LR)
• Interrupt return occurs when:
• Processor is in Handler mode
• EXC_RETURN loaded to PC by executing one of these instructions:
• LDM or POP that loads the PC
• LDR with PC as the destination
• BX using any register
 Interrupt Service Routine (ISR)
• A group of instructions that accomplishes the task requested
by the interrupting source
• Similar to a subroutine except that the ISR must be
terminated in a Return instruction specially designed for
interrupts
• The Return instruction, when executed, finds the return address
on the stack and redirects the program execution where the
program was interrupted.
• Some Return instructions are designed to retrieve the contents of
MC registers if saved as a part of the interrupts.
Memory Map of Cortex-M4
 Data Memory
Data Memory

0xFFFFFFFF 0x3FFFFFFF
0.5 GB
System
0xE0000000

External
1 GB
RAM
0xA0000000

External 0x20017FFF
1 GB
Device Stack

0x60000000
0.5 GB Peripheral Internal
0x40000000
Heap
SRAM
0.5 GB SRAM Memory 96 KB
0x20000000 Zero-initialized data
0.5 GB Code Initialized data
0x00000000 0x20000000
Instruction Memory
Code Memory
0xFFFFFFFF 0x1FFFFFFF
0.5 GB System Reserved
0xE0000000

External 0x080FFFFF
1 GB
RAM RW Data Section
Internal
0xA0000000 RO Data Section
Flash
Text Section
External Memory
1 GB Interrupt
Device Vector Table
1 MB

Initial MSP 0x00000000

0x08000000
0x60000000
0.5 GB Peripheral Mapped
0x40000000 Reserved
(aliasing)
0.5 GB SRAM
0x20000000 Interrupt
0.5 GB Code Vector Table
0x00000000 Initial MSP 0x00000000
 Cortex-M4 Registers (co

Interrupt mask registers

– Set to one will block all the interrupts apart from NMI
– 1-bit BASEPRI
• 1-bit PRIMASK – Set to one will block all interrupts of the same or low
• Set to one will block all the interrupts apart from non-maskable interrupt
(NMI) and the hard fault exception level (only allow for interrupts with higher priorities)
• 1-bit FAULTMASK • CONTROL: special register
• Set to one will block all the interrupts
– 1-bitapart
stack from NMI
definition
• 1-bit BASEPRI – Set to one: use the process stack pointer (PSP)
• Set to one will block all interrupts–ofClear
thetosame or lower level (only allow for
zero: use the main stack pointer (MSP)
interrupts with higher priorities)
PRIMASK Reserved

FAULTMASK Reserved

BASEPRI Reserved

CONTROL Reserved

bit31 bit24 bit16 bit8

Stack definition
 Cortex-M structure
Cortex-M structure
• Non Maskable
Interrupt (NMI)
• Interrupt
Requests (IRQs)
• Nested Vectored
Interrupt
Controller (NVIC)

Nested Vectored
Interrupt Controller
---------
Coordinates multiple
Interrupt sources
 Interrupt
Interrupt Number
• Cortex-M supports upto 256 interrupts.
n •Cortex-M supportsonly
In reality supports up 65
to 256 interrupts.
• Allowed to support 496
System Peripheral interrupt
Exceptions Interrupts number

-16 -1 0 239

• First 16 are system exceptions

CMSIS Interrupt Number
n •First
CMSIS are system
16defines exceptions
their interrupt numbers as negative
•q Defined
CMSISbydefines
ARM core
their interrupt numbers as negative
• The
q rest 240by
Defined areARM
peripheral
core interrupts
• Peripheral interrupt number starts with 0.
n
•The rest by
Defined 240 aremanufacturers.
chip peripheral interrupts
•q TM4C123 hasinterrupt
Peripheral 16 System Exceptions
number starts and
with 78
0. peripheral Interrupts
q Defined by chip manufacturers.
 Interrupt Service Routine Vector Table
• Start address for the Address
Pri
ori
Type of
Acronym Description
exception hander for ty
priority

each exception type is 0x0000_0000 - - - Stack Pointer

-3 fixed Reset Reset Vector
fixed and predefined
0x0000_0004
Non maskable interrupt. The RCC Clock

• Processor loads PC
0x0000_0008 -2 fixed NMI_Handler Security System (CSS) is linked to the NMI
vector.

with this fixed, pre- 0x0000_000C -1 fixed HardFault_Handler All class of fault

defined address 0x0000_0010 0 settable

MemManage_Handl
er
Memory management

• Exception Vector Table

0x0000_0014 1 settable BusFault_Handler Pre-fetch fault, memory access fault

starts at memory
0x0000_0018 2 settable UsageFault_Handler Undefined instruction or illegal state

0x0000_001C-
address 0 0x0000_002B
- - - Reserved

3 settable SVC_Handler System service call via SWI instruction

• Program Counter pc =
0x0000_002C
0x0000_0030 4 settable DebugMon_Handler Debug Monitor
0x00000004 initially 0x0000_0034 - -- Reserved

0x0000_0038 5 settable PendSV_Handler Pendable request for system service

0x0000_003C 6 settable SysTick_Handler System tick timer

Interrupt and Exception assignments in
ARM Cortex-M
• (Nested Vector Interrupt Controller) NVIC of the ARM Cortex-M has room for
the total of 256 interrupts and exceptions.
• Interrupt numbers are also referred to as INT type (or INT #) in which the
type can be from 1 to 255 or 0x01 to 0xFF.
• NVIC in ARM Cortex-M assigns the first 15 interrupts for internal use.
• Memory locations 0 to 3 are used to store the value to be loaded into the stack
pointer when the device is coming out of reset.
Interrupt Request (IRQ) for Peripheral
interrupts
• ISR (Interrupt Service Routine) can be launched as a result of an event at the
peripheral devices such as timer timeout or analog-to-digital converter (ADC)
conversion complete. The largest number of the interrupts in the ARM Cortex-M
belong to this category.
• ARM Cortex-M NVIC has first 15 interrupts (INT 1 to INT 15) for internal use and
exceptions and is not available to chip designer. The Reset, NMI, undefined
instructions, and so on are part of this group of exceptions. The rest of the interrupts
can be used for peripherals.
• Many of the INT 16 to INT 255 are used by the chip manufacturer to be assigned to
various peripherals such as timers, ADC, Serial COM, external hardware interrupts,
and so on. There is no standard in assigning the INT 16 to INT 255 to the peripherals.
• Each peripheral device has a group of special function registers that must be used to
access the device for configuration.
• For a given peripheral interrupt to take effect, the interrupt for that peripheral must
be enabled. The special function registers for that device provide the way to enable
the interrupts.
 Interrupt Priority for ARM Cortex-M
• All exceptions and interrupts in the Cortex-M4 system have certain priority levels, either
maskable or un-maskable sources.
• Most maskable interrupts have programmable priority levels, but all Non-Maskable
Interrupts (NMIs) have fixed priority levels (-2).
• When an exception or interrupt occurs, the NVIC performs a comparison between the
priority level of current exception or interrupt and the priority level of the new coming
exception/interrupt.
• Current running task will be suspended and the control will be transferred to the service routine of the
new coming exception/interrupt if the priority level of the new coming exception/interrupt is higher.
• In the ARM Cortex-M4 system, the interrupt priority levels are controlled by the Interrupt
Priority Registers,
• Each priority register can use 3 bits, 4 bits, or 8 bits to cover all priority levels used in the
priority control system.
• 8 priority levels can be used if 3 bits are used in this register,
• 16 priority levels can be obtained if 4 bits are used in this register.
• Devices within the Tiva family support up to 154 interrupt sources and 8 priority levels,
• which means that 3 bits are used in the priority register in the TM4C123GH6PM MCU.
 Steps to Configure an Interrupt
• System clocks on processor must be set up
• Clocks must be enabled to the interrupt block, specifically, using the
RCGCTIMER register
• Configure the GPTMTnMR register.
• Timer will be set up as a 16-bit timer, so the initial count will be (by a reset)
set to 0xFFFF. By default, the timer will count down to zero, rather than up.
• Interrupt from the timer needs to be enabled
• GPTMIMR register, or General-Purpose Timer Interrupt Mask Register, than
needs to be configured
• Interrupts needs to be enabled from Timer 0A in the NVIC. Bit 19 of
the Interrupt Set Enable register in the NVIC enables Timer 0A.
• The timer needs to be started.
For Lab and Project
Relationship between vectors and NVIC
definitions
Priority
Interrupt Interrupt
Vector Address Interrupt Register Priority
(Exception) #
address (Priority Register) Source (Tivaware Bits
Number (IRQ)
Name)
NVIC_SYS_PRI
0x00000038 14 -2 0xE000.ED20 PendSV 23 - 21
3_R
NVIC_SYS_PRI
0x0000003C 15 -1 0xE000.ED20 SysTick 31 - 29
3_R
0x00000040 16 0 0xE000.E400 GPIO Port A NVIC_PRI0_R 7-5
0x00000044 17 1 0xE000.E400 GPIO Port B NVIC_PRI0_R 15 - 13
0x00000048 18 2 0xE000.E400 GPIO Port C NVIC_PRI0_R 23 - 21
0x0000004C 19 3 0xE000.E400 GPIO Port D NVIC_PRI0_R 31 - 29
0x00000050 20 4 0xE000.E404 GPIO Port E NVIC_PRI1_R 7-5
0x000000B8 46 30 0xE000.E41C GPIO Port F NVIC_PRI7_R 23 - 21
Interrupt numbers 0 to 15 contain the faults, software interrupt and SysTick; these interrupts will be handled
differently from interrupts 16 and up.
 GPIO Port Interrupt Programming
• On top of the 6-defined registers, few other registers need to be defined for
Interrupt
• GPIO Interrupt Control Registers
• GPIO Interrupt sense register (GPIO_PORTx_IS_R)
• GPIO Interrupt Event Register (GPIO_PORTx_IEV_R)
• GPIO Interrupt Both Edge (GPIO_PORTx_IBE_R)
• GPIO Interrupt Mask Register (GPIO_PORTx_IM_R)
• GPIO Interrupt Clear Register (GPIO_PORTx_ICR_R)
• GPIO Direction Register (GPIO_PORTx_DIR_R)
• GPIO Digital Enable Register (GPIO_PORTx_DEN_R)
• NVIC Interrupt Priority Register
• NVIC Interrupt Enable (NVIC_ENe_INT2)
• NVIC Interrupt Set Enable Register (NVIC_ENe_R)
• NVIC Interrupt Priority Register (NVIC_PRIn_R)
• x = [A-F], e = [0-3], n = [0-12]
• Let’s connect a Edge Triggered switch in PC4 (PORT C PIN 4) for our interrupt design
 Interrupt trigger point
• When an input pin is connected to an external device to be used for
interrupt, we have 5 choices for trigger point. They are:
• low-level trigger (active Low level),
• high-level trigger (active High level),
• rising-edge trigger (positive-edge going from Low to High),
• falling-Edge trigger (negative-edge going from High to Low),
• Both edge (rising and falling) trigger.
 GPIO Interrupt sense register
(GPIO_PORTx_IS_R)
• Let’s connect a Edge sensetive switch in PC4 (PORT C PIN 4) for our
interrupt design
Bit Bit Name Description
GPIO Interrupt Sense
7-0 IS 0: The edge on the corresponding pin is detected (edge-sensitive).
1: The level on the corresponding pin is detected (level-sensitive).

• #define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404))

• GPIO_PORTC_IS_R &= ~0x10; // PC4 is edge-sensitive
GPIO Interrupt Event Register
(GPIO_PORTx_IEV_R)
• After using the GPIOIS register we need to indicate which level or edge.
• To do that, we use the GPIO Interrupt Event (GPIOIEV) to decide low-level, high-
level, falling, or rising-edge.
• Since we need a rising edge triggered interrupt at PC4, so writing 1 to the respective
bit field will do the same for us.
GPIO_IS (interrupt sense) GPIO_IEV (Interrupt Event) Explanation
0 0 Falling edge
0 1 Rising edge
1 0 Low level
1 1 High level
• Ex: Our is Falling EDGE PORT C PIN 4
• #define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C))
• GPIO_PORTC_IEV_R &= ~0x10; // PC4 falling edge event
GPIO Interrupt Both Edge
(GPIO_PORTx_IBE_R)
• Setting the corresponding bit field enables the interrupts for both edges i.e.
rising edge and falling edge
Bit Bit Name Description
GPIO Interrupt Both Edges
0: Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV)
7-0 IBE
register
1: Both edges on the corresponding pin trigger an interrupt

• Ex: Falling Edge sensetive switch in PC4 (PORT C PIN 4)

• #define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408))
• GPIO_PORTC_IBE_R &= ~0x10; // PC4 is not both edges
GPIO Interrupt Clear Register
(GPIO_PORTx_ICR_R)
• The Bit fields in this register clears the interrupt for the respective pin to
ensure that any previous interrupt has been cleared writing 1 to the
respective bit field.
• It is critical that the interrupt handler clears the interrupt flag before returning from
interrupt handler. Otherwise the interrupt appears as if it is still pending and the
interrupt handler will be executed again and again forever and the program hangs.
• Ex: Falling Edge sensetive switch in PC4 (PORT C PIN 4)
• #define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C))
• GPIO_PORTC_ICR_R = 0x10; // clear flag4
GPIO Interrupt Mask Register
(GPIO_PORTx_IM_R)
• We need to enable the interrupt capability of a given peripheral at
the module level.
• In I/O ports, each pin can be used as a source of external hardware
interrupt. This is done with the GPIO Interrupt Mask (GPIO_IM) register.
• Lower 8 bits of this register is used to enable the interrupt capability of
each pin of the I/O port. To enable the interrupts for PF0 and PF4 pins, we
will need the following:
• GPIO_PORTF_IM_R |= 0x11; /* unmask interrupt */
• Ex: Falling Edge sensetive switch in PC4 (PORT C PIN 4)
• #define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410))
• GPIO_PORTC_IM_R |= 0x10; // arm interrupt on PC4
 DIR, DEN, PUR Registers
• As it is a PIN to get the input from switch as an Interrupt you need
to have a DIR
• However, input is by default LOW (0) in PIN
• Switch send a digital input, so DEN is required
• As it is an switch need the PUR register enabled
• Ex: Falling Edge sensetive switch in PC4 (PORT C PIN 4)
• #define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400))
• GPIO_PORTC_DIR_R &= ~0x10; // make PC4 in
• #define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C))
• GPIO_PORTC_DEN_R |= 0x10; // enable digital I/O on PC4
• #define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510))
• GPIO_PORTC_PUR_R = 0x10; /* enable pull-up for PC4 */
NVIC Interrupt Priority Register (NVIC_PRIn_R)
PRIn Register Bit Priority Register
Interrupt Source
Field Macros
Bits 31:29 Interrupt[IRQ] = Interrupt[4n+3]
Bits 23:21 Interrupt[IRQ] = Interrupt[4n+2]
NVIC_PRIn_R
Bits 15:13 Interrupt[IRQ] = Interrupt[4n+1]
Bits 7:5 Interrupt[IRQ] = Interrupt[4n]
 NVIC Interrupt Priority Register (NVIC_PRIn_R)
• Priority register bit field (INTA, INTB, INTC, INTD) is 3-bits wide which means that for
an interrupt there can be 8 priority levels from 000 to 111 and it can be programmed
as per the need.
• ‘n’ represents the group number of priority registers, for each group n registers
NVIC_PRIn can control up to 4 peripheral ranging from 4n to 4n+3.
• Example, IRQ = 0, so the equation interrupt[4n]=0, the value of n must be zero which
corresponds to the NVIC_PRI0_R
• For n=0, the same priority level register can be used to configure the interrupts
whose IRQ Number are within 4×0 to 4×0+3, which corresponds to the IRQ number
0,1,2,3.
• Next table shows some of the priority registers on the NVIC. Each register contains an
8-bit priority field for four devices. On the TM4C micro controllers, only the top three
bits of the 8-bit field are used. This allows us to specify the interrupt priority level for
each device from 0 to 7, with 0 being the highest priority.
• Defining the Priority
• NVIC_PRIn_R = (NVIC_PRIn_R& LowInBitPosition) | PriorityInBitPosition
NVIC Interrupt Priority Register (NVIC_PRIn_R)
• Ex: Falling Edge sensetive switch in PC4 (PORT C PIN 4)
• IRQ_PORTC = 2 [From slide 28]
• 2 = 4 * 0 + 2, that’s PRIn Register Bit Field is Bits 23:21 [INTC] and can be taken n=0
• In bits 23:21 we should set 000 with address 0xE000E400
• For PORTC we take n= 0, so NVIC_PRI0_R (from table)
• If we want to set priority 5 (101 00000 = A0), for the PORT C PIN 4, NVIC_PRI0_R =
(NVIC_PRI0_R&0xFF00FFFF) | 0x00A0 0000
• #define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400)) // IRQ 0 to 3 Priority Register
• NVIC_PRI0_R = (NVIC_PRI0_R&0xFF00FFFF) | 0x00A0 0000
• The interrupt number is loaded into the IPSR register. The servicing of interrupts does
not set the I bit in the PRIMASK, so a higher priority interrupt can suspend the
execution of a lower priority ISR.
• If a request of equal or lower priority is generated while an ISR is being executed, that
request is postponed until the ISR is completed. In particular, those devices that need
prompt service should be given high priority.
Popular priority registers used in the
TM4C123GH6PM NVIC
Address 31 - 29 23 - 21 15 - 13 7-5 Name
0xE000E400 GPIO Port D GPIO Port C GPIO Port B GPIO Port A NVIC_PRI0_R
0xE000E404 SSI0, Rx Tx UART1, Rx Tx UART0, Rx Tx GPIO Port E NVIC_PRI1_R
0xE000E408 PWM Gen 1 PWM Gen 0 PWM Fault I2C0 NVIC_PRI2_R
0xE000E40C ADC Seq 1 ADC Seq 0 Quad Encoder 0 PWM0 Gen 2 NVIC_PRI3_R
0xE000E410 Timer 0A Watchdog ADC Seq 3 ADC Seq 2 NVIC_PRI4_R
0xE000E414 Timer 2A Timer 1B Timer 1A Timer 0B NVIC_PRI5_R
0xE000E418 Comp 2 Comp 1 Comp 0 Timer 2B NVIC_PRI6_R
0xE000E41C GPIO Port G GPIO Port F Flash Control System Control NVIC_PRI7_R
0xE000E420 Timer 3A SSI1, Rx Tx UART2, Rx Tx GPIO Port H NVIC_PRI8_R
0xE000E424 CAN0 Quad Encoder 1 I2C1 Timer 3B NVIC_PRI9_R
0xE000E428 Hibernate Ethernet CAN2 CAN1 NVIC_PRI10_R
0xE000E42C uDMA Error uDMA Soft Tfr PWM Gen 3 USB0 NVIC_PRI11_R
0xE000ED20 SysTick PendSV --- Debug NVIC_SYS_PRI3_R
 Enabling and Disabling an Interrupt
• Upon Reset, all the interrupts are disabled. To enable any interrupt we should:
• Enable the interrupt for a specific peripheral module.
• This is done with the GPIO Interrupt Mask (GPIOIM) register.
• Enable the interrupts at the NVIC module.
• Enable the interrupt globally .
NVIC Interrupt Set Enable Register
(NVIC_ENe_R)
• Interrupt set enable register ranging from NVIC_EN0_R ... NVIC_EN3_R,
• Each ISER register is 32 bit wide that can be used to set the interrupt against the respective
IRQ numbers.
• Each ISER register can be used to enable 32 different types of interrupt sources.
• NVIC_EN0_R is used to enable the interrupt sources whose IRQ numbers are 0-31,
• IRQ numbers are 32-63 can be enabled by NVIC_EN1_R.
• Corresponding bit field is required to be set according to the IRQ number of the interrupt sources since
each register is 32 bit wide.
• IRQ number is greater than 31 the corresponding bit number can be calculated by this formula: bit
number = IRQ number - 32(n-1) where n=1 for IRQ number 0-31.
• Similarly n=2 for interrupt sources having IRQ number 32-63 and so on.
• For enabling interrupt at PC4 pin writing 1 to the bit field 2 of NVIC_EN0_R will do the same for us, as its
IRQ number is 2.
• To disable interrupts there are another registers: NVIC_DIS0_R to NVIC_DIS3_R (Interrupt
Clear Enable).
• Writing zeros to the NVIC_EN0_R through NVIC_EN3_R registers has no effect. To disable
interrupts we write ones to the corresponding bit in
the NVIC_DIS0_R through NVIC_DIS3_R register.
NVIC Interrupt Set Enable Register (NVIC_ENe_R)
• Ex: Falling Edge sensetive switch in PC4 (PORT C PIN 4)
• #define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100)) // IRQ 0 to 31
Set Enable Register
• NVIC_EN0_R |= 0x4; // enable interrupt 2 (3rd bit) in NVIC for PORTC
• #define NVIC_EN0_INT2 0x00000004 // Interrupt 2 (3rd bit) enable for PORTC
Enable 32-Enable Bits
Address
Register 0 1 2 3 4 5 6-29 30 31
0xE000E
NVIC_EN0_R PORTA PORTB PORTC PORTD PORTE UART0 ... PORTF PORTG
100
0xE000E
NVIC_EN1_R PORTH UART2 SSI1 Timer3A Timer3B I2C1 ... UART6 UART7
104
WTimer0 0xE000E
NVIC_EN2_R ... ... ... ... I2C2 I2C3 ... WTimer0B
A 108
0xE000E
NVIC_EN3_R WT1A WT1B WT2A WT2B WT3A WT3B ... GPIOQ2 GPIOQ3
10C
 GPIO Raw Interrupt Status
(GPIO_PORTx_RIS_R)
• For edge-detect interrupts, this bit is cleared by writing a 1 to the
corresponding bit in the GPIOICR register.
• For a GPIO level-detect interrupt, the bit is cleared when the level is
deasserted.
• GPIO_PORTC_RIS_R

Bit Bit Name Description

GPIO Interrupt Raw Status
7-0 RIS 0: An interrupt condition has not occurred on the corresponding pin.
1: An interrupt condition has occurred on the corresponding pin.
GPIO Masked Interrupt Status
(GPIO_PORTx_MIS_R)
• For edge-detect interrupts, this bit is cleared by writing a 1 to the
corresponding bit in the GPIOICR register.
• For a GPIO level-detect interrupt, the bit is cleared when the level is
deasserted.
•
Bit Bit Name Description
GPIO Masked Interrupt Status
0: An interrupt condition on the corresponding pin is masked or has not
7-0 MIS occurred.
1: An interrupt condition on the corresponding pin has triggered an
interrupt to the interrupt controller.
 Interrupt Latency
• The Cortex-M3/M4 processor has the minimum interrupt entry latency of 12-
cycles and interrupt exit latency of 10- cycles. Achieving these minimum
interrupt entry and exit latencies requires a number of conditions to be
fulfilled.
 Device Interrupt Configuration
• Each device interrupt configuration has two components.
• One configuration is performed for the device using the corresponding registers,
• Interrupt Vector Table configuration (startup.s)
• Second configuration is performed for the interrupt vector table and implementation of
associated ISR.
• ISR Implementation
• //Interrupt service routine for Port C
void GPIOC_Handler(void){
// Take the apropriate action in response to interrupt ... ...
// Clear the interrupt status flag before exiting ISR
}
• In C, we enable and disable interrupts by calling the functions
EnableInterrupts() and DisableInterrupts() respectively.
 Exception States
• Inactive: The exception is not active and not pending.
• Pending: The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change
the state of the corresponding interrupt to pending.
• Active: An exception that is being serviced by the processor but has
not completed. Note: An exception handler can interrupt the
execution of another exception handler. In this case, both
exceptions are in the active state.
• Active and Pending. The exception is being serviced by the
processor, and there is a pending exception from the same source.
 Interrupt Terminology
• To arm a device means to allow the hardware trigger to interrupt.
• Conversely, to disarm a device means to shut off or disconnect the hardware
trigger from the interrupts.
• Each potential interrupting trigger has a separate arm bit. One arms a trigger if one is
interested in interrupts from this source.
• Conversely, one disarms a trigger if one is not interested in interrupts from this source.
• To enable means to allow interrupts at this time.
• Conversely, to disable means to postpone interrupts until a later time.
• On the ARM Cortex-M processor there is one interrupt enable bit for the
entire interrupt system. We disable interrupts if it is currently not convenient
to accept interrupts. In particular, to disable interrupts we set the I bit in
PRIMASK.
• In C, we enable and disable interrupts by calling the functions
EnableInterrupts() and DisableInterrupts() respectively.
 Check for reading
• ARM Cortex-M4 User Guide (Interrupts, exceptions, NVIC)
• Sections 2.1.4, 2.3 – Exceptions and interrupts
 CMSIS Interrupt Number
CMSIS Interrupt Number
/****** Cortex-M4 System Exceptions ********************************************************/
NonMaskableInt_IRQn = -14, /* 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Cortex-M4 Usage Fault Interrupt System */
SVCall_IRQn = -5, /* 11 Cortex-M4 SV Call Interrupt Exceptions */
DebugMonitor_IRQn = -4, /* 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 Cortex-M4 System Tick Interrupt */
/****** Peripheral Interrupt Numbers *******************************************************/
WWDG_IRQn = 0, /* Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /* PVD/PVM1,2,3,4 through EXTI Line detection Interrupts */
TAMP_STAMP_IRQn = 2, /* Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /* RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /* FLASH global Interrupt */
RCC_IRQn = 5, /* RCC global Interrupt */
EXTI0_IRQn = 6, /* EXTI Line0 Interrupt */
... Peripheral
Interrupts