MIT SCHOOL OF COMPUTING

Lab Manual
DIGITAL ELECTRONICS
AND LOGIC DESIGN
LABORATORY

F.Y. B. Tech.

(2023 Course)

Department of Computer Science and Engineering

 MIT SCHOOL OF COMPUTING

PREFACE

Every day digital concepts are being applied to problems that could only be solved by analog methods
several years ago. Fast and reliable solutions using digital techniques proved the tremendous power
and usefulness of digital electronics. Now a day’s digital circuits are used in wide variety of industrial
and consumer products such as automated industrial machinery, pocket calculators, digital computers,
digital watches and TV games.
This laboratory deals with the basic understanding of the digital electronics and provides thorough
understanding of principles and design of digital applications. In Digital laboratory, theory comes alive
and practical hands-on skills are learnt; a balance is struck between theory and practice.
This laboratory manual is prepared by referring to various standard books, which help the students to
perform the experiments. Students are not expected to copy the contents of the manual as it is. They
must understand the concepts given in the manual and write journal on their own. The manual is
prepared as per MIT ADT University syllabus and accordingly the practical assignments are discussed
in the manual. However, students can go beyond this set and perform extra practical assignments.
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INDEX

Sr. Page
Title
No. No.

1 Verification of Logic gates/ Universal Gates. 1

Implementation of the Given Boolean Function using Logic Gates in Both SOP 6
2
and POS Forms.
3 Design & implement 4 bit BCD to Gray Code Converter 10
4 Design & implement 4 bit BCD to Excess-3 Code Converter 15
5 Design & implement Single bit Magnitude comparator using basic gates 21
Design & implementation of multiplexer/demultiplexer using basic gates and 27
6
verification of Multiplexer IC 74153
a. Design & implementation of 4:1 multiplexer using basic gates
b. Verification of IC 74153.
c. Realization of Boolean Expressions using IC 74153.
d. Implementation of 8:1 MUX with IC 74153.
e. Design & implementation of 1:2 Demultiplexer using basic gates.
7 Design & implementation of Asynchronous counter……………………………. 35
a. 2 bit up counter
b. 2 bit down counter
8 Design & implementation of Synchronous counter……………………………… 39
a. 2 bit up counter
b. 2 bit down counter
9 Design & implementation of Ring counter & Johnson counter 45
a. Verification of Universal shift register IC 74194
b. Design & implement 4 bit ring counter using IC 74194
c. Design & implement 4 bit Twisted ring counter using IC 74194
IC Pin Diagrams 53
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Experiment No:1
Title: Logic gates/ Universal Gates.

After completion of this experiment, students will be able to:

● Express Truth Table of logic gates
● Realize logic gates using universal gates.

Aim: Verification of Logic Gates/universal gates

Apparatus: Digital Trainer kit, connecting wires, ICs required as per the hardware requirement.

Theory: In electronics, a logic gate is an idealized or physical device implementing a Boolean

function; that is, it performs a logical operation on one or more logical inputs, and produces a single
logical output. Depending on the context, the term may refer to an ideal logic gate, one that has for
instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device.
Logic gates are primarily implemented using diodes or transistors acting as electronic switches. With
amplification, logic gates can be cascaded in the same way that Boolean functions can be composed,
allowing the construction of a physical model of all of Boolean logic, and therefore, all of the
algorithms and mathematics that can be described with Boolean logic.
Logic circuits include such devices as multiplexers, registers, arithmetic logic units (ALUs),
and computer memory, all the way up through complete microprocessors, which may contain more
than 100 million gates.
NAND and NOR gates can be used to realize all the operations of the basic gates. Hence, it is
called as Universal gates.
Components required:

Sr. No NAME OF THE COMPONENT IC NUMBER

1 AND Gate 7408

2 OR Gate 7432
3 NOT gate 7404
4 Ex-OR Gate 7486
5 Ex-NOR Gate 74266
6 NAND Gate 7400
7 NOR Gate 7402
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NOT GATE

OR GATE

AND GATE

UNIVERSAL GATES
NAND GATE
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NOR GATE

IMPIMENTATION OF BASIC GATES USUNG UNIVERSAL GATES

Realisation of AND Operation using NAND GATE

Realisation of OR Operation

Realisation of NOT Operation

Realisation of NOR Gate

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Realization of Ex-OR Operation

REALIZATION OF NOR As

AND Operation

OR Operation

NOT Operation

EX-OR Operation

Conclusion:
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References:
1. R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2. James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage Learning
publication.
3. Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata McGraw
Hill publication.
 MIT SCHOOL OF COMPUTING

Experiment No:2
Title: Implementation of Boolean Function
After completion of this experiment, students will be able to:
● Express Boolean expression using logic gates
● Check equivalence of two Boolean expressions using logic gates
● Check equivalence of two logic circuits consisting of multiple gates

Aim: Implementation of the Given Boolean Function using Logic Gates and universal gates
in Both SOP and POS Forms.
A. Y = A’B + AB’
B. Y = (A’ + B) . (A + B’)
C. Y = AB’C’ + A’BC’ + ABC
D. Y = (A+B’+C’) . (A’+B+C’) . (A’+B’+C)

Apparatus: Digital Trainer kit, Connecting wires, ICs required as per the hardware requirement.

Theory:
A. Y = A’B + AB’

B. TRUTH TABLE:

A B A’ B’ A’B AB’ Y
0 0 1 1 0 0 0
0 1 1 0 1 0 1
1 0 0 1 0 1 1
1 1 0 0 0 0 0

LOGIC DIAGRAM:
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HARDWARE REQUIREMENTS:

Sr. No. IC Description Quantity

1 7408 AND 1
2 7432 OR 1
3 7404 NOT 1

B. Y = (A’ + B) . (A + B’)

TRUTH TABLE:

A B A’ B’ A’+B A+B’ Y
0 0 1 1 1 1 1
0 1 1 0 1 0 0
1 0 0 1 0 1 0
1 1 0 0 1 1 1
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LOGIC DIAGRAM:

HARDWARE REQUIREMENTS:

Sr. No. IC Description Quantity

1 7408 AND 1
2 7432 OR 1
3 7404 NOT 1
MIT SCHOOL OF COMPUTING

For Equation C and D students should draw Truth Table, Logic

Diagram and Hardware requirements.

Conclusion:

References:
1. R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2. James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage Learning
publication.
3. Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata McGraw Hill
publication.
MIT SCHOOL OF COMPUTING

Experiment No: 3
Title: BCD to Gray Code converter
After completion of this experiment, students will be able to:
⮚ Explain the Combinational Logic Circuit.
⮚ Explain the design steps of combinational Logic circuit.
⮚ Explain the different types of codes like BCD, Gray code.
⮚ Explain the applications of all codes.
⮚ Learn the importance of weighted and non-weighted code.
⮚ Learn the necessity and application of code conversion.

Aim: To design and implement 4 bit BCD to Gray code converter.

Apparatus: Digital Trainer kit, Connecting wires, ICs 7404,7408,7432.

Theory:

There is a wide variety of binary codes used in digital systems. Some of these codes are binary- coded
-decimal (BCD), Excess-3, Gray, octal, hexadecimal, etc. Often it is required to convert from one code
to another. For example, the input to a digital system may be in natural BCD and output may be 7-
segment LEDs. The digital system used may be capable of processing the data in straight binary format.
Therefore, the data has to be converted from one type of code to another type for different purpose.
The various code converters can be designed using gates.
1) Gray Code:
It is a modified binary code in which a decimal number is represented in binary form in such a way
that each Gray- Code number differs from the preceding and the succeeding number by a single bit.
(E.g., for decimal number 5 the equivalent gray code is 0111 and for 6 it is 0101. These two codes
differ by only one-bit position i. e. third from the left.) Whereas by using binary code there is a
possibility of change of all bits if we move from one number to other in sequence (e.g., binary code
for 7 is 0111 and for 8 it is 1000). Therefore, it is more useful to use Gray code in some applications
than binary code.
The Gray code is a non-weighted code i.e., there are no specific weights assigned to the bit positions.
Like binary numbers, the Gray code can have any no. of bits. It is also known as reflected code.
MIT SCHOOL OF COMPUTING

Applications:
1. Important feature of Gray code is it exhibits only a single bit change from one code word to the
next in sequence. This property is important in many applications such as Shaft encoders where error
susceptibility increases with the number of bit changes between adjacent numbers in sequence.
2. It is sometimes convenient to use the Gray code to represent the digital data converted from the
analog data (Outputs of ADC).
3. Gray codes are used in angle-measuring devices in preference to straightforward binary encoding.
4. Gray codes are widely used in K-map
The disadvantage of Gray code is that it is not good for arithmetic operation

2) BCD Code:
Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-bit binary
code. For example (23)10 is represented by 0010 0011 using BCD code rather than(10111)2 This code
is also known as 8-4-2-1 code as 8421 indicates the binary weights of four bits(23, 22, 21, 20). It is easy
to convert between BCD code numbers and the familiar decimal numbers. It is the main advantage of
this code. With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code, only
10 of these are used. The six code combinations (1010 to 1111) are not used and are invalid.
Applications: Some early computers processed BCD numbers. Arithmetic operations can be
performed using this code. Input to a digital system may be in natural BCD and output may be 7-
segment LEDs.
It is observed that more number of bits are required to code a decimal number using BCD code than
using the straight binary code. However, in spite of this disadvantage it is very convenient and useful
code for input and output operations in digital systems.

Fig.1: BCD Coded Decimal Representation

BCD To Gray code Conversion
In this conversion, the input straight BCD number can easily be converted to its Gray code equivalent.
1. Record the most significant bit as it is.
2. EX-OR this bit to the next position bit, record the resultant bit.
3. Record successive EX-ORed bits until completed.
4. Convert 0011 BCD to Gray.
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0 0 1 1 BCD code

+ + +

0 0 1 0
BCD code Gra
(MSB) (LSB)

Fig.2: BCD To Gray code Conversion

Design:

BCD to Gray Code conversion:

1) Truth Table:
Table 1: BCD To Gray Code Conversion
INPUT (BCD CODE) OUTPUT (GRAY CODE)
D3 D2 D1 D0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
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3)
2) K-Map for Reduced Boolean Expressions of 4) Logic Diagram:
Each Output:
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BCD TO GRAY CODE CONVERTER

Fig.4: Logic Diagram for 4 bit BCD to Gray code Converter

4 ) Hardware Requirements:

Sr. No. IC Description Quantity

2 7408 AND 1
3 7432 OR 1
4 7404 NOT 1
Testing:
1. Make the connections as shown in Fig.
2. Switch ON the supply and verify the truth table.

Conclusion:

References:
1.) R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2.) James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage Learning
publication.
3.) Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata McGraw Hill
publication.
MIT SCHOOL OF COMPUTING

Experiment No: 4
Title: BCD to Excess-3 Code converter
After completion of this experiment, students will be able to:
⮚ Explain the Combinational Logic Circuit.
⮚ Explain the design steps of combinational Logic circuit.
⮚ Explain the different types of codes like BCD, Excess-3 code.
⮚ Explain the applications of all codes.
⮚ Learn the importance of weighted and non-weighted code.
⮚ Learn the necessity and application of code conversion.

Aim: To design and implement 4 bit BCD to Excess-3 code converter and verify the truth table.

Apparatus: Digital Trainer kit, Connecting wires, ICs 7404,7486,7408,7432.

Theory:
There is a wide variety of binary codes used in digital systems. Some of these codes are binary- coded
-decimal (BCD), Excess-3, Gray, octal, hexadecimal, etc. Often it is required to convert from one code
to another. For example, the input to a digital system may be in natural BCD and output may be 7-
segment LEDs. The digital system used may be capable of processing the data in straight binary format.
Therefore, the data has to be converted from one type of code to another type for different purpose.
The various code converters can be designed using gates.
1) Binary Code:
It is straight binary code. The binary number system (with base 2) represents values using two
symbols, typically 0 and 1. Computers call these bits either as off (0) or on (1). The binary code are
made up of only zeros and ones, and used in computers to stand for letters and digits. It is used to
represent numbers using natural or straight binary form.
It is a weighted code since a weight is assigned to every position. Various arithmetic operations can
be performed in this form. Binary code is weighted and sequential code.
2) BCD Code:
Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-bit binary
code. For example (23)10 is represented by 0010 0011 using BCD code rather than (10111)2 This code
is also known as 8-4-2-1 code as 8421 indicates the binary weights of four bits (23, 22, 21, 20). It is easy
to convert between BCD code numbers and the familiar decimal numbers. It is the main advantage of

this code. With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only
MIT SCHOOL OF COMPUTING
10 of these are used. The six code combinations (1010 to 1111) are not used and are invalid.
Applications: Some early computers processed BCD numbers. Arithmetic operations can be
performed using this code. Input to a digital system may be in natural BCD and output may be 7-
segment LEDs.
It is observed that more number of bits are required to code a decimal number using BCD code than
using the straight binary code. However, in spite of this disadvantage it is very convenient and useful
code for input and output operations in digital systems.

Fig.1: BCD Coded Decimal Representation

3) EXCESS-3 Code:
Excess-3, also called XS3, is a non-weighted code used to express decimal numbers. It can be used for
the representation of multi-digit decimal numbers as can BCD. The code for each decimal number is
obtained by adding decimal 3 and then converting it to a 4-bit binary number. For e.g. decimal 2 is
coded as 0010 + 0011 = 0101 in Excess-3 code.

This is self-complementing code which means 1’s complement of the coded number yields 9’s
complement of the number itself. Self-complementing property of this helps considerably in
performing subtraction operation in digital systems, so this code is used for certain arithmetic
operations.

BCD To Excess – 3 Code Conversion:

Convert BCD 2 i. e. 0010 to Excess – 3 code
For converting 4 bit BCD code to Excess – 3, add 0011 i. e. decimal 3 to the respective code using
rules of binary addition.
0010 + 0011 = 0101 – Excess – 3 code for BCD 2
Excess – 3 Code To BCD Conversion:
The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3 i.e.
0011 from 4 bit Excess-3 digit.
e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.
0101-0011= 0010- BCD for 2
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Design:

4 bit BCD To Excess-3 Code Conversion:

1) Truth Table:
Table 1: BCD To Excess-3 Code Conversion
INPUT (BCD CODE) OUTPUT (EXCESS-3 CODE)
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
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2) K-Map for Reduced Boolean Expressions of Each Output:

Fig.2: K-Map for Reduced Boolean Expressions Of Each Output (Excess-3 Code)

We can rewrite the expression for each output as follows:

𝐸0 = 0 (1)
𝐸1 = 1 ⊙ 𝐵0 (2)
𝐸2 = 𝟐 ⊕ (𝑩𝟏 + 𝑩𝟎) (3)
𝐸3 = 𝑩𝟑 + 𝑩(𝑩𝟏 + 𝑩𝟎) (4)
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3) Logic Diagram:

BCD TO EXCESS-3 CONVERTER

Fig.3: Logic Diagram for BCD to Excess-3 Code Conversion

4 ) Hardware Requirements:

Sr. No. IC Description Quantity

1 7486 XOR 1
2 7408 AND 1
3 7432 OR 1
4 7404 NOT 1
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TESTING:
1. Make the connections as shown in Fig.
2. Switch ON the supply and verify the truth table.

Conclusion:

References:
1. R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2. James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage Learning
publication.
3. Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata McGraw Hill
publication.
MIT SCHOOL OF COMPUTING

Experiment No: 5

Title: Design & Implementation of single bit magnitude comparator.

After completion of this experiment, students will be able to:
⮚ Understand magnitude comparator circuit.
⮚ Design and implement 1 bit and 2-bit comparator.

Aim: a. Design and Implement 1 bit comparator using logic gates.

b. Design and Implement 2-bit comparator using logic gates.
Apparatus: Digital Trainer kit, Connecting wires, ICs 7404, 7408, 7432.

Theory:
A magnitude comparator is a combinational circuit that compares two given numbers and determines
whether one is equal to, less than or greater than. The output is in the form of three binary variables
representing the conditions A = B, A>B and A<B, if A and B are the two numbers being compared. If
the two numbers, let us say, are four-bit binary numbers and are designated as (A3 A2 A1 A0) and (B3
B2 B1 B0), the two numbers will be equal if all pairs of significant digits are equal, that is, A3= B3, A2=
B2, A1= B1 and A0= B0. In order to determine whether A is greater than or less than B, we inspect the
relative magnitude of pairs of significant digits, starting from the most significant position. The
comparison is done by successively comparing the next adjacent lower pair of digits if the digits of the
pair under examination are equal. The comparison continues until a pair of unequal digits is reached.

Fig.1: Block diagram of comparator

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Design:

A. Design and implement 1-bit comparator using Logic gates.

Truth Table:

K-Map:
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Logic Diagram:

Fig.2: Logic Diagram of 1-bit comparator

B. Design and implement 2-bit comparator using Logic gates.

Truth table

:
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K-MAP:
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Logic Diagram:

Fig.3: Logic Diagram of 2-bit comparator

Testing:

● Make the connection according to circuit diagram

● Connect Vcc & GND to IC.
● Verify the functionality of given function according to truth table.
MIT SCHOOL OF COMPUTING

Conclusion:

References:
1. R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2. James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage Learning
publication.

3. Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata McGraw
Hill publication.
MIT SCHOOL OF COMPUTING

Experiment No: 6

Title: Implementation of logic functions using multiplexer IC 74153

& Demultiplexer using Logic gates
After completion of this experiment, students will be able to:
⮚ Familiarize with the structure and the operation of Multiplexer, Demultiplexer
⮚ Differentiate between Multiplexer, Demultiplexer depending upon number of
inputs, outputs and select lines.
⮚ Implement logical functions using multiplexer and demultiplexer.
⮚ Learn how to implement a large multiplexer using a small Multiplexer as the building block.
⮚ Minimize the hardware by using MUX.
⮚ Recognize demultiplexer as a data distributor and multiplexer as a data selector.

Aim:
⮚ Design and Implement 4:1 Mux using Logic gates.
⮚ Verification of Functional table of IC 74153.
⮚ Verification of Sum of Product (SOP) and Product of Sum (POS) with the help of
given Boolean expression.
a. Y = ∑m (1, 2, 3)
b. Y = ∏ M (0, 2)
⮚ Implement the following Boolean Function using single 4:1
Mux. F (A, B, C) = ∑m (1,3,5,6)
⮚ Verify the functional table using cascading of two ultiplexers.
(Implementation of 8:1 MUX using two 4:1 MUX)
⮚ Design and Implement 1:2 Demux using Logic gates.

Apparatus: Digital trainer kit, connecting wires, IC 74153, IC 7408,IC 7432, IC 7400.
Theory: 1. Multiplexer

Fig.1: Block diagram of Multiplexer

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● Multiplexer is a digital switch that allows digital information from several sources to be
routed onto a single output line. Basic multiplexer has several data inputs and a single
output line.
● The selection of a particular input line is controlled by a set of selection line.
● There are 2n input lines & n is the number of selection line whose bit combinations
determines which input is selected. It is “Many into One”.

2. Significance and application of multiplexer

 No need to simplify logic expression.
 The IC package count is minimized.
 Logic design is simplified.
 It is possible to expand the range of inputs for multiplexers beyond the available Range in
the integrated circuits. This can be accomplished by interconnecting several multiplexers.
 So it is used in the data acquisition circuit
 In designing the combinational circuit
 To minimize number of connections in communication system were we need to handle
thousands of connections. Ex. Telephone exchange

2. Demultiplexer.
 Demultiplexer is a logic used to perform exactly reverse function performed by
multiplexer.
 It accepts a single input and distributes among several outputs.
 The selection of a particular output line is controlled by a set of selection line.
 There are n input lines & 2m is the number of selection line whose bit combinations
determine which output to be selected.
3. Difference between Mux / Demux / Decoder.

Point Multiplexer Demultiplexer Decoder

Input Many input lines Single input line Many inputs line also
Acts as select line
Output Single output line Many outputs line Many outputs line,
Active low output
Select line 2m = n n = 2m Enable inputs used
MIT SCHOOL OF COMPUTING

Design: Design and Implement 4:1 mux.

Theory: 4x1 Multiplexer has four data inputs D0, D1, D2 & D3 two selection lines s 1 & s0 and one
output Y. One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines. Truth table of 4x1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

From Truth table, we can directly write the Boolean function for output, Y as

Y=(S1′S0′)D0+(S1′S0)D1+(S1S0′)D2+(S1S0)D3
We can implement this Boolean function using Inverters, AND gates & OR gate.

Fig.2: Implementation Of 4:1 Using Basic Gates

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1. Verification of Functional table of IC 74153

Verification of Sum of Product (SOP) and Product of Sum (POS) with the help of given
Boolean expression.
a. Y = ∑m (1, 2, 3)
b. Y = ∏ M (0, 2)
a. Y = ∑m (1, 2, 3) Sum of Product Form (SOP)

Truth Table:

INPUTS Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
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Logic Diagram:

Fig.3: Logic Diagram

Hardware Requirement:

Sr. No. IC Description Quantity

1 74153 Dual 4:1MUX 01

b. Y = ∏ M (0, 2) Product of Sum Form

(POS) Truth Table:

INPUTS Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Logic Diagram:

Fig.4: Logic Diagram

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Hardware Requirement:

Sr. No. IC Description Quantity

1 74153 Dual 4:1MUX 01

Implement the following Boolean Function using single 4:1 Mux.

F (A, B, C) = ∑m (1,3,5,6)
Truth Table
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
We have to design using 4:1 Mux only hence we use Hardware Reduction Method.
Implementation Table:

D0 D1 D2 D3
A’ 0 1 2 3
A 4 5 6 7
Final I/P to MUX 0 1 A A’

Logic Diagram:

Fig.5: Logic Diagram

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Sr. No. IC Description Quantity

1 74153 Dual 4:1MUX 01

2 7404 Hex Inverter 01

Design and Implement 8:1 using two 4:1 mux as cascading of two 4:1 multiplexer results in 8:1

E= S2 S1 S0 output
0 0 0 D0
0 0 1 D1 Multiplexer1
0 1 0 D2
0 1 1 D3

1 0 0 D4
1 0 1 D5 Multiplexer2
1 1 0 D6
1 1 1 D7

a. Use Enable pin of mux as third select line.

b. Similarly, 16:1 mux can be implemented using two 8:1 mux IC’s.
c. Draw Multiplexer Tree according to given
equation (Specify number of IC required)

Logic Diagram:

Fig.6: Logic Diagram

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Sr. No. IC Description Quantity

1 74153 Dual 4:1MUX 01

2 7404 NOT Gate 01

3 7432 OR Gate 01

Implementation of 1:2 Demultiplexer using Logic Gates:

Fig.7: Logic Diagram and Truth table

Hardware Requirement:
Sr. No. IC Description Quantity
1 7408 AND Gate 01
2 7400 NAND Gate 01

Conclusion:

References:

1. R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2. James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage Learning
publication.
3. Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata McGraw
Hill publication.
 MIT SCHOOL OF COMPUTING

Experiment No: 7

Title: Study of Asynchronous / Ripple Counter

Aim: Design and implementation of 2 bit Up and Down asynchronous counter using master slave
JK flip-flop IC 7476.

After completion of this experiment, students will be able to:

⮚ Differentiate between combinational and sequential circuit.
⮚ Explain asynchronous counter as a ripple counter.
⮚ Familiarize with the internal structure of master slave jk flip-flop ic 7476.
⮚ Differentiate between up, down asynchronous counter.
⮚ Draw the timing diagram for 2 bits up, down asynchronous counter.

Apparatus: Digital trainer kit, Connecting wires, IC 7476 (MS-JK Flip-flop)

Theory:
1) Asynchronous counter:

A digital counter is a set of flip flop. When state changes in response to pulse applied at
i/p to counter. The flip flop is connected such that their combined state at any time is binary equivalent
of total no. of pulses that have occurred up to that time. Thus, its name implies a counter is used to
count pulse. A counter is used as frequency dividers. To obtain waveform with frequency that is
specific fraction of clock frequency.
Counter may be Asynchronous or synchronous. The Asynchronous counter is also
called as ripple counter. An Asynchronous counter uses T flip flop to perform a counting function. The
actual hardware used is usually J-K flip flop connected to logic1.Even D flip flops may be used here.
In asynchronous counter commonly called ripple counter, the first flip-flop is clocked by the external
clock pulse & then each successive flip-flop is clocked by the Q or /Q’ output the previous flip-flop.
Therefore, in an asynchronous counter the flip-flop are not clocked simultaneously. The input of MS-
JK is connected to VCC because when both inputs are one output is toggled. As MS-JK is negative
edge triggered at each high to low transition the next flip-flop is triggered. On this basis the
design is done for MOD-8 counter.
2) Up Counter:
Fig 1 shows 2-bit Asynchronous Up Counter. Here Flip-flop A act as a MSB Flip-flop and
Flip-flop B can act as a LSB Flip-flop. Clock pulse is connected to the Clock of Flip-flop B. Output
 MIT SCHOOL OF COMPUTING
of Flip-flop B (QB) is connected to clock of next flip-flop (i.e Flip-flop A) and so on. As soon as clock
pulse changes output is going to change (at the negative edge of clock pulse) as a Up count sequence.
For 2-bit Up counter Truth table is as shown below.
3) Down Counter:
Fig 2 shows 2-bit Asynchronous Down Counter. Here Flip-flop A act as a MSB Flip-flop and
Flip-flop B can act as a LSB Flip-flop. Clock pulse is connected to the Clock of Flip-flop B. Output of
Flip-flop b (QB’) is connected to clock of next flip-flop (i.e Flip-flop A) and so on. As soon as clock
pulse changes output is going to change (at the negative edge of clock pulse) as a Down count
sequence. For 2-bit Down counter Truth table is as shown below.
In both the counters Inputs J and K are connected to Vcc, hence J-K Flip flop can work in toggle mode.
Preset and Clear both are connected to logic 1.

LOGIC DIAGRAM:

Fig.1: 2 Bit Asynchronous Up Counter

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Fig 2: 2 Bit Asynchronous Down Counter

Hardware Requirements:

Sr. No. IC Description Quantity

1 7476 Dual J-K Flip-Flop 2

Timing Diagram:

1. 2 Bit Asynchronous Up Counter

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2. 2 Bit Asynchronous Down Counter

Testing:
1. Make the connection according to circuit diagram
2. Connect Vcc & GND to IC.
3. Verify the functionality of given function according to truth table.

Conclusion:

References:
1. R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2. James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage Learning
publication.
3. Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata McGraw
Hill publication.
 MIT SCHOOL OF COMPUTING

Experiment No: 8

Title : Study of Synchronous Counter

Aim: To design and implement 2 bits UP and Down Synchronous Counter using MS-JK Flip-flop.

After completion of this experiment, students will be able to:

⮚ Differentiate between Asynchronous and Synchronous Sequential circuit.
⮚ Familiarize with Excitation tables of flip-flops.
⮚ Differentiate between truth table, excitation table and state table.
⮚ Explain the concept of frequency in synchronous counter.
⮚ Draw the timing diagram for 2 bits Up, Down synchronous counter.

Apparatus: Digital Trainer Kit, Connecting Wires, IC 7476 (MS-JK Flip-flop)

Theory:

Counters: counters are logical device or registers capable of counting the no of states or no of clock
pulse arriving at its clock input where clock is a timing parameter arriving at regular intervals of time,
so counters can be also used to measure time & frequencies. They are made up of flip flops. Where the
pulse are counted to be made of it goes up step by step & the o/p of counter in the flip flop is decoded
to read the count to its starting step after counting n pulse in case of module & counters.

Types of Counters:

Counter are of two types:

1) Synchronous counter.
2) Asynchronous counter.

1) SYNCHRONOUS COUNTER:

When counter is clocked such that each flip flop in the counter is triggered at
the same time, the counter is called as synchronous counter.
Synchronous binary counter has regular & can easily be constructed with complimentary flip
flop & gates. The gates propagation delay at reset time will not be present or we may say will not
occur.
 MIT SCHOOL OF COMPUTING
Types of synchronous counter:
1) Synchronous up counter.
2) Synchronous down counter.

Design:
Excitation Table of JK FlipFlop

Present State Next State Flip Flop Inputs

QA QA+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

1) Synchronous up counter:
The up-counter counts binary from 0 to 3 i.e. (00 to 11) for this we are using JK flip flop.
State table for synchronous up counter:
Present State Next State Flip Flop Inputs
QB QA QB+1 QA+1 JB KB JA KA
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1

K-Map
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Logic Diagram:

Hardware Requirements:

Sr. No IC Quantity
1 7476 1

2)Synchronous down counter:

This is used to count pulse from 3-0 i.e. (11-00) for this also 1 IC of 74LS76 IS required & hence
we use 2 JK flip flops.

State table for synchronous down counter:

Present State Next State Flip Flop Inputs

QB QA QB+1 QA+1 JB KB JA KA
1 1 1 0 X 0 X 1
1 0 0 1 X 1 1 X
0 1 0 0 0 X X 1
0 0 1 1 1 X 1 X
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K-Map:

Logic Diagram:
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Hardware Requirements:

Sr. No IC Description Quantity

1 7476 Dual J-K Flip-Flop 1

Timing Diagram:

2 Bit Synchronous Up Counter

2 Bit Synchronous Down Counter

Testing:
● Make the connection according to circuit diagram
● Connect Vcc & GND to IC. Verify the functionality of given function according to truth
table.

Conclusion:
MIT SCHOOL OF COMPUTING

References:
1. R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2. James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage
Learning publication.
3. Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata
McGraw Hill publication.
 MIT SCHOOL OF COMPUTING

Experiment No: 9

Title: Study of Shift Register, Ring Counter and Twisted Ring (Johnson) Counter

Aim: To design and test Ring counter and Johnson counter using Shift register IC 74194
After completion of this experiment, students will be able to:
⮚ Familiarize with Shift register IC 74194
⮚ Differentiate between Ring counter and Johnson Counter circuit.
⮚ Explain the concept of mod n and mod 2n counter.

Apparatus: Digital Trainer Kit, Connecting wires, IC 74194 (Shift Register), IC 7404 (NOT
Gate)

Theory:
A shift register is a digital device used for storage and transfer of data. The data to be stored could be
the data appearing at the output of an encoding matrix before they are fed to the main digital system
for processing or they might be the data present at the output of a microprocessor before they are fed
to the driver circuitry of the output devices. The shift register thus forms an important link between
the main digital system and the input/output channels. The shift registers can also be configured to
construct some special types of counters that can be used to perform a number of arithmetic operations
such as subtraction, multiplication, division, complementation, etc. The basic building block in all shift
registers is the flip flop, mainly a D-type flip-flop. Although in many of the commercial shift register
ICs their internal circuit diagram might indicate the use of R-S flip-flops, a careful examination will
reveal that these R-S flip-flops have been wired as D flip-flops only.
The storage capacity of a shift register equals the total number of bits of digital data it can store,
which in turn depends upon the number of flip-flops used to construct the shift register. Since each
flip-flop can store one bit of data, the storage capacity of the shift register equals the number of flip-
flops used. As an example, the internal architecture of an eight-bit shift register will have a cascade
arrangement of eight flip-flops. Based on the method used to load data onto and read data from shift
registers, they are classified as serial-in serial-out (SISO) shift registers, serial-in parallel-out (SIPO)
shift registers, parallel-in serial-out (PISO) shift registers and parallel-in parallel-out (PIPO) shift
registers. A shift register, unlike a counter, has no specified sequence of states. However, if the serial
output of the shift register is fed back to the serial input, we do get a circuit that exhibits a specified
sequence of states. The resulting circuits are known as shift register counters. Depending upon the
nature of the feedback, we have two types of shift register counter, namely the ring counter and the
shift counter, also called the Johnson counter.

Universal Shift Register IC74194:

IC 74194 is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high-speed multifunctional
sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial;
shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers
 MIT SCHOOL OF COMPUTING

Fig 5. Universal Shift Register

Fig 6. Pin diagram of 74194

Function table of IC 74194:

Control Inputs Operation

S0 S1
0 0 No Operation
0 1 Shift left (Data at DSL)
1 0 Shift right (Data at DSR)
1 1 Parallel Loading
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We know that a register may operate in any one of the modes like SISO, SIPO, PISO, PIPO or
bidirectional. If a register can be operated in all the five possible ways, it is known as “Universal Shift
register’. Fig.5 shows logic symbol of IC 74194, a 4 bit bidirectional universal shift register.
As shown in fig., it has 4 parallel data inputs A, B, C, D and S0, S1 are the control inputs.
Shift Right is accomplished synchronously with the positive edge of the clock when S0 is High
and S1 is Low. Data in this mode are entered at the shift right data input. (DSR).
When S0 is Low and S1 is High, data bits shifts left synchronously with the clock and new data
are entered at the shift left data input (DSL).
Parallel loading, which is synchronous with a positive transition of the clock is accomplished
by applying the 4 bits of data to the parallel inputs and a High to the S0 and S1 inputs.
When S0 and S1 are Low, operation is clock inhibit (do nothing).

Ring Counter (Divide by ‘N’ counter/N:1 scalar)

A ring counter is obtained from a shift register by directly feeding back the true output of the output
flip-flop to the data input terminal of the input flip-flop. If D flip-flops are being used to construct the
shift register, the ring counter, also called a circulating register, can be constructed by feeding back the
Q output of the output flip-flop back to the D input of the input flip-flop. If J-K flip-flops are being
used, the Q and Q outputs of the output flip-flop are respectively fed back to the J and K inputs of the
input flip-flop.

Fig.1: Ring Counter

Truth Table:
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Timing Sequence for 4-bit Ring Counter:

Fig. 2: Timing sequence

As shown in fig.1, Q output of each stage is connected to the D input of the next stage and output of
the last stage is connected to the input of the first stage. Initially a “1” is preset into the first flipflop
and the rest of the flip flops are cleared means output of the first stage is 1 and remaining outputs are
“0” i.e QA=1 and QB, QC, QD =0.
The clock pulse produces QB=1 and remaining outputs are 0. According to clock pulse applied at the
clock input, a sequence of 4 states is produced. These states are summarized in the table. As shown in
the table, “1” is always retained in the counter and simply shifted “around the ring” advancing one
stage for each clock pulse. In this case, 4 stages of the flip flops are used so a sequence of 4 states is
produced and repeated.
The Ring counter can be used for counting the no. of pulses. The no. of pulses counted is read by
nothing which flip flop is in state “1”. No decoding circuitry is required. Since there is one pulse at the
output for each of the “N” clock pulses, this circuit is also referred to as a divide by N counter or N:1
scalar Ring counter. Ring counters can be instructed for any desired MOD No., that is “MOD N”
ring counter requires N flip-flops.
Design:
Ring Counter using shift register IC 74194 (Considering DSL serial Input)
● The fig.7 shows the circuit diagram for a 4-bit ring counter with a single circulating 1.

● Here IC 74194 universal shift register is connected so that it normally performs a left shift.
● However, when reset is asserted, it loads 0001.
 MIT SCHOOL OF COMPUTING
● Once reset is negated the IC 74194 shifts left on every clock pulse. The DSL serial input is
connected to the leftmost output (Q3 : MSB), so the next states are 0010, 0100, 1000,
0001, 0010,....
● Thus the counter visits four unique states before repeating.

Fig 7. Ring Counter using DSL serial input.

Twisted ring counter using shift register IC 74194 (Johnson counter)

A twisted ring counter, also called Johnson counter, connects the complement of the output of the last
shift register to the input of the first register and circulates a stream of one followed by zeros around
the ring. For example, in a 4-register counter, with initial register values of 0000, the repeating pattern
is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000... .
Johnson counters are often favored, not just because they offer twice as many count states from the
same number of shift registers, but because they are able to self-initialize from the all-zeros state,
without requiring the first count bit to be injected externally at start-up. The Johnson counter generates
a Gray code, a code in which adjacent states differ by only one bit.
 MIT SCHOOL OF COMPUTING

Fig. 3: Twisted Ring Counter

As shown in fig. 3, the feedback arrangement produces a unique sequence of states shown in table
below. Initially all flipflops are cleared, so all outputs QA, QB, QC and QD are zero. The output of
the last stage QD is zero, hence complement output of the last stage (QD’) is one. This connected back
to the D input of the first stage. So DA is one. The first leading edge of the clock produces QA=1 and
QB, QC QD=0. Since DB, DC, DD = 0.
The next clock pulse produces QA=1, QB=1, QC=0 and QD=0. The sequence of the states is
summarized in the table below. After 8 states same sequence is repeated. In this case, 4 bit register is
used, so the 4 bit sequence has a total of 8 states.
In general, “n” stage Johnson counter will produce a modulus of “2n”, where “n” is the number of
stages (i.e flipflops) in the counter. As shown in the table, the counter will fill up with 1s from left to
right and then it will fill up with 0s again. One advantage of this type of sequence is that is readily
decoded with 2 input AND gate.
Truth Table:
 MIT SCHOOL OF COMPUTING
Timing Sequence:

Fig. 4: Timing Sequence of Twisted Ring Counter

Design:
Twisted Ring Counter:
● The fig.8 shows the circuit diagram for a 4-bit Twisted ring counter.

● Here IC 74194 universal shift register is connected so that it normally performs a left shift.
● Initially all flip flops are clear.
● Q3 is negated and connected to the DSL input to get the Johnson counter.

Fig 8. Twisted Ring Counter using DSL serial input.

MIT SCHOOL OF COMPUTING

Testing:
1. For Ring counter do the connections as per the diagram shown in fig. 7.
2. Verify the output as per the truth table of the same.
3. For Twisted Ring counter do the connections as per the diagram shown in fig. 8.
4. Verify the output as per the truth table of the same.

Conclusion:

References:
1. R.P.Jain, ‘Modern digital electronics’, 3rd edition, Tata McGraw Hill publication.
2. James W. Bignell, Robert Donovan, ‘Digital Electronics’, 5th edition, Cengage Learning
publication.
3. Malvino, Leach, Saha ‘Digital Principles and Applications’, 6th edition, Tata McGraw
Hill publication.
MIT SCHOOL OF COMPUTING

IC PIN DIAGRAMS

7400: Quad 2-Input NAND Gate

7402: Quad 2-Input NOR Gate

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7404: Hex Inverting Gates

7408: Quad 2-Input AND Gates

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7410: Triple 3-Input NAND Gate

7432: Quad 2-Input OR Gate

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7474: Dual Positive Edge Triggered D Flip-Flop

7476: Dual Master-Slave J-K Flip-Flops

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7486: Quad 2-Input Exclusive-OR Gate

74151: 8:1 Multiplexer

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74153: Dual 4:1 Multiplexer

IC 74194 Universal Shift Register