A Novel Command Generation Method with Variable

Feedrate utilizing FGPA for Motor Drives

Ulas Yanan, Melik Dolen, A. Bugra Kou

Department of Mechanical Engineering
Middle East Technical University
Ankara 06531, Turkey
{uyaman, dolen, kbugra}@metu.edu.tr

Abstact-This paper focuses on a novel command generator for Industrial motion controller units utilize vector data tables
servo-motor drives to be used as an integral part of their motion to represent the trajectory in terms of liner patches. These
controllers. The method, which incorporates a new data cards can then perform a liner interpolation between the two
compression algorithm, is capable of generating trajectory data consecutive entries in real-time to produce the relevant
at variable rates. In this paradigm, higher-order diferences of a reference signals for the position servo-conrol loop. For
given trajectory (i.e. position) are irst computed and thus the complex trajectories the size of the vector table may exceed
resulting data are compressed via the proposed technique. The
the available resources on the system. The conventional
generation of the commands is carried out according to the feed­
machining approach does not meet the requirements of high
rate (i.e. the speed along the trajectory) set by the external logic
speed and high accurate machining. To overcome these
dynamically. The paper discusses the implementation of the
dificulties, the proposed method is implemented into the
method on a Field Programmable Gate Array (FPGA). During
conventional manufacturing process as illustrated in Fig.
implementation Very High Speed Integrated Circuit Hardware
Description Language (VHDL) is used rather than using
1.0ne of the major advantages of the method is that it can
embedded processors on the FPGA chip. The performance of the send position, velocity, and acceleration commands
method is assessed according to the resources used in the FPGA simultaneously to the controller. The purpose of compressing
chip on the development board and these results are also the servo comands is to decrease the data transfer load and
compared with the same approach without an interpolator. feedrate is given as an input to the proposed method to reduce
the error along the curves where the radius of curvature is
Keywords-command generation; data compression; FPGA; small.
adjusable feedrate; inear intepoaon
In today's technology, memory devices with large capacity
as well as multi-core processors running at high clock
I. INTRODUCTION requencies are widely available in the mrket at relatively low
Modern servo drive systems employ digital motion cost. Consequently, there is a potential for devising simple yet
controllers (DSPs, micro-controllers) to regulate precisely not very effective comand generators for computer numerically
only motor currents (electromagnetic torque) but also motor's controlled machinery that beneit fully from the properties of
angulr velocity along with the position. If the drive system is these advanced devices [1].
conigured for (digital) motion control, the relevant reference
signals (velocity or position) must be generated by a central
controller unit (host) depending on the trajectory to be
followed. These signals are eventually transferred to each
motor driver via a serial communication protocol (SERCOS,
CAN, Proibus, TCPlP, RS-232, RS-485, etc.). This approach
requently pushes the comunication interface to its liits for
high-end applications. Consequently, the objective of this
study is to develop a direct comand generator system with
vriable feedrate for servo motor drives where the commands
could be produced directly in the drive system without the
need for intermittent data transfer rom a host controller. This
Is it a Robotics Yes
FPGA based system, which could be directly embedded into a Application?
motor drive system, is expected to generate the relevant
commands by utilizing not only the (dynamically adjusted) No

speed along the traced trajectory but also decompressed data

Position, Velocity, Acceleration Commands
being produced in advance to represent trajectory to the to the Control1er

desired accuracy.

This work was supported by the Scientiic and Technological Research Figure I. CNC / Robotics Applications
Council of Turkey under the project contract I08E048.

978-1-42-5716-8110$26 .00 ©2010 IEE

 This paper focuses on a novel technique composed of three compression method described in the paper can be regarded as
consecutive prts: the irst part, which is commonly referred task-speciic since it is developed to compress the integer
as differencing in literature [2], computes the higher order position comand sequences. It may not yield better results for
differences of the trajectory data (e.g. position). Second part text or image compression.
reduces the size of the resultant data utilizing a novel
(lossless) compression technique. The last prt of the method B. FPGA-Based Command Geneation Systems
generates the comands according to the feedrate input.
Implementations of comand generation methods on
The rest of the paper is organized as follows: Section I FPGA chips re not very common in the literature due to high
represents a review of the relevant reserch ields. Section III computational complexity involved in the methods. Therefore,
describes the FPGA-based comand generation method using techniques employed on PGA have simpliications and/or
differencing plus compression and its hardware implementation include error compensation modules into the systems. For
is presented in Section IV. Section V presents the results of the instance, Su, Hu, and Cheng [11] developed a motion
proposed method employed on the test case and compres the comand generation chip utilizing FPGA for point-to-point
results without the feedrate input. Finally, Section VI motion applications. They implemented trapezoidal and S­
concludes this paper. curve motion planning adopting the digital convolution method
rather than the complex polynomial type method. With this
approach, the computational complexity is signiicantly
II. BACKGROUND
decreased. Furthermore, they developed a real-time output
In this section, the literature laying the basis of the pulse compensation algorithm to eliminate he error in the
proposed technique is presented in three different topics. In the number of output pulses and the results re found to be
irst prt, examples of vrious data compression methods satisfactory.
implemented on PGA are reviewed. In the second prt,
FPGA-based comand generation systems as well as methods Jeon and Kim [12] also used the digital convolution method
re presented. Finally, the CNC applications with variable and designed an FPGA-based acceleration and deceleration
feedrates re investigated. circuit for industrial robots and CNC machine tools. Likewise
the method developed by Su, Hu & Cheng [11], they did not
use the complex polynomial technique to generate velocity
A. FPGA Implementations 0/Data Compression Methods
proiles of various acceleration and deceleration characteristics
Data compression is regrded as the crucial component in that requires much computations. Since the current techniques
high-speed data transfer and storage. Two types of compression are not satisfactory for generating velocity proiles for
exist in the literature: lossless and lossy. In lossless data industrial robots and CNC machine tools [13], they developed
compression, original data is encoded to a smaller data set that a new method to compensate this deiciency. According to the
can later be decoded back to recover the original data. Whereas experimental results given in the paper, they were able to
in lossy compression, the original data can only be generate unsymmerical velocity proiles that cannot be
approximated after decompression. Lossless data compression, generated by digital convolution techniques. Comparing the
where the original data is extracted without any loss after two works, former one is superior over the latter method. The
decompression, applications have increased over the past years error in the output pulses is not compensated in Jeon and Kim
due to the need to improve the storage capacity and data ,
[12] s study, so the errors are inevitable between the comand
ransfer rate [3]. There re many examples for the hrdwre and response signals. On the other hand, the method proposed
implementations of conventional data compression techniques in the paper generates commands without any error.
in the literature. Among these techniques, Huffman [4] [5], Furthermore, it generates position, velocity and acceleration
Lempel-Ziv (LZ) [6] [7], and Golomb [8] compression proiles at the same time.
algorithms are the most populr ones for PGA
implementations. For instance, Rigler, Bishop, and Kennings
. Feedate Control o/CNC Machine Tools
[4] implemented Huffman and LZ encoders on an FPGA and
concluded that modiied Hufman algorithm uses less hrdware The precision of the inal mechanical product is getting
resources than the LZ algorithm. On the other hand, Abd El better as the manufacturing technology improves. In the
Ghany, Salama, and Khalil [6] also realized the LZ encoding manufacturing process, the quality of the product is dependent
and decoding algorithm on FPGA. In order to increase the on the functions of CNC machine. Feedrate conrol of the
eficiency, they used systolic rray which resulted in a 40% machine tool is very important factor for a high-precision CNC
decrease in the compression rate. machine.

Among conventional data compression techniques, There re vrious algorithms proposed on feedrate conrol
hardware implementations of different algorithms for in order to increase the surface quality of the product. For
compressing speciic data structures re also present in the instance Cheng, Tsai, and Maciejowski [14] employed a
literature. For instance, Yongming, Jungang, and Jianmin [9] predictor-corrector algorithm in order to estimate the servo
have realized the Liner Approximation Distance Threshold command at the next sampling time. In another study of Cheng,
algorithm on FPGA to compress the Elecrocrdiograph Tsai, and Cheng [15] developed a new interpolator to produce
signals. Similrly, Valencia and Plaza [10] developed an servo commands for real-time control of CNC machining. The
FPGA-based data compression technique based on the concept main advantage of the proposed intepolator is being capable of
of spectral unmixing to compress hyperspectral data. The novel generating motion commands for servo conrollers at variable
feedrates. In a similar study of Xu, Tam, Zhou, and Tse [16],
they presented variable intepolation schemes for planar given as input to the system and fmax is the maximum feedrate
implicit curves. They were also able to intepolate in real-time at which comands can be generated. Another variable in the
to improve machining eiciency. In the proposed method, the equations is the diference multiplier, a. It accumulates after
feedrate is set by the operator according to geometrical state of each generation according to (2). During the implementation
the surface. In other words, it is decreased when the tool is of this equation, the next original comand should be fed to
machining curved prts and increased on planr surfaces. the interpolator when the interpolated comand is out of the
difference region. In Fig. 3, a sample interpolation is carried
III. PROPOSED MEHOD
out with a feedrate of (0.375)fmaJ. As can be seen rom the
igure that before the 4h interpolated comand is generated,
In this section of the paper, the method suggested for the diference value is updated and the next three comands
comand generation is elaborated. Ater the encoding and are generated according to the new difference value. The
decoding algorithms of the suggested compression method are shaded area underneath the 2nd original command can be
briely explained, the interpolator is elaborated. regarded as the misinterpretation. In future works, it is aimed
to develop new algorithms to decrease the error at original
A. Encoding Algorithm comand points. For instance, it may exrapolate rather than
According to the previous study of authors [1], taking third interpolating at these points.
order differences of the command rajectory before
compressing does increase the compression ratio. In the IV. IMPLEMENTATION
proposed method after the difference of the comand
The implementation of the proposed method is realized on
(position) sequence is calculated according to the speciied
an Altera FPGA DEI Development Board, which contains a
order, data is compressed utilizing the suggested algorithm in
number of memory devices (SRAM, SDRAM, SD Card,
[1]. In Fig. 2, a sample encoding process for the third-order
Flash) ready to be used in conjunction with the FPGA chip
difference is illusrated. In order to use the memory eficiently,
(Cyclone II). Among these chips ISSI IS61LV25616 SRAM is
a compressed code structure is also developed [17].
selected due to its ease of conrol. It is organized as 256K
words by 16 bits. To decrease the complexity of the coding in
B. Decoding Algorithm
VHDL, the schematic design property of Quartus II 9.0 Web
Decoding starts with the comparison of the consecutive Edition is employed. The schematic of comand generator
two bits of the length ield. Ater the binary length of the data shown in Fig. 4 basically consists of 6 diferent modules:
is determined, it is passed to a let shit register. Considering SRAM Controller, Memory Management Unit, Decoding
the length of the data, register forwards the amplitude of the Unit, Accumulators, Interpolator and RS-232 Controller. The
data rom the corresponding ield to the differenced data following sections elaborate the design of these units.
module. After the sign value is obtained from the sign ield,
the data is sent to the accumulator module. Then the initial A. SAM Controller
values re transferred to the integration module in the proper
The main task of the SRAM controller is to maintain the
order and original data is generated rom the buffer.
communication between the Memory Management Unit and
the SRAM located on the FPGA Development Board. It sends
. Interpolator
out the compressed data to the Memory Management Unit
The interpolator used in the method is a linear type. It (one by one) according to the address information emanating
interpolates between the two original command values, from the Memory Management Unit.
decoded rom the compressed code, according to the current
status of the feedrate. It employs the below equations for a B. Memoy Management Unit
proper interpolation.
The Memory Management Unit (MMU) can be regarded
(1) as the core of the design since it comunicates with all
modules except the RS-232 Controller and the interpolator.
Input signals to this module are limited when the number of
(2)

misinterpreted
In the above equations u represents the comands according
to their indices. k and m re the indices of the generated and 1 0
decoded sequences, respectively. fk is the current feedrate i--�"·.-
-. · . '
'
"

0
,
,.
, ,"
{555,983,1354, 1710,2058,2400,2736,
...--
Original Command Sequence �
3068,3394,3715,4031,4341,4646, ... J "00
1
3n 0rder Difference� {42, 7, 2, 0, 2, -2, 1,0, -I, I, .. . J ",0 0 Original
0" 0 Interpolated
Time

m-2 m-J m

Figure 2. Encoding Process of the Proposed Method Figure 3. Interpolated Data

 RS-232 Controller

--- "U_" �15 0) �15 0)

..-
- - __".."" 01 __'" --1.. _"
---__"I" 01 �u_d - --- r;»_!15 0)
- gb_l{'� 0) .Ia_� - -- c

j
� r_a�47. 0) - .....
--"
"' . Decoding Unit

SRAM Controller
Memory
Management
Unit

"'
Interpolator J

Figure 4. Schematic Design of Command Generator with Variable Feedrate

output signals is considered. Input signals are only the data words rom each ield re sent to the DU. This state is only
sent rom the SRAM Controller and acknowledgment signals initiated when the incoing signals 'signdata_need' and
coming from the Decoding Unit (DU) indicating that the unit 'ampdata_need' are set. Note that there is no signal indicating
is out of data. Output signals are the necessity for a data point from the length ield. When a
word rom the amplitude ield is needed, the corresponding
• the initial values sent to the accumulators, word from the length ield is sent automatically to the DU.
• header data for the compressed ile, This state lasts until all the commands are generated.

• three ields transferred to the DU. . Decoding Unit

The basic operating principles of the MMU are described in DU is the module where the decoding algorithm is
Fig. 5. As can be seen, there are four states of this unit: i) get implemented. It communicates with the MMU and the irst
header, ii) get initial conditions, iii) fetch irst set, iv) send & accumulator module. All the input signals to this unit are fed
wait. After the system is reset, the unit starts acquiring header rom the MMD. Two of the output signals ('signdata_need'
data (words) rom the SRAM and sending them to the DU. In and 'ampdata_need') are the acknowledgment signals which
the next state, the initial values are conveyed to the are described in the previous sub-section. The remaining two
accumulators in a proper order. In the following state, the irst output signals are directly connected to the first accumulator.
set of words are fetched rom the SRAM and re sent to the Thus, the decoded command is transferred to the accumulator
DU to initiate the decoding process promptly. In last state, the in signed integer format at an additional clock indicating that a
new command is being subitted. The basic operating
principles of the DU are depicted in Fig. 6. Decoding that
constitutes nine states starts when the header data rom the
MMU are acquired. Then, the header data (constituting the
order of difference, length of the command sequence, and the
number of amplitude ield words) are divided and stored for
further use. In the second state, the irst set of words rom
three different ields is saved. Second set received rom the
MMU is stored in the third and fourth states. While decoding,
the second set is necessary since it may turn out that the
corresponding comand is distributed between two
consecutive words. The main task of this unit is executed in
the 'Decode' state of which is associated with five other states.
When there is a lack of data during decoding, the inite-state
"decoding" machine moves either on to 'Fetch Amplitude' or
Figure 5. State Diagram of Memory Management Unit
'Fetch Sign' states to obtain the required data. If the decoding
 F. RS-232 Controller

The RS-232 Controller is implemented in the design for

monitoring purposes. Instead of the RS-232 Controller, the
output of the architecture may be connected to any other serial
data transfer controller (RS-485, TCP/lP, CAN, etc.). Since
the controller is designed to transfer bytes, a splitter module is
implemented ater the output of the last accumulator (of 16
bits).

V. RESULTS AND COMPARISON

In the previous study [1], the proposed compression

algorithm is rigorously tested in MATLAB environment. Its
performance is compared to those of two other
(popular) compression methods: Huffman and Arithmetic
Coding. The proposed compression algorithm is superior to
the above-mentioned (lossless) compression algorithms in
terms of compression ratios within the given context.
The proposed command generation method with variable
feedrate is evaluated in MATLAB before implementing it on
an FPGA development board. The feedrate proile given in
Figure 6. State Diagram of Decoding Unit Fig. 7 is applied on the original command trajectory illustrated
in Fig. 8 with straight line. There occur comand
is complete for a given command, the data (in unsigned
representation errors (Fig. 9) at each original data points since
integer format) are processed in the 'Pre-Output' state. In case
the interpolation algorithm, described in the previous sub­
the corresponding comand is stored in two diferent words,
section, is not capable of generating commands at these points.
'Detect Pair' state takes over for proper decomposition. The
In further study, it is planned to develop algorithms to
conversion of unsigned to signed integer format is performed
eliinate or decrease these type errors in the trajectory. When
in the 'Output' state. For this purpose, the data rom the sign
Fig. 8 and Fig. 9 are considered together, it can easily be
ield must be ready. When sign data run out, the DU moves
inferred that lrger errors occur at the inlection points of the
onto the third state and gets the necessary data. Ater the
trajectory.
decoded command is formed as signed integer, it is sent to the
irst accumulator instance. The proposed comand generation method described in
the previous sections is then applied to the command
D. Accumulators sequences generated for all six joints of a PUMA 560
Accumulator (integrator) modules are the simplest manipulator. The optical position encoders used in this study
elements of this design. It gets the input data, sums it with the can generate 40000 pulses/rev ( 4 X 10000 pulse/rev) in 4X
=

previous value of the accumulator and outputs the resulting quadrature decoding mode. Decompressor algorithm of the
value to the next accumulator. The number of accumulators in proposed method is realized utilizing Altera Cyclone II FPGA
the design depends on the order of difference. Note that the DEI Development Board. Table I shows the obtained results
given design in Fig. 4 is hard-wired and can decompress data in terms of allocated resources for three different cases. In the
differentiated up to the third order. However, the general irst two approaches decoding algorithm is realized as a inite
design should have 15 accumulator instances (in compliance state machine utilizing VHDL. In the last case, a sot-core
with the format speciied in Section 3.1). A demultiplexer unit processor embedded into the FPGA chip is used. When
must be incorporated to the design to deselect the unused compared to the irst two cases, the one with the soft-core
accumulator instances. Notice that in the proposed design, the processor uses much more resources than the others. As can be
three accumulators yield the acceleration, velocity, and understood rom the table that the main difference between the
position proiles of the commanded trajectory. This attribute two cases is that the one with the interpolator uses 2 embedded
is one of the advantages of the proposed method. Since when a multipliers in order to perform interpolation. This
state-space controller is embedded into the system, the computational effort also results in an increase in the number
velocity and acceleration proiles must be ready for use. of total logic elements.

TBLE I. PGA RESOURCES USED

E. Interpolator
With Without Sot-core
The interpolator in the schematic design simply performs Resources
Interpolator Interpolator Approach
the computations described with (1) and (2). While generating Total Logic
the comands, it sends 'pause' signals to the DU, MMU, and 1728(8%) 1105(6%) 3095(17%)
Elements
accumulators to stop their operations. When there is need for a Total Combinatorial
1482(8%) 825(4%) 2722(15%)
new original comand, it sets the 'pause' signal to low. In Functions
order to overcome the delays between the generated Dedicated Logic
910(5%) 577(3%) 1687(9%)
comands, it also employs a buffer inside. Registers
Embedded Multipliers 2(4%) 0 0
 140--
,
-
compression method suggested is not a universal technique.
The method takes advantage of the fact that the command
sequences in motion control are composed of integers.
The implementation results showed that the addition of an
interpolator to the hardware design resulted in an increase in
the use of FPGA resources due to the computational efort. In
further studies, the proposed command generation method will
be modiied to generate in the reverse direction also. With this
1000 improvement in manufacturing processes the quality will
further be enhanced.
Figure 7. Feedrate Proile
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