Cascode Amplifier

Figure 1(a) shows a cascode amplifier with ideal current source load. Figure 1(b) shows the ideal
current source is implemented by PMOS with constant gate to source voltage.
Vo
V
DD
M1
(a)
V
G2
V
i
M2
V
G3
V
DD
Vo
Vi
M1
M3
(b)
V
G2
M2
V
TN0
+V=
V
DD
-(|V
TP0
|+|V|)=
V
TN0
+V
TN2
+2V=
|V
TP0
|+|V|
V
TN2
+V
V
TN0
+V
(3)
(2)
(7)
(6)
(1)
(5)
(4) V
SS
=0
V
TN0
+V
V
V



Figure 1. Cascode amplifier with simple current load.
1. Low Frequency Small Signal Equivalent Circuit
Figure 2(a) and 2(b) show its low frequency small signal equivalent circuit. Figure 2( c) shows its
two-port representation and port variables assignment.














1
G1
D1
S1
S2 D2
V
o
+
V
i
-
-
g
ds1
g
ds2
g
ds3
+
g
m1
v
gs1
g
m2
v
gs2
g
mb2
v
bs2
+
-
V
S2
v
gs2
=-V
S2
; v
bs2
=-V
S2
G1
D1
S1
S2 D2
V
o
+
V
i
-
-
g
ds1
g
ds2
g
ds3
+
g
m1
v
gs1
g
m2
V
S2
g
mb2
V
S2
+
-
V
S2
v
gs2
=-V
S2
; v
bs2
=-V
S2
Z
i
b Z
o
b
G
L
Y
a
Y
b
V
i
+
+
V
1
a
V
2
a
= V
1
b
I
1
a
I
2
b
I
2
a
I
1
b
Z
o
a




Figure 2. Cascode amplifier low frequency small signal equivalent circuit.



2
) 0 or Z ( Y Y ); r or Z ( g Y Y
S
a
S S ds3
b
L ds3
b
L L
= = = = = =


The current equation of network a is:

a
2 ds1
a
1 m1
a
2
a
1
V g V g I
0 I
+ =
=

The corresponding Y-parameter matrix is:

(

=
ds1 m1
a
g g
0 0
Y

The current equation of network b is:

b
2 ds2
b
1 ds2 mb2 m2
b
2
b
2 ds2
b
1 ds2 mb2 m2
b
1
V g )V g g g ( I
V g - )V g g g ( I
+ + + =
+ + =
The corresponding Y-parameter matrix is:

(

+ +
+ +
=
ds2 ds2 mb2 m2
ds2 ds2 mb2 m2 b
g ) g g g (
g g g g
Y


The common gate stage gain is:


ds3 ds2
ds2 mb2 m2
b
L
b
22
b
21 b
V
g g
g g g
Y y
y
A
+
+ +
=
+

=
The input impedance of common gate stage (the load of common source stage) is:


m2 ds3 ds2 mb2 m2
ds3 ds2
b
L
b
11
b
b
L
b
22 a
L
b
i
g
2
g ) g g g (
g g
Y y detY
Y y
Z Z
+ +
+
=
+
+
= =

The gain of the common source stage is:

2
g g
2g -
g ) g g ( g g g g g g
) g g ( g

g ) g g g ( ) g (g g
) g g ( g
g g
g ) g g g (
g
g
Y y
y
A
mb2 m2
m1
ds3 mb2 m2 ds3 ds2 ds3 ds1 ds2 ds1
ds3 ds2 m1
ds3 ds2 mb2 m2 ds3 ds2 ds1
ds3 ds2 m1
ds3 ds2
ds3 ds2 mb2 m2
ds1
m1
a
L
a
22
a
21 a
V

+ + + +
+
=
+ + + +
+
=
+
+ +
+

=
+

=

Assuming all g
m
are equal, and all g
ds
are equal. In addition g
m
>>g
mb
, and g
m
>>g
ds
.

With a gain of 2 the miller capacitance C
gd1
of the common source stage is negligible.
3

The overall gain is:

ds
m
ds3 ds2 mb2 m2 ds3 ds1 ds2 ds1
ds2 mb2 m2 m1
ds3 mb2 m2 ds3 ds2 ds3 ds1 ds2 ds1
ds3 ds2 m1
ds3 ds2
ds2 mb2 m2 a
V
b
V V
g
g
g ) g g g ( g g g g
) g g g ( g -

g ) g g ( g g g g g g
) g g ( g
g g
g g g
A A A

+ + + +
+ +
=
|
|
.
|

\
|
+ + + +
+
|
|
.
|

\
|
+
+ +
= =

The output impedance of the cascode amplifier is computed by obtaining the output impedance of the
common source stage ( or the source impedance of the common gate stage) first. That is,

ds1
a
22
a
S
a
22
a
a
S
a
11 b
S
a
o
g
1
y
1
Y y detY
Y y
Z Z = =
+
+
= =
The result is obtained by dividing the numerator and denominator by Y
S
a
. The output impedance of the
cascode is the output impedance of the common gate stage.

ds1 ds2 m2 ds2 ds1 ds1 ds2 mb2 m2
ds1 ds2
ds1 ds2 mb2 m2
b
S
b
22
b
b
S
b
11 b
o
r r g r r r r ) g g (
g g
g g g g
Y y detY
Y y
Z + + + =
+ + +
=
+
+
=

That is, the output impedance is equal to the output impedance, r
ds1
, of the first stage (common source)
magnified by the gain, g
m2
r
ds2
, of the second stage (common gate ). The effective load is the parallel
combination of output impedance of the cascode amplifier and the load.

ds3 ds3 ds1 ds2 m2 ds3 ds2 ds1 ds1 ds2 mb2 m2 L
b
o o
r )//r r r g ( r // ) r r r r ) g g (( Z // Z Z + + + = =

The overall gain is approximately equal to :

ds3 m1 o m1 V
r g Z g A =

Although the output impedance has been magnified but the effective load impedance is determined by
smaller impedance. That is, r
ds3
.

The overall gain of the cascode amplifier can be increased if we can increased r
ds3
. This can be achieved by
adding a cascode at the load. This is shown in Figure 3. Figure 4 shows its low frequency small signal
equivalent circuit and its two-port representations and port variables assignment. There are three two-port
networks. The Y-parameter matrices are derived as follows:

The current equation of network a is:



a
2 ds1
a
1 m1
a
2
a
1
V g V g I
0 I
+ =
=

The corresponding Y-parameter matrix is:

4
(

=
ds1 m1
a
g g
0 0
Y

The current equation of network b is:

b
2 ds2
b
1 ds2 mb2 m2
b
2
b
2 ds2
b
1 ds2 mb2 m2
b
1
V g )V g g g ( I
V g - )V g g g ( I
+ + + =
+ + =

The corresponding Y-parameter matrix is:

(

+ +
+ +
=
ds2 ds2 mb2 m2
ds2 ds2 mb2 m2 b
g ) g g g (
g g g g
Y

The current equation of network c is:

c
2 ds3
c
1 ds3 mb3 m3
c
2
c
2 ds3
c
1 ds3 mb3 m3
c
1
V g )V g g g ( I
V g - )V g g g ( I
+ + + =
+ + =

The corresponding Y-parameter matrix is:

(

+ +
+ +
=
ds3 ds3 mb3 m3
ds3 ds3 mb3 m3 c
g ) g g g (
g g g g
Y


The output impedance of network b has been obtained earlier it is,

ds1 ds2 m2 ds2 ds1 ds1 ds2 mb2 m2
b
o
r r g r r r r ) g g ( Z + + + =

The output impedance of network c is computed as follows:

ds4 ds3 m3 ds4 ds3 ds4 ds3 mb3 m3
ds4 ds3
ds4 ds3 mb3 m3
c
S
c
22
c
c
S
c
11 c
o
r r g r r r r ) g g (
g g
g g g g
Y y detY
Y y
Z + + + =
+ + +
=
+
+
=


The effective load impedance is the parallel compbination of the output impedance of network b and c.
2
r g
//Z Z Z
2
ds m c
o
b
o o
=
Assuming all g
m
are equal and all g
ds
are equal.









5
Vo
V
DD
M1
(a)
V
G2
V
i
M2
V
G4
V
DD
M3
Vo
Vi
M1
(b)
V
G2
M2
M4
V
G3
V
DD
- (|V
TP0
|+|V|)=
VDD-(|V
TP0
|+|V
TP3
|+2|V|)=
V
TN0
+V
TN2
+2V=
V
TN0
+V=
(|V
TP0
|+|V|)
(|V
TP3
|+|V|)
V
TN2
+V
V
TN0
+V
(7)
(5)
(1)
(2)
(4) V
SS
=0
(8)
(9)
(3)
(6)
V
DD
V
SS
V
SS


Figure 3. Cascode amplifier with cascode current load.













6
G1
D1
S1
S2 D2
V
o
-
+
+
V
i
-
g
ds1
g
ds2
g
ds3
g
m1
v
gs1
g
m2
V
S2
g
mb2
V
S2
+
-
V
S2
v
gs2
=-V
S2
; v
bs2
=-V
S2
g
ds4
g
m3
V
S3
g
mb3
V3
+
V
S3
-
Y
d
Y
c
Y
a
Y
b
D3
S3
D4
S4
Z
o
b
Y
a
Y
b
V
i
+
V
1
a
V
2
a
= V
1
b
I
1
a
I
2
b
I
2
a
I
1
b
Z
o
c
Z
o
+
V
o
-
Y
c
+
g
ds4




Figure 4. Cascode amplifier with cascode load low frequency small signal equivalent circuit.

7
2. High Frequency Small Signal Equivalent Circuit






V
DD
Vo
C
L
Vi
M2
M1
C
gd1
C
gs2
C
db1
C
sb2
C
db2
C
gd2
V
G1
V
G2
C
db3 C
gd3
M3
C
gs1


Figure 5. Cascode amplifier parasitic capacitances.

Figure 5 shows all the parasitic capacitances needed for high frequency modelling. Figure 6(a)
shows the high frequency small signal equivalent circuit of cascode amplifier with simple current load.
Figure 6(b) its two-port representation and port variables assignment.


C C C C C C ; C C C C ; C C
) 0 or Z ( Y ; C g Y Y
L gd3 db3 db2 gd2 3 sb2 gs2 db1 2 gd1 1
S S 3 ds3
b
L L
+ + + + = + + = =
= = + = = s

The input capacitance C
gs1
is assummed to be part of the input voltage source. C
gs1
is shorted out by the
input voltage source, it does not affect the circuit operation, hence can be ignored or deleted.. C
3
is
assummed to be part of the load. The current of the first stage (network a) is given by:
a
2 2 1 ds1
a
1 1 m1
a
2
a
2 1
a
1 1
a
1
)]V C (C g [ )V C - g ( I
V C V C I
+ + + =
=
s s
s s



8











S1
G1
D1 S2 D2
V
o
+
-
-
g
ds1
g
ds2
g
ds3
+
g
m1
v
gs1
g
m2
V
S2
g
mb2
V
S2
+
-
V
S2
v
gs2
=-V
S2
; v
bs2
=-V
S2
Z
i
b
Z
o
b
G
L
Y
a
Y
b
V
i
+
+
V
1
a
V
2
a
= V
1
b
I
1
a
I
2
b
I
2
a
I
1
b
C
1
C
gs1
C
2 C
3
C
2
=C
db1
+C
gs2
+C
sb2
C
3
=C
gd2
+C
db2
+C
db3
+C
gd3
+C
L
C
1
=C
gd1
V
i


Figure 6. Cascode amplifier high frequency equivalent circuit.


The corresponding Y-parameter matrix is:


(

+ +

=
)] C (C g [ C - g
C C
Y
2 1 ds1 1 m1
1 1 a
s s
s s

The current equation of network b is:

9
a
2 ds2
a
1 ds2 mb2 m2
b
2
a
2 ds2
a
1 ds2 mb2 m2
b
1
V g )V g g g ( I
V g - )V g g g ( I
+ + + =
+ + =

The corresponding Y-parameter matrix is :

(

+ +
+ +
=
ds2 ds2 mb2 m2
ds2 ds2 mb2 m2 b
g ) g g g (
g - g g g
Y

The voltage gain of network b is:

3 ds3 ds2
ds2 mb2 m2
b
L
b
22
b
21 b
V
C g g
g g g
Y y
y
A
s + +
+ +
=
+

=

The input impedance of network b or load of network a is:

) C )(g g g (g
C g g
Y y detY
Y y
Z Z
3 ds3 ds2 mb2 m2
3 ds3 ds2
b
L
b
11
b
b
L
b
22 a
L
b
i
s
s
+ + +
+ +
=
+
+
= =
The voltage gain of network a is:

) C )(g g g (g ) sC g g )( ) C s(C g (
) sC g )(g sC - (g -

sC g g
) C )(g g g (g
) C s(C g
) sC - (g -
Y y
y -
A
3 ds3 ds2 mb2 m2 3 ds3 ds2 2 1 ds1
3 ds3 ds2 1 m1
3 ds3 ds2
3 ds3 ds2 mb2 m2
2 1 ds1
1 m1
a
L
a
22
a
21 a
V
s
s
+ + + + + + + +
+ +
=
+ +
+ + +
+ + +
=
+
=

The overall gain of the cascode amplifier is:

10
) g g g (g g g g c
) g g g (g g g g
) g (g C ) g (g C ) g g g (g C
b
) g g g (g g g g
) C (C C
a
: where
] a b c[1
) g g )(g sC - (g -
) C )(g g g (g ) sC g g )( ) C s(C g (
) g g )(g sC - (g -
) C )(g g g (g ) sC g g )( ) C s(C g (
) sC g )(g sC - (g -
C g g
g g g
A A A
ds2 ds1 mb2 m2 ds3 ds2 ds1
ds2 ds1 mb2 m2 ds3 ds2 ds1
ds3 ds2 1 ds3 ds2 2 mb2 m2 ds2 ds1 3
ds2 ds1 mb2 m2 ds3 ds2 ds1
2 1 3
2
ds2 mb2 m2 1 m1
3 ds3 ds2 mb2 m2 3 ds3 ds2 2 1 ds1
ds2 mb2 m2 1 m1
3 ds3 ds2 mb2 m2 3 ds3 ds2 2 1 ds1
3 ds3 ds2 1 m1
3 ds3 ds2
ds2 mb2 m2
a
V
b
V V
+ + + + =
+ + + +
+ + + + + + +
=
+ + + +
+
=
+ +
+ +
=
+ + + + + + + +
+ +
=
|
|
.
|

\
|
+ + + + + + + +
+ +
|
|
.
|

\
|
+ +
+ +
=
=
s s
s
s
s



If the poles are far apart, it can be approximated as follows:



| p | | p | : where
p p
1
p
1
1
p p
1
p
1
p
1
1
p
1
p
1 a b 1 ) D(
1 2
2
2 1 1
2
2 1 2 1 2 1
2
>>
|
|
.
|

\
|
+
|
|
.
|

\
|

|
|
.
|

\
|
+
|
|
.
|

\
|
+ =
|
|
.
|

\
|

|
|
.
|

\
|
= + + = s s s s
s s
s s s
That is,

2 1
m2
2 1 3
ds3 ds2 1 ds3 ds2 2 mb2 m2 ds2 ds1 3
2
3
ds3
ds3 ds2 1 ds3 ds2 2 mb2 m2 ds2 ds1 3
ds2 ds1 mb2 m2 ds3 ds2 ds1
1
C C
g
) C (C C
] ) g (g C ) g (g C ) g g g (g C [
a
b
p
C
g
) g (g C ) g (g C ) g g g (g C
)] g g g (g g g [g -
b
1
p
+

+
+ + + + + + +
=

+ + + + + + +
+ + + +
=

=

Note that the poles are associated with the inverse product of the resistance and capacitance of a node to
ground. p
1
is associated with node D2 to ground, and p
2
is associated with D1 (or S2) to ground. The
cascode amplifier also has a zero at the right half plane given by:

1
m1
1
C
g
z =




11




Cascode Amplifier Experiments
3. Cascode Amplifier with Simple Current Load

The biasing voltages will be determined by ignoring the effect of the bulk voltage on M2. Using
the biasing principle discussed in the current sink/source section. The biasing requirement from Figure 1(b)
are:

5 . 2 V |) 5 . 1 | | 1 (| V |) V | | V (| V V
5 2(1.5) 2(1) V 2 V 2 V
2.5 1.5 1 V V V
DD DD TP0 DD G3
TN G2
TN0 bias
= + = + =
= + = + =
= + = + =

The output voltage dynamic range with the above biasing is:

5 . 7 V If ; 6 V 4
5 . 1 V V 4 2(1.5) 1
V V V V 2 V
DD O
DD O
DD O TN
=
= +
+
5 2.5 7.5 2.5 - V V
DD G3
= = =

The effect of bulk bias on M2 on the output voltage will be considered next. The actual minimum output
voltage will be determined. The threshold voltage of M2 is no longer equal to V
T0
, due to the present of the
bulk bias.

6 V 325 . 3
25 . 3 5 . 1 75 . 1 V V V
1.5 V V
1.75 1.5 - 1.75 - 5 V V V V
75 . 1 V
iteration by V for Sove
) V V V ( V V
V V V V
) V ( V ) V ( V V
V V
O
DS2(min) DS1(min) O(min)
DS2(min)
TN2 G2 DS1(min)
TN2
TN2
TN2 G2 T0 TN2
TN2 G2 DS1
DS1 TN0 BS2 TN0 TN2
DS1 BS2

= + = + =
= =
= = =
=
+ + =
=
+ + = + =
=




The bulk bias increases the output voltage dynamic range. Using the above biasing voltages, Pspice
simulation is conducted to obtain the DC transfer characteristic curve. The Pspice netlist below is used to
obtain the DC transfer characteristic.

12
*PSpice file for NMOS Common Gate Amplifier with
*PMOS Current Load
*Filename="Lab3.cir"
VIN 1 0 DC 2.5212VOLT AC 1V
VDD 3 0 DC 7.5VOLT
VSS 4 0 DC 0VOLT
VG2 6 0 DC 5VOLT
VG3 7 0 DC 5VOLT
M1 5 1 4 4 MN W=9.6U L=5.4U
M2 2 6 5 4 MN W=9.6U L=5.4U
M3 2 7 3 3 MP W=25.8U L=5.4U

.MODEL MN NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL MP PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
*Analysis
.DC VIN 0 7.5 0.05
.TF V(2) VIN
.AC DEC 100 1HZ 10GHZ
.PROBE
.END



The exact V
bias
is determined by locating a point in the DC transfer characteristic curve with the highest
slope. The AC small signal characteristic and operating node voltages are then obtained at this operating
point. The Pspice node voltages at the operating point is given below:

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE


( 1) 2.5212 ( 2) 4.6987 ( 3) 7.5000 ( 4) 0.0000

( 5) 1.7410 ( 6) 5.0000 ( 7) 5.0000

The voltage at node 5 is 1.7410 which is reasonably closed to the calculated value of V
DS1(min)
=1.75. If we
ignore the bulk bias of M2 the calculated value is :

2.5 1.5 1 V V V
TN0 DS1(min)
= + = + =


The DC transfer characteristic curve is given below:


13

Theoretical calculations of the small signal parameters are given below:

36.355db or 65.75 6)(.495E6) - E 79 . 132 ( R g A
mho 79 . 132 6) - 6)(101E - E 3 . 87 ( 2 I 2 g g
M 495 .
6) - E 101 )( 02 (.
1
I
1
r R
A 101 1) - 0 - 2 6/2)(2.521 - E 3 . 87 ( ) V - V - V )( 2 / ( I
87.3uA/V 4u) 6)(9.6u/4. - E 40 ( (W/L) K
out m1 V0
DSQ N1 m2 m1
DSQ
ds3 out
2 2
T0 SS bias N1 DSQ
2
1 N N1
= = =
= = = =
= = = =
= = =
= = =
u
u

The Pspice results are:

36.644db or 95 . 67 A
M 5 . R
V0
out
=
=













**** SMALL-SIGNAL CHARACTERISTICS
14


V(2)/VIN = -6.795E+01

INPUT RESISTANCE AT VIN = 1.000E+20

OUTPUT RESISTANCE AT V(2) = 5.000E+05

4. Cascode Amplifier High Frequency Model Experiments

The parasitic capacitances will be determined to check the theory against Pspice simulation
results. The capacitances are determined at the operating point. The reverse bulk bias are first calculated at
the quiescent operating point.

For M1
VBD=V(4)-V(5)=0-1.7410=-1.7410
VBS=0, bulk connected to source
For M2
VBD=V(4)-V(2)=0-4.6987=-4.6967
VBS=V(4)-V(5)=0-1.7410=-1.7410
For M3
VBD=-(V(3)-V(2))=-(7.5-4.6987)=-2.8013

The MATLAB program is invoked to obtain the parasitic capacitances.
For M1,

[CGS,CGD,CBD,CBS]=cap(9.6,5.4,-1.7410,0)
CGS=23.2704fF, CGD=3.84fF, CGD=24.1791fF, CBS=61.84fF

For M2,

[CGS,CGD,CBD,CBS]=cap(9.6,5.4,-4.6987,-1.7410)
CGS=23.2704fF, CGD=3.84fF, CGD=16.0715fF, CBS=38.2591fF

For M3,

[CGS,CGD,CBD,CBS]=cap(25.8,5.4,-2.8013,0)
CGS=62.5392fF, CGD=10.32fF, CGD=47.956fF, CBS=152.02Ff


In the simulation without specifying the area and perimeter of source and drain, only Cgs and Cgd are
accounted in computing the parasitic capacitances. These are calculatedbelow:

C1=Cgd1=3.84fF
C2=Cgs2=23.2704fF
C3=Cgd2+Cgd3+CL=3.84fF+10.32fF+0=14.16fF








15
19 . 12 43 . 62 38 . 15 90
4.898E9
E9 38 . 9
tan -
34.1E9
9.38E9
tan - 90
p
w
tan -
z
w
tan - 90 PM
G 43 . 5
2
E9 1 . 34
2
z
f
E9 1 . 34
15 - E 84 . 3
6 - E 79 . 132
C
g
z
G 7799 .
2
E9 898 . 4
2
p
f
E9 898 . 4
15 - E ) 2704 . 23 84 . 3 (
6 - E 79 . 132
C C
g
p
G 493 . 1
2
E9 38 . 9
2
w
f
9.38E9 E6) 67 . 142 )( 75 . 65 ( w A w
M 7 . 22
2
E6 67 . 142
2
w
f
E6 67 . 142
15) - E6)(14.16E 495 . 0 (
1
C r
1
p w
1 - 1 -
2
GBW 1 - GBW 1 -
z
1
m1
2
p2
2 1
m2
2
GBW
GBW
BW V0 GBW
BW
BW
3 ds3
1 BW
= = |
.
|

\
|
|
.
|

\
|
=
|
|
.
|

\
|
|
.
|

\
|
=
= = =
= = =
= = =
=
+

=
+

=
= = =
= = =
= = =
= = = =






In the Pspice simulation, if the PM is determined at the frequency
where zero db gain occurs the result is:


33.84 PM
@0db G 1 f
GBW
=
=


This result seem to be quite different from the theoretical result of


12.19 PM
G 493 . 1 f
GBW
=
=
The discrepancy occurs because the non-dominant pole p
2
=4.898E9 occurs
before the gain bandwith product w
GBW
=9.38E9. The gain bandwidth
calculation assume that the slope of 20db/dec is maintain before
intersecting the zero db line. With p
2
occuring before w
GBW
means that
the slope becomes 40db/dec, causing it to intersect the zero db gain
line sooner. If one extend the 20db/dec line in the Pspice simulation,
this line will intersect the zero db gain axis at:

1.53G M) 496 . 22 )( 95 . 67 ( f A f
BW V0 GBW
= = =

If the phase margin is determined at 1.53G, the result is 16.744 which
is closer to the theretical calculation of 12.19. That is, the
16
theretical calculation will be in error if the non-dominant pole p
2

occurs before w
GBW
.


















17



The PM of 33.84 is rather low. For stability a PM of at least 60 is
desirable. Looking at the PM calculation, one can increase the PM by
decreasing w
GBW
. Increasing the value of capacitor C
3
will decrease w
GBW

while maintaining the value of p
2
. C
3
is a function of the load
capacitance C
L
. One can compute the value of C
L
needed to achieve the
desired PM. To illustrate this we will compute the value of C
L
for a
PM=80.

First compute w
GBW
to achieve PM=80.

G 75 . 0 w
10
4.898E9
w
tan
34.1E9
w
tan
10
p
w
tan
z
w
tan
80
p
w
tan -
z
w
tan - 90 PM
GBW
GBW 1 - GBW 1 -
2
GBW 1 - GBW 1 -
2
GBW 1 - GBW 1 -
=
= |
.
|

\
|
+ |
.
|

\
|
=
|
|
.
|

\
|
+ |
.
|

\
|
=
|
|
.
|

\
|
|
.
|

\
|
=

The value of load capacitance is then calculated to achieve w
GBW
.

18
168.87fF 14.16fF - 183.03fF 14.16fF -
.75E9) (.495E6)(0
67.95
fF 16 . 14
w r
A
C
C fF 16 . 14
w r
A
C
C r
1
A w
GBW ds3
V0
L
L
GBW ds3
V0
3
3 ds3
V0 GBW
= = = =
+ = =
|
|
.
|

\
|
=

The result of Pspice simulation with C
L
added shows that PM is now
82.195.





Filename=cascexp3.doc

5. Cascode Amplifier With Cascode Current Load Experiments

The derivation of the biasing circuit is shown in Figure 7. The
complete circuit is shown in Figure 8.
19

MBP2
MBP1
(3) VDD
(4) VSS
(9)
(8)
IBP=101UA
MBN2
MBN1
(7)
(10)
+
Vin
(1)
IBN=101UA
MBP2
MBP1
(9)
(8)
(3) VDD
(4) VSS
IBP=101UA
MBN2
MBN1
(7)
(10)
+
Vin
(1)
(9)
(8)
(a) (b)
(c)




Figure 7. Biasing circuit for the cascode amplifier with cascode load.










20
MBP2
MBP1
(9)
(8)
(3) VDD=10
(4) VSS=0
MBN2
MBN1
(7)
(10)
+
Vin
(1)
(9)
(8)
MBP4
MBP3
M4
M3
M2
M1
(2)
(6)
(5)
Vo
IBP





Figure 8. Complete circuit of the cascode amplifier with cascode load.


Netlist for the complete circuit of Figure 8 is shown below:

*PSpice file for NMOS Common Gate Amplifier with
*PMOS Current Load
*Filename="Lab32b.cir"
*All bulks are connected to supply rail
.PARAM Wn=9.6U, Ln=5.4U
.PARAM Wp=25.8U, Lp=5.4U
VIN 1 10 DC 0VOLT AC 1V
VDD 3 0 DC 10VOLT
VSS 4 0 DC 0VOLT

M1 5 1 4 4 NMOS1 W={Wn} L={Ln}
M2 2 7 5 4 NMOS1 W={Wn} L={Ln}
M3 2 8 6 3 PMOS1 W={Wp} L={Lp}
M4 6 9 3 3 PMOS1 W={Wp} L={Lp}

*Biasing circuit
MBN1 10 10 4 4 NMOS1 W={Wn} L={Ln}
MBN2 7 7 10 4 NMOS1 W={Wn} L={Ln}
IBP 8 4 100UA
MBP1 8 8 9 3 PMOS1 W={Wp} L={Lp}
MBP2 9 9 3 3 PMOS1 W={Wp} L={Lp}
MBP3 7 8 11 3 PMOS1 W={Wp} L={Lp}
MBP4 11 9 3 3 PMOS1 W={Wp} L={Lp}
21

.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9

*Analysis
.DC VIN -2.5 7.5 0.05
.TF V(2) VIN
.AC DEC 100 1HZ 10GHZ
.PROBE
.END

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE


( 1) 2.4774 ( 2) 5.9211 ( 3) 10.0000 ( 4) 0.0000

( 5) 2.4774 ( 6) 7.5450 ( 7) 5.9211 ( 8) 4.4772

( 9) 7.5280 ( 10) 2.4774 ( 11) 7.5450
The biasing voltages are obtained from the above table

VG1=Vbias=V(10)=2.4774
VG2=V(7)=5.9211
VG3=V(8)=4.4772
VG4=V(9)=7.5280


The low frequency small signal parameters are:












mho 13 . 132 6) - 6)(100E - E 3 . 87 ( 2 I 2 g g
M 5 .
6) - E 100 )( 02 (.
1
I
1
r r
I uA 100 I
87.3uA/V 4u) 6)(9.6u/4. - E 40 ( (W/L) K
DSQ N1 m2 m1
DSQ
ds2 ds1
BIAS DSQ
2
1 N N1
u = = = =
= = = =
= =
= = =

22
2182.78 ) 6)(16.52E6 - E 13 . 132 ( R g A
M 52 . 16
2
0.5E6) 6)(0.5E6)( - E 13 . 132 (
2
r r g
R
out m1 V0
ds1 ds2 m2
out
= = =
= = =



Pspice simulation results:
**** SMALL-SIGNAL CHARACTERISTICS


V(2)/VIN = -3.136E+03

INPUT RESISTANCE AT VIN = -2.424E+19

OUTPUT RESISTANCE AT V(2) = 2.342E+07







23































6. Cascode Amplifier Design Example

24
Design specification

Given: A
V
>=10,000 Ro>=10Meg
Find: V
DD
, acceptable output voltage swing, and transistor sizing

MBP2
MBP1
(9)
(8)
(3) VDD
(4) VSS=0
MBN2
MBN1
(7)
(10)
+
Vin
(1)
(9)
(8)
MBP4
MBP3
M4
M3
M2
M1
(2)
(6)
(5)
Vo
IBP
(11)
V
TN0
+V
V
TN
+V
|V
TP0
|+,V|
|V
TP
|+,V|
V
DD
-(|V
TP0
|+|V
TP
|+2,V|)
V
TN0
+V
TN
+2V



Design Procedure



umho 1000
M 10
10000
R
A
g
R -g A
O
V
m1
O m1 V
= = =
=
O OP ON
OP ON O
2R R R
//R R R
= =
=


M 141 . 0
10000
2
M) 10 (
A
2
R
A
R 2
g
R 2
r
r r ; 2R r g r r g R
V
O
V
2
O
m1
O
O1
O2 O1 O
2
O1 m1 O1 O2 m2 ON
= = = = =
= = =

25

uA 354
M) 141 . 0 )( 02 . 0 (
1
r
1
I
I
1
r
O1
DSQ
DSQ
O1
= = =
=

3 . 35
6) - 6)(354E - 2(40E
6) - E 1000 (
I 2K
g
W/L) ( W/L) (
I (W/L) K 2 I 2 g
2
DSQ N
2
m1
2 1
DSQ 1 N DSQ N m1
= = = =
= =


708 . 0
6)(35.3) - E 40 (
6) - E 354 ( 2
(W/L) K
2I 2I
V
V) /2)( ( ) V - /2)(V ( I
1 N
DSQ DSQ
2 2
T GS DSQ
= = = =
= =

Output voltage swing neglecting bulk to source effect

e) (acceptabl V 5 . 7 V ; 084 . 5 V 416 . 2
) acceptable (not V 5 V ; 584 . 2 V 416 . 2
416 . 2 V )) 708 (. 2 1 ( V V 416 . 2 ) 708 . 0 ( 2 1
) V 2 V ( V V V 2 V
DD DD
DD DD
DD DD O
T0P DD O T0N
=
=
= + = +
+ +


Designing for equal V or
R
=1

13 . 94 ) 3 . 35 (
5 - 15E
6 - 40E
(W/L)
K
K
W/L) ( W/L) (
1
P
N
3 3
= = = =

L 3
L 282
3
3
13 . 94
L
W
L
W
L
W
L 3
L 9 . 105
3
3
3 . 35
L
W
L
W
L
W
Peff
P
3
3
3
3
Neff
N
2
2
1
1
=
|
.
|

\
|
= = =
=
|
.
|

\
|
= = =


For Lambda L=0.6

U 3 L L
169.2U 282(0.6U) L 282 W
3U 2.8U 2(0.5U) 3(0.6U) 2LD 3L LD 2 L L
63.6U 63.54U ) 105.9(0.6U L 9 . 105 W
N P
P
Neff N
N
= =
= = =
= + = + = + =
= = =




26

*PSpice file for NMOS Common Gate Amplifier with
*PMOS Current Load
*Filename="Lab61.cir"
*All bulks are connected to supply rail
.PARAM Wn=63.6U, Ln=3U
.PARAM Wp=169.2U, Lp=3U
VIN 1 10 DC 0VOLT AC 1V
VDD 3 0 DC 7.5VOLT
VSS 4 0 DC 0VOLT

M1 5 1 4 4 NMOS1 W={Wn} L={Ln}
M2 2 7 5 4 NMOS1 W={Wn} L={Ln}
M3 2 8 6 3 PMOS1 W={Wp} L={Lp}
M4 6 9 3 3 PMOS1 W={Wp} L={Lp}

*Biasing circuit
MBN1 10 10 4 4 NMOS1 W={Wn} L={Ln}
MBN2 7 7 10 4 NMOS1 W={Wn} L={Ln}
IBP 8 4 354UA
MBP1 8 8 9 3 PMOS1 W={Wp} L={Lp}
MBP2 9 9 3 3 PMOS1 W={Wp} L={Lp}
MBP3 7 8 11 3 PMOS1 W={Wp} L={Lp}
MBP4 11 9 3 3 PMOS1 W={Wp} L={Lp}

.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9

*Analysis
.DC VIN -2.5 7.5 0.05
.TF V(2) VIN
.AC DEC 100 1HZ 10GHZ
.PROBE
.END

**** SMALL-SIGNAL CHARACTERISTICS


V(2)/VIN = -1.268E+04

INPUT RESISTANCE AT VIN = -1.318E+19

OUTPUT RESISTANCE AT V(2) = 1.321E+07

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE


( 1) 1.7334 ( 2) 4.2146 ( 3) 7.5000 ( 4) 0.0000

( 5) 1.7334 ( 6) 5.7694 ( 7) 4.2146 ( 8) 3.5826
27

( 9) 5.7657 ( 10) 1.7334 ( 11) 5.7694







The circuit is simulated with VDD=5V to show that the resulting the cascode does not yield the desired
gain and output impedance. Replace the VDD line in the netlist to:
28

VDD 3 0 DC 5VOLT

**** SMALL-SIGNAL CHARACTERISTICS


V(2)/VIN = -1.216E+01

INPUT RESISTANCE AT VIN = 3.651E+18

OUTPUT RESISTANCE AT V(2) = 1.285E+04


NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE


( 1) 1.7233 ( 2) 4.1910 ( 3) 5.0000 ( 4) 0.0000

( 5) 1.7233 ( 6) 4.3287 ( 7) 4.1910 ( 8) 1.0826

( 9) 3.2657 ( 10) 1.7233 ( 11) 4.3287


29