AMERICAN INTERNATIONAL UNIVERSITY-BANGLADESH

Faculty of Engineering
Project Report
Project Title: Prepare a design that realizes the following equation using complimentary
CMOS logic. 𝐹 = (𝐴. 𝐵) + (𝐶. 𝐷)

Date of Perform: 21 January 2025 Date of Submission: 02 February 2025

Course Title: VLSI CIRCUIT DESIGN Laboratory
Course Code: EEE4217 Section: A
Semester: Fall 2024-25 Degree Program: BSc in EEE
Course Teacher: Dr. Shahriyar Masud Rizvi
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* Student(s) must complete all details except the faculty use part.

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FACULTY COMMENTS
 Marks Obtained
Total Marks

Abstract:
This project focuses on designing and implementing a complementary CMOS logic circuit to
realize the Boolean function F = (A · B) + (C · D). The design process involved creating the
schematic, simulating the circuit, and developing the layout to ensure accuracy and efficiency.
Various performance metrics, including transient response, Design Rule Check (DRC), and
Layout Versus Schematic (LVS) verification, were analyzed. The goal was to optimize power
consumption, propagation delay, and circuit area while maintaining functional integrity.
Simulation results validated the design, confirming its correctness and efficiency. This project
demonstrates the significance of CMOS technology in modern digital circuit design,
emphasizing its advantages in power efficiency and reliability.
Introduction:
CMOS (Complementary Metal-Oxide-Semiconductor) technology is widely used in VLSI (Very
Large-Scale Integration) circuit design due to its low power consumption, high noise immunity,
and scalability. This project aims to design a CMOS logic circuit to implement the Boolean
function F = (A · B) + (C · D) while ensuring efficiency and accuracy.
The design process includes schematic development, circuit simulation, and verification through
Design Rule Check (DRC) and Layout Versus Schematic (LVS) analysis. Additionally, key
performance factors such as propagation delay, power dissipation, and circuit area are evaluated
to optimize the design. By analyzing and simulating the circuit, this project highlights the
significance of CMOS logic in digital circuits and its role in modern electronic systems.
Literature Review:
CMOS technology is a key component in VLSI design, known for its efficiency, high speed, and
scalability. Research indicates that complementary CMOS logic is superior to other logic
families due to its low static power consumption. Studies on Boolean function implementation
focus on optimizing transistor placement, power efficiency, and circuit layout. Furthermore,
verification techniques such as Design Rule Check (DRC) and Layout Versus Schematic (LVS)
are essential for ensuring circuit reliability. This project applies these established concepts to
develop an optimized CMOS circuit for the Boolean function F = (A · B) + (C · D).
Methodology:

 The Boolean function F = (A · B) + (C · D) is first converted into a

logic gate representation using AND and OR gates to ensure accurate
implementation.
 Complementary CMOS logic is applied, selecting appropriate PMOS and
NMOS transistors to enhance power efficiency and circuit performance.
 A schematic diagram is developed using circuit design software to
visualize and verify the circuit’s functionality.
  The designed circuit undergoes simulation using tools like SPICE to
analyze transient response, propagation delay, and power dissipation.
 Design Rule Check (DRC) and Layout Versus Schematic (LVS)
verifications are performed to ensure compliance with design
constraints and layout accuracy.
 Finally, the optimized circuit is evaluated based on key metrics such as
power consumption, propagation delay, and area efficiency to ensure it
meets performance requirements.
Circuit Diagram:
Schematic Diagram:

Layout Diagram:
Stick Diagram:

Simulation:
Transient Analysis:
Circuit:
DRC:
LVS:

Simulation Waveform:

Transient Measurement:
Result Analysis:
The designed CMOS circuit for F = (A · B) + (C · D) was successfully implemented and
analyzed through simulation. The transient analysis confirmed correct logical operation, with
output transitions matching expected behavior. Propagation delay and power dissipation were
measured, showing efficient performance within acceptable limits. Design Rule Check (DRC)
and Layout Versus Schematic (LVS) verification ensured accuracy and compliance with design
constraints. Overall, the results validate the circuit’s functionality, demonstrating its reliability
and efficiency in CMOS logic design.

Conclusion:
The objective of this experiment was to learn layout design and verification of logic gates. The
process of designing and verifying the design was learned properly. Furthermore, practice will be
helpful to minimize the errors.
Discussion :
Using the Cadence Virtuoso tool, the schematic of a NAND gate was designed. In the layout
window, the connections were made according to the given instructions. During
verification, the LVS was found to be clean; however, the DRC was not entirely correct due
to some color mismatches in the metal layers.

The objective of the experiment was to understand the process of

layout design and verification of logic gates. The design and
verification processes were learned effectively. Further practice is
recommended to minimize errors and improve accuracy