AJAY KUMAR GARG ENGINEERING COLLEGE, GHAZIABAD

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

LIST OF EXPERIMENTS

COURSE: B.Tech Semester: III SESSION: 2024-25 (ODD SEM)

BRANCH: CSE/CS/AIML/CSE(DS)/CSE(AIML)/CS(Hindi)
SUBJECT & CODE: Computer Organization and Architecture Lab. (BCS-352)

Sr. NAME OF EXPERIMENT

No.
1 Implementing HALF ADDER, FULL ADDER using basic logic gates.

2 Implementing Binary -to -Gray, Gray -to -Binary code conversions.

3 Implementing 3-8 line DECODER

4 Implementing 4x1 and 8x1 MULTIPLEXERS

5 Verify the excitation tables of various FLIP-FLOPS

6 Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.

7 Design of an 8-bit ARITHMETIC LOGIC UNIT.

8 Design the data path of a computer from its register transfer language description

9 Design the control unit of a computer using either hardwiring or microprogramming based on its
register transfer language description.
10 Implement a simple instruction set computer with a control unit and a data path.

11* Design of N-bit Carry Look ahead Adder

12* Design N-bit Counter

* Additional / Innovative Experiments

Subject Faculty Name & Signature Dr Anu Chaudhary

HoD CSE

CSE 2024 CO-LAB

 EXPERIMENT

Objective:-
Design and implementaion of Logic gates with verification of Truth table.

Gates IC NO.

AND 7408

OR 7432

NAND 7400

NOR 7402

NOT 7404

XOR 74136

Theory:-
Logic gates are idealized or physical devices implementing a Boolean function, which it
performs a logical operation on one or more logical inputs and produce a single output.
Depending on the context, the term may refer to an ideal logic gate, one that has for
instance zero rise time and unlimited fan out or it may refer to anon-ideal physical device.

The main hierarchy is as follows:-

1. Basic Gates

2. Universal Gates

3. Advanced Gates

CSE 2024 CO-LAB

Basic Gates
1. AND gate: - Function of AND gate is to give the output true when both the inputs
are true. In all the other remaining cases output becomes false. Following table
justifies the statement:-

Input A Input B Output

1 1 1

1 0 0

0 1 0

0 0 0

IC 7408

2. OR gate: - Function of OR gate is to give output true when one of the either inputs
are true .In the remaining case output becomes false. Following table justify the
statement:-

Input A Input B Output

0 0 0

0 1 1

1 0 1

1 1 1
 IC 7432

3. NOT gate: -Function of NOR gate is to reverse the nature of the input .It
converts true input to false and vice versa. Following table justifies the statement :-

Input Output

1 0

0 1

IC 7404
Universal Gates
1. NAND gate: -Function of NAND gate is to give true output when one of the two
provided input are false. In the remaining output is true case .Following table
justifies the statement :-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 1

IC 7400

2. NOR gate: - NOR gate gives the output true when both the two provided input
are false. In all the other cases output remains false. Following table justifies the
statement :-

Input A Input B Output

1 1 0

1 0 0

0 1 0

0 0 1
 IC 7402

Advanced Gates
1. XOR gate: - The function of XOR gate is to give output true only when both the
inputs are true. Following table explain this:-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 0

IC 74136
Result:-
All gates are verified. Observed output matches theoretical concepts.
Experiment 1: Implementing HALF ADDER and FULL ADDER using basic logic
gates

Objective:
To design and implement Half Adder and Full Adder circuits using basic logic gates, and verify
their functionality.

Theory:

 A Half Adder adds two single bits and outputs the sum and carry.
o Sum = A XOR B
o Carry = A AND B
 A Full Adder adds three bits (two inputs and a carry-in), producing a sum and a carry-out.
o Sum = (A XOR B) XOR Carry-in
o Carry-out = (A AND B) OR (Carry-in AND (A XOR B))

Procedure:

1. Half Adder:
o Open CircuitVerse.
o Add two inputs A and B.
o Use XOR gate for sum and AND gate for carry.
o Simulate and verify the output for all possible combinations of A and B.
2. Full Adder:
o Extend the half adder to a full adder by adding a third input (Carry-in).
o Implement two half adders and an OR gate to produce Carry-out.
o Simulate the circuit.

Code/Simulation:

 Use CircuitVerse to design both adders.

 Simulate and capture the truth tables.

Observation/Analysis:

 Record the sum and carry for each input combination and verify that the circuit works
correctly for both half and full adders.
Experiment 2: Implementing Binary-to-Gray and Gray-to-Binary code
conversions

Objective:
To design and implement Binary-to-Gray and Gray-to-Binary code converters.
Theory:
 Binary-to-Gray conversion: The MSB of Gray code is the same as the MSB of Binary,
and each subsequent bit is XORed with the previous bit.
o G(n)=B(n)G(n) = B(n)G(n)=B(n)
o G(n−1)=B(n)⊕B(n−1)G(n-1) = B(n) \oplus B(n-1)G(n−1)=B(n)⊕B(n−1)
 Gray-to-Binary conversion: The MSB remains the same, and each subsequent bit is
XORed with the previous Gray bit.
o B(n)=G(n)B(n) = G(n)B(n)=G(n)
o B(n−1)=B(n)⊕G(n−1)B(n-1) = B(n) \oplus G(n-1)B(n−1)=B(n)⊕G(n−1)
Procedure:
1. Binary-to-Gray:
o Open CircuitVerse.
o Design the converter using XOR gates.
o Simulate and verify the output.
2. Gray-to-Binary:
o Implement the reverse conversion using XOR gates.
o Simulate and check for correctness.
Code/Simulation:
 Design both converters in CircuitVerse.
 Test with various binary inputs.
Observation/Analysis:
 Compare the output of both converters for correctness.
 Ensure that the Gray code is accurate for each binary input and vice versa.
Experiment 3: Implementing 3-to-8 Line Decoder

Objective:
To implement a 3-to-8 line decoder using logic gates.
Theory:
 A decoder converts binary input to a corresponding active output line.
 A 3-to-8 decoder has 3 inputs and 8 outputs, where each input combination activates one
unique output.
Procedure:
1. Open CircuitVerse and design the decoder.
2. Use 3 inputs and connect them to the AND gates for each output.
3. Verify the output for all input combinations.
Code/Simulation:
 Design the decoder using basic AND gates and NOT gates to handle different input
combinations.
 Simulate the 3-to-8 decoder.
Observation/Analysis:
 Record the active output for all 8 possible combinations of inputs.

Implementing 3-8 line DECODER.

Experiment 4: Implementing 4x1 and 8x1 MULTIPLEXERS

Objective:
To design and implement 4x1 and 8x1 multiplexers.
Theory:
 A multiplexer (MUX) selects one input from several inputs and passes it to the output,
based on select lines.
o A 4x1 MUX has 4 inputs, 2 select lines.
o An 8x1 MUX has 8 inputs, 3 select lines.
Procedure:
1. 4x1 MUX:
o Design the MUX with 4 inputs, 2 select lines, and one output.
o Simulate the circuit and verify output for all input and select line combinations.
2. 8x1 MUX:
o Extend the design for an 8x1 MUX.
o Simulate and verify.
Code/Simulation:
 Use CircuitVerse to design both multiplexers.
 Simulate with various input and select line combinations.
Observation/Analysis:
 Verify the output based on different select line inputs.
2X1 MUX

4X1 MUX

8X1 MUX
Experiment 5: Verify the excitation tables of various FLIP-FLOPS

Objective:
To verify the excitation tables of different flip-flops (SR, JK, D, T).
Theory:
 Flip-flops store one bit of data and change state based on clock input.
o SR Flip-flop: Set/Reset.
o JK Flip-flop: Toggle functionality.
o D Flip-flop: Data latch.
o T Flip-flop: Toggle on each clock pulse.
Procedure:
1. Design each flip-flop (SR, JK, D, T) in CircuitVerse.
2. Simulate their behavior based on input and clock signals.
3. Verify the output against the excitation table for each flip-flop.
Observation/Analysis:
 Observe how each flip-flop responds to inputs.
 Verify the truth table and timing behavior.
Experiment 6: Design of an 8-bit Input/Output System with Four 8-bit Internal
Registers

Objective:
To design and implement an 8-bit input/output system with four internal 8-bit registers.
Theory:
 In a typical I/O system, data is transferred between internal registers and external devices.
 The system will contain four 8-bit registers that can be used for temporary data storage and
manipulation.
Procedure:
1. Open CircuitVerse and create four 8-bit registers.
2. Design a control unit to handle data transfers between the input/output system and the
internal registers.
3. Simulate the system by inputting 8-bit data into the registers and verifying the output.
Code/Simulation:
 Use CircuitVerse to design the system with registers and I/O controls.
 Simulate with various input and output combinations.
Observation/Analysis:
 Verify that data is correctly written to and read from the registers.

8-bit Internal Register

8-bit input output system

Experiment 7: Design of an 8-bit Arithmetic Logic Unit (ALU)

Objective:
To design and implement an 8-bit ALU that performs arithmetic and logical operations.
Theory:
 An ALU performs arithmetic (addition, subtraction) and logical operations (AND, OR,
NOT) on data.
 The design should include a selector to choose the operation and generate the appropriate
result.
Procedure:
1. Design the 8-bit ALU using basic gates in CircuitVerse.
2. Implement addition, subtraction, AND, OR, and NOT operations.
3. Use a control line to select the desired operation.
4. Simulate the circuit with different inputs.
Code/Simulation:
 Create the ALU in CircuitVerse with 8-bit inputs.
 Simulate and test the ALU with different operations.
Observation/Analysis:
 Verify the output of the ALU for each operation.
 Ensure that the results are correct for all input combinations.

1-Bit ALU
8-Bit ALU using 1-bit ALU
Experiment 8: Design the Data Path of a Computer from its Register Transfer
Language (RTL) Description

Objective:
To design the data path of a computer system based on its RTL description.
Theory:
 The data path of a computer includes all components involved in moving data between
registers and performing operations on that data.
 The RTL description provides a detailed plan of how data is transferred and processed
within the system.
Procedure:
1. Analyze the RTL description of the computer system.
2. Design the data path in CircuitVerse, including the ALU, registers, and control signals.
3. Simulate the data path by executing sample RTL instructions.
Code/Simulation:
 Use CircuitVerse to design the data path as per the RTL description.
 Simulate and verify the functionality of data transfers.
Observation/Analysis:
 Observe how data moves between registers and verify the correct execution of instructions.

Register to Bus using MUX

Bus to Register using Decoder
Experiment 9: Design the Control Unit of a Computer using Hardwired or
Microprogramming
Objective:
To design the control unit of a computer using either hardwired control or microprogramming.
Theory:
 The control unit is responsible for directing the operation of the CPU by generating control
signals.
 Hardwired control uses fixed logic circuits, while microprogrammed control uses a set of
instructions to control data flow.
Procedure:
1. Choose between hardwired or microprogramming for your control unit design.
2. Design the control unit in CircuitVerse, connecting it to the data path.
3. Simulate the control unit by executing sample instructions.
Code/Simulation:
 Design the control unit and link it to the data path.
 Simulate and verify the correct generation of control signals.
Observation/Analysis:
 Ensure the control signals are correct for each instruction and verify the data flow.
Experiment 10: Implement a Simple Instruction Set Computer with a Control
Unit and Data Path
Objective:
To implement a simple instruction set computer (ISC) with a control unit and data path.
Theory:
 A simple instruction set computer executes a small set of basic instructions such as load, store,
add, and jump.
 The system includes a control unit and a data path for executing these instructions.
Procedure:
1. Design a simple instruction set in CircuitVerse.
2. Implement the control unit and data path for executing the instructions.
3. Simulate the execution of various instructions.
Code/Simulation:
 Use CircuitVerse to design and simulate the ISC, ensuring that the control unit and data path work
together.
Observation/Analysis:
 Observe the execution of each instruction and ensure the correct data transfers between registers.
Experiment 11: Design of N-bit Carry Look-ahead Adder

Objective:
To design and implement an N-bit carry look-ahead adder.

Theory:

 A Carry Look-ahead Adder is designed to improve the speed of binary addition by

calculating the carry signals in advance, eliminating the delay associated with ripple carry
adders.
 The carry look-ahead logic generates carry signals based on the inputs and propagates
them more quickly than traditional ripple carry adders.

Procedure:

1. Start with a 4-bit carry look-ahead adder in CircuitVerse.

2. Implement the logic for generating the carry for each bit position using logic gates (AND,
OR).
3. Extend the design to N-bits by adding more bits to the adder and propagate logic.
4. Simulate the N-bit adder by applying different inputs and verifying the sum and carry
outputs.

Code/Simulation:

 Use CircuitVerse to design the carry look-ahead logic for N bits.

 Test and verify the output for various input combinations.

Observation/Analysis:

 Compare the performance of the carry look-ahead adder with the ripple carry adder.
 Observe how carry propagation is improved, reducing the time delay.
Experiment 12: Design of N-bit Counter
Objective:
To design and implement an N-bit binary counter using flip-flops.
Theory:
 A counter is a sequential circuit that counts the number of clock pulses and progresses through a
predefined sequence of states.
 A simple binary counter counts from 0 to 2N−12^N - 12N−1, where N is the number of bits.
 The counter can be designed using T flip-flops or JK flip-flops to toggle their states on each clock
pulse.
Procedure:
1. Design a 4-bit binary counter in CircuitVerse using flip-flops.
2. Connect the flip-flops such that the output of one flip-flop serves as the clock input to the next one.
3. Simulate the counter and observe how it increments with each clock pulse.
4. Extend the design to N bits by adding more flip-flops.
5. Simulate the N-bit counter with different clock frequencies.
Code/Simulation:
 Design the N-bit counter in CircuitVerse using either T or JK flip-flops.
 Simulate the counter and observe the output in response to clock pulses.
Observation/Analysis:
 Verify that the counter correctly counts from 0 to 2N−12^N - 12N−1 and resets after reaching the
maximum value.
 Observe the timing diagram of the counter and ensure proper toggling of flip-flops.