Received 10 September 2023, accepted 3 October 2023, date of publication 5 October 2023, date of current version 11 October 2023.

Digital Object Identifier 10.1109/ACCESS.2023.3322358

Application of Machine Learning in

FPGA EDA Tool Development
PINGAKSHYA GOSWAMI , (Student Member, IEEE),
AND DINESH BHATIA , (Senior Member, IEEE)
Department of Electrical and Computer Engineering, The University at Texas at Dallas, Richardson, TX 75080, USA
Corresponding author: Pingakshya Goswami ([email protected])

ABSTRACT With the recent advances in hardware technologies like advanced CPUs and GPUs and the large
availability of open-source libraries, machine learning has penetrated various domains, including Electronics
Design Automation (EDA). EDA consists of multiple stages, from high-level synthesis and logic synthesis
to placement and routing. Traditionally, estimating resources and areas from one level of design abstraction
to the next level uses mathematical, statistical, and analytical approaches. However, as the technology node
decreases and the number of cells inside the chip increases, the traditional estimation methods fail to correlate
with the actual post-route values. Machine-learning (ML) based methodologies pave a strong path towards
accurately estimating post-route values. In this paper, we present a comprehensive survey of the existing
literature in the ML application field in EDA, emphasizing FPGA design automation tools. We discuss
how ML is applied in different stages to predict congestion, power, performance, and area (PPA), both for
High-Level Synthesis (HLS) and Register Transfer Level (RTL)-based FPGA designs, application of design
space exploration and application in Computer-Aided Design (CAD) tool parameter settings to optimize
timing and area requirements. Reinforcement learning is widely applied in both FPGA and ASIC physical
design flow, a topic of discussion in this paper. We also discuss various ML models like classical regression
and classification ML, convolution neural networks, reinforcement learning, and graph convolution network
and their application in EDA.

INDEX TERMS Machine learning, electronic design automation, FPGA.

ACRONYMS IR Intermediate Representation.

ADRS Average Distance to Reference Set. MAPE Mean Absolute Percentage Error.
ANN Artificial Neural Network. MARS Multivariate Adaptive Regression Splines.
CAD Computer Added Design. ML Machine Learning.
CDFG Control and Dataflow Graph. MLP Multi Layer Perceptron.
CNN convolution Neural Network. PPA Power Performance and Area.
DRC Design Rules Check. RL Reinforcement Learning.
DSE Design Space Exploration. RTL Register Transfer Language.
EDA Electronics Design Automation. SA Simulated Annealing.
GA Genetic Algorithm. TNS Total Negative Slack.
GAN Generative Adversarial Network. XGB Gradient Boost Regression.
GCN Graph convolution Network.
HLS High Level Synthesis.
HPWL Half Perimeter Wirelength. I. INTRODUCTION
IC Integrated Circuit. As the technology node size decreases due to Moore’s
Law [1], and Dennard’s scaling [2], more and more transistors
are fitted per unit area inside the integrated circuit (IC)
The associate editor coordinating the review of this manuscript and than ever before. With the decrease in technology size, the
approving it for publication was Mauro Tucci . tools used to design the ICs are becoming more complex.
2023 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
109564 For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/ VOLUME 11, 2023
P. Goswami, D. Bhatia: Application of Machine Learning in FPGA EDA Tool Development

FIGURE 1. Different categories in which ML is applied in FPGA EDA Flow.

Electronic Design Automation (EDA) is the branch of science paper, we have surveyed the literature in the ML application
or technology that deals with the tools used to design domain in EDA tool design and optimization, focusing on
integrated circuits. IC design is a highly complex process FPGA EDA tools. We have clustered the application in the
consisting of multiple stages with an average turnaround time following five categories:
ranging from a few days to a few years. While designing i. Power, performance and area prediction in RTL and
an IC, it is always a good practice to estimate the power, HLS Designs
performance, area, congestion, and wirlength of the design ii. Design Space Exploration (DSE)
down the flow in an early stage. Traditionally, this is done iii. CAD tool optimization using ML
using statistical, mathematical, or analytical methods [3], [4], iv. Congestion estimation in HLS and RTL designs
[5]. Although the analytical and mathematical models get v. ML in FPGA Phyiscal Design Flow
pretty accurate estimates, these methods are computationally In Fig. 1, we have shown how ML is applied at various
expensive and consume a lot of time (few hours) to perform stages of FPGA EDA flow. The figure also shows the various
basic estimations like congestion [3], [4] and wirelength [6]. subcategories and ML algorithms applied at each flow stage.
These methods generally solve every problem from scratch We have discussed both analytical and mathematical-based
and do not utilize any experience or knowledge. PPA estimators [19], [20], [21] and ML-based estima-
On the other side of the technology world, another domain tors [22], [23], [24], [25], [26], where the design entry is either
is emerging pretty fast and has shown its application in HLS or RTL input. The prediction models use traditional
almost every aspect of human life known as Machine ML methods like regression and classification and advanced
Learning (ML). ML has seen its applications in various methods like deep learning and graph convolution [26],
domains like image recognition [7], [8], natural language [27] to estimate the PPA of a circuit. For autotuning and
processing [9], [10], [11], audio and signal processing [12], recommendation of CAD tool parameters [28], [29], [30].
[13], [14], etc. This is because the hardware used for training Bayesian methods are used to select the hyperparameters
the models, like GPUs, has progressed significantly with of the CAD tools. Yanghua et al. perform the feature
multiple processors fabricated inside one die along with selection to reduce the number of FPGA CAD parameters to
easy availability of open source training frameworks like consider [31] from 80 to 8 features without compromising
Tensorflow, Scikitlearn, and Pytorch [15], [16], [17]. ML has the quality of results. To reduce the parameter-tuning
also penetrated the EDA domain in the last five to six effort, Kwon et al. [32] propose a CAD tool parameter
years. All the problems that were previously solved using recommender system that involves learning a collaborative
analytical methods [3], [4], [5], [6], [18] are now reframed prediction model through tensor decomposition and regres-
as ML problems. The issues that took a few minutes to sion. ML-based design space exploration of HLS designs
hours using analytical or mathematical methods can now is discussed in [33], [34], [35], and [36]. Reference [30]
be solved using ML-based pre-trained models within a uses Bayesian optimization to perform DSE to optimize
few seconds. Machine learning has found its application an HLS-based CNN architecture, while Carloni [35] uses
in almost all stages of IC designs, which include timing, transfer learning to optimize the designs during DSE.
power, and area estimation; routing congestion estimation, Congestion estimation is another problem that machine
both using classical ML and deep learning methods; design learning can solve accurately and quickly. In [37] and
space exploration; CAD tool parameter tuning; Wirelength [38], the congestion estimation of RTL designs on FPGA
(WL) estimation and lithographic hotspot detection. For this uses classical regression-based ML modes. Reference [39]

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predicts the routing congestion of HLS designs using ML, methods like CNN, GNN, and RL. They only discuss
while [40] and [41] uses convolution neural network(CNN) wirelength estimation in placement and Design Rules Check
methods to forecast the congestion on post-placed images of (DRC) hotspot detection in post-routed circuits. Paper [46]
logic netlists. and [49] discuss hotspot and DRC violation prediction using
As shown in Fig. 1, ML can be applied at different stages ML in ASIC circuits and static timing analysis using ML.
of the logical and physical design flow, from quality of These two papers are more of a roadmap paper than a
results (QoR) estimations to hyperparameter selection and survey paper. These papers discuss in what different domains
design space exploration. In this paper, we comprehensively ML can be applied to future IC designs. Similar to [46]
reviewed how ML is applied in different stages of FPGA and [47] is a roadmap that discusses performance limitations
physical design flow, along with some insights into future of traditional compute and storage systems and the systems
developments and open research areas. The rest of the and infrastructure considerations for performing machine
paper is organized as follows: Section II, we discuss learning at scale. This paper also briefly discusses how ML
the other works, where application of ML in EDA tool can be applied to solve functional verification and debug
development for both ASICs and FPGAs have been studied; problems. Even though [48] is not a proper survey paper, the
in Section III, we discuss the various ML models applied authors discuss how RL can be applied to solve various circuit
in EDA tool design, which includes classical regression design problems like DRC violations, layout, and routing
and classification, CNN, reinforcement learning, transfer issues. This work profoundly focuses on using Reinforcement
learning, and graph convolution network (GCN). From Learning (RL) to solve post-route violation issues.
Section IV to Section VIII, we discuss in detail the five As the above discussion shows, most existing surveys are
categories in which ML is applied for FPGA CAD. Finally, highly focused on IC development or EDA tools for ASICs.
Section IX summarizes the paper’s contents and looks into Even though there are many recent works in which ML
future trends and directions. has been applied to solve various FPGA physical design
problems, their discussion has been limited to the ‘‘Related
II. RELATED SURVEYS IN ML BASED EDA TOOL Works’’ section of the papers only. No comprehensive survey
DEVELOPMENT is available that discusses the existing work of ML-based
There are few survey papers in which different works in FPGA CAD tool design. To address these loopholes,
the ML application domain in EDA have been studied [42], we created this detailed survey in which we exclusively
[43], [44], [45], [46], [47], [48]. Most of these works are review various works in which ML has been applied to
either too generic for ASIC [42], [45] or too specific to multiple FPGA CAD tool design stages. We discuss both
a particular domain [43], [44], [48]. These papers discuss ML-based HLS tools and ML-based RTL tools for FPGAs.
how ML has been applied to predict or improve the This paper surveys the recent advancements in GNN and RL,
CAD tools’ performance to design ASICs. Discussion of which have been widely applied to the synthesis, placement,
ML-based FPGA CAD tools has been neglected in survey and routing of FPGA circuits.
papers. Reference [42] is a comprehensive survey in which
they have performed a detailed analysis of how ML can III. BASICS OF MACHINE LEARNING
be applied to various stages of ASIC design flow. They ML algorithms are broadly divided into two classes:
discussed ML applications for ASIC physical design, power
(i) Supervised Learning
delivery network and IR drop analysis, lithography and mask
(ii) Unsupervised Learning
production, analog IC design, device sizing automation, and
verification and testing. As we can see here, in this work, Most of the ML models used in EDA fall under supervised
all the predictions are targeted for nanometer scale ASIC learning, including regression, classification, Convolution
physical design flow. They have minimal discussion on the Neural Networks, and Graph Convolution Network. The
FPGA front, that too on the HLS part, but nothing has CAD tool optimization or Design Space Exploration tools
been discussed about prediction in various stages of FPGA use Bayesian learning and the Gaussian process to set the
physical design. In [43], the authors surveyed exclusively on hyperparameters of the CAD tools. In Table 1, we have
applying graph neural network (GNN), ASIC physical design mapped the different EDA applications to the ML models
flow. The paper [43] discusses primarily the theoretical used.In this section, we have discussed the ML algorithms
details of GNN, and the discussion on applying GNN on mentioned in column 1 of Table 1 in detail.
EDA has been minimal. In another work, [44], the authors (i) Linear Regression: Linear regression is a method to
discussed explicitly the application of ML in analog circuit find relationship between two continuous variables;
design. They mentioned the ANN ANN-based analog IC one is independent, and the other is dependent. Linear
design process, the hybrid analog IC design automation regression tries to create a statistical relationship that
process, and the application of ANN and RL in analog may not always be deterministic. Linear regression
IC manufacturing. In [45], the authors briefly discuss the tries to obtain a straight line that shows the relationship
application of ML in the placement and routing of ASIC between the independent and the dependent variable.
designs. There is no mention of FPGAs, HLS, and recent For most of the linear regression models, the error

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TABLE 1. ML models and their applications in EDA flow.

is measured using the least squared error. A linear as ‘‘knots’’. If there are multiple knots present in the
regression line has an equation of Y = a + bX , where MARS equation, it may lead to overfitting.
X is the explanatory variable and Y is the dependent (iv) Multi Layer Perceptron based Regression (MLP):
variable. The slope of the line is b, and a is the MLP-based regression models comprise multiple per-
intercept, which is determined during model training. ceptrons known as neurons. This type of model falls
(ii) Random Forest Regression(RF): Random forest is into the feedforward class of artificial neural networks.
a supervised learning method that uses ensemble Generally, Artificial Neural Networks (ANN)s are
methods for learning. Ensemble learning is a technique used for classification. But they can be used for
that combines multiple weak learners to create a strong regression, too. MLP-based models are trained using
learner. In random forests, these weak learners are a backpropagation algorithm. Each network consists
decision trees. The outputs from the individual learners of an input layer of neurons, a few hidden layers,
are averaged to generate the final output. Random and an output layer. The output of each function is
forest belongs to the bagging class of learners where, linear. To make the output non-linear and emulate the
during training, data samples are selected at random real-world behavior, activation functions like ‘‘tanh’’,
without replacement. Bagging makes each model run ‘‘RELU’’ and ‘‘sigmoid’’ are added.
independently and then aggregates the outputs at the (v) Gradient Boost Regression (XGB): Similar to ran-
end without preference for any model. Because of dom forest regression, Gradient boost regression is
the introduction of the bagging method, the chances also an ensemble class of ML model. Boosting is
of overfitting are less in a random forest. Random a method of converting weak learners into strong
forest is a very fast training method because each learners. Unlike random forest regression, where we
tree can be trained in parallel, and the inputs and use fully grown trees, in XGB, the trees are weak
outputs of each tree are not related to one another. learners; hence, shallow trees can also be used for
To summarize, Random Forest Algorithm merges the fast learning. In boosting, each new tree is fit on a
output of multiple Decision Trees to generate the final modified version of the original data set. XGB uses
output. multiple trees in sequence, which fixes the error of
(iii) Multivariate Adaptive Regression Splines (MARS): the previous tree. The XGB uses a gradient decent
Multivariate adaptive regression splines [65], an algorithm on the loss function to minimize the error
algorithm that automatically creates a piecewise generated by the previous trees. The XGB method
linear model which creates a nonlinear model by keeps adding trees one after another iteratively until
combining multiple small linear functions known as there is no improvement in the loss. The loss function
steps. In MARS, non-linearity is introduced by using used is either sum of squared error (SSE) or mean
step functions. There are no polynomial terms in the square error (MSE) [66].
MARS equation. Equation 1 shows the linear stepwise (vi) Graph Convolution Network(GCN): With the wide
equation: application of deep learning, neural networks are an
effective and efficient model for tasks like classifi-
yi = β0 + β1 C1 (xi ) + β2 C2 (xi ) + · · · + βd Cd (xi ) + ϵi ,
cation and regression. However, neural networks like
(1) ANN and CNN only take vectors or tensors as input
MARS is an adaptive procedure for regression and is data, which makes it difficult to work on graphs.
well-suited for high-dimensional problems (i.e., many Defferrard et al. generalize convolutional neural net-
inputs). The bends in the step functions are known works from regular grids (e.g., images) to general

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graphs via graph convolutional filters [67]. Later,

Kipf and Welling simplify the convolutional operator
and propose a graph convolutional network [68].
Graph learning techniques can be categorized into
transductive and inductive settings. Under the trans-
ductive setting, the embedding of each node is directly
optimized, and thus, the training process requires
seeing all the nodes. The original GCN [67] is one kind
of transductive approach. The inductive approaches
learn a general rule from the training graphs through
sample and aggregation of structural information and
node attributes. The learned model can be applied to
unseen data.
(vii) Reinforcement Learning(RL): Reinforcement learn-
ing is an ML algorithm in which the machine tries to
learn by itself. The machine repeatedly uses trial and
error to learn from its own experience. To program
the machine, the programmer sets rewards for correct
actions and penalizes the machine for wrong actions.
The goal of the machine is to maximize the rewards.
Unlike supervised learning, the training data of
reinforcement learning have no labels. By leveraging
the power of search and many trials, reinforcement
learning is currently the most effective way to hint at a
machine’s creativity [69], [70]. FIGURE 2. Conventional FPGA routing flow and the AI based flow shown
(viii) Bayesian Optimization: Bayesian optimization is an in dotted line on right.
optimization technique that uses Bayes Theoram to
find the global maxima or global minima of a non-
convex, non-linear, multi-dimensional function. It is developed ML-based congestion estimation methods for
highly suitable for optimizing functions consisting of FPGAs and ASICs. They have used traditional regression
less than twenty dimensions. Bayesian optimization models on RTL netlists [37], [38] and HLS designs [39].
consists of two parts: a Surrogate Function, which uses Other researchers have addressed the FPGA congestion
the Bayesian model to model the objective function, prediction problem as Generative Adversarial Network
and an Acquisition Function to decide what dimension (GAN) and CNNs [27], [41]. In these models, the authors
value to sample next. Gaussian Process Regression apply image-based GAN and CNN algorithms to detect
is an example of an acquisition function. Bayesian congestion hotspots on the 2D images of post-placed netlists.
optimization is used in hyperparameter tuning of ML This section discusses the ML-based works to predict
models and hyperparameter of CAD tools [29]. congestion on FPGA netlists. In Fig. 2, we have shown
a conventional FPGA/ASIC design flow starting from the
In the rest of the paper, we will discuss the various RTL code to the routing congestion map level. On the right
applications of ML in EDA flow. side, we have shown how ML can be applied right after the
placement stage to get a quick estimate of the post-route
IV. ML IN ROUTING CONGESTION ESTIMATION congestion value. The applied ML model can be traditional
Detailed routing is the most time-consuming stage in VLSI regression/classification methods or image-based models like
or FPGA design flow. Generally, the routing in VLSI is CNN and GAN (generative adversarial network).
divided into two stages: a) Global Routing and b) Detailed
Routing. Congestions generally occur in the detailed routing A. ROUTING CONGESTION PREDICTION USING
stage, which results in a violation of DRC rules, and the CLASSICAL ML MODELS
circuit sometimes becomes unroutable. Routing congestion There are three recent works in which FPGA recent works in
can be measured accurately only after detailed routing has which the FPGA routing congestion prediction problem has
been completed, which takes a lot of time. Because of been addressed as a regression problem [37], [38], [71]. The
these reasons, predicting the approximate value of routing authors divided the FPGA architectures into global routing
congestion before the actual detailed routing stage can cells called gcells, which consist of one CLB and one switch
save both time and energy for the designers. Since global box, and predict the routing congestion in each gcell. In [37]
routing-based congestion estimation cannot be estimated and [38], the authors considered various intrinsic properties
accurately for smaller technology nodes, researchers have of post-placed FPGA netlists like pin density, Wirelength Per

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TABLE 2. Classification of ML algorithms and their application in congestion estimation.

Area (WLPA), Net Cut Per Region (NCPR) etc., as their approach can achieve high prediction accuracy for large
features to the regression model. Goswami et al. [71] FPGA designs while relying on well-engineered features
considered a total of nine features for their model, which that encode the placement and connectivity information
include LUT and Flipflop utilization, incoming/outgoing for large-scale designs. The main contributions of [40]
and fully local nets in each gcells and relative location of include selecting features only from post-placed netlist
each gcell inside the FPGA device. All three works tested image, estimation of the routing channel utilization by
and verified their models on ISPD 2016 [72] benchmarks. forecasting the full congestion heat map instead of hotspots
While [37] and [38] divided their dataset into 70% train and only, and integration with placement tool to estimate routing
30% test dataset, [71] predicted on individual benchmarks. congestion on the fly during placement. Both tools can be
To create their models, the three works used conventional easily integrated with open-source academic placers like
regression methods like linear regression, random forest, and UTPLace and GPlace [74], [75] and achieve very high
gradient boost. accuracy.

B. ROUTING CONGESTION PREDICTION IN HLS DESIGN

D. SUMMARY OF ROUTING CONGESTION WORK AND
One of the major limitations of the current commercial FUTURE DIRECTIONS
HLS tools is that it cannot estimate routing estimation, even The application of ML to solve congestion estimation can
inaccurately. In [39], Zhao et al. address this issue by creating be broadly classified into two classes: (a) Using traditional
an ML model that predicts routing congestion after the regression methods and (b) Using image-based GAN meth-
C-synthesis stage, i.e., before actual RTL synthesis. If high ods. Also, the design entry to the tool can be either RTL-based
congestion is detected for a certain portion of the code, they or HLS-based. In Table 2, we have summarized all the
suggested methods to modify the high-level C/C++ code, ML-based congestion estimation tools for FPGAs and the
reducing congestion after routing. To do so, they converted models used for prediction. In most cases, the performance
the HLS code into LLVM-IR [73] and backtracked each of the post-route congestion estimation tool is measured in
of the instructions on the IR code to the actual layout terms of mean absolute percentage error (MAPE). In row
after routing. The back tracing is done in the following 4 of Table 2, we present the average error reported in each
way: of the six works. Since post-route congestion is estimated
Congested CLB → gate level netlist → RTL code → IR after the placement stage of the FPGA physical design
code → HLS code process, for RTL-based designs, features are extracted from
Once the source of the instruction for the congested CLB is the post-placement netlists. Even for GAN-based designs,
determined in the HLS code, features are extracted to create placement netlists are converted to images, and features are
a regression model. The regression model is later used to extracted from those images. For example, in [41], encoded
predict the post-route congestion from the high-level C/C++ feature maps in high-definition images are created for pin
and LLVM IR codes. density vertical and horizontal routing congestion from post-
placed netlists. Similarly, in [40], different color schemes
C. ROUTING CONGESTION PREDICTION USING GAN are used in post-placement images to represent routing
BASED METHOD channels, CLB spots, multipliers, memories, IO blocks, and
The work described in [40] and [41] addressed the routing connectivity matrices. Row 6 in Table 2 represents the feature
congestion estimation problem as a conditional generative sources, while row 7 represents the datasets. Although all the
adversarial network (CGAN) problem. In both works, work discussed in this section can accurately estimate the
the authors transfer the routing congestion problem in routing congestion, almost all the estimation is done only
large-scale FPGAs to an image-to-image problem and then for CLB levels. No work estimates routing congestion for
use conditional GAN to solve it. In [41], proposed a DSPs or BRAM, even though they consume a significant
new placement-based routing congestion prediction approach amount of resources in modern designs. Also, none of the
for large-scale FPGA designs. The proposed approach work is properly integrated with open-source or commercial
adopts a new CGAN model, namely pix2pixHD, which implementation tools. Easy integration of the prediction
performs high-definition (HD) image translations for large models with existing physical implementation tools is still an
high-resolution images. With HD image translation, this open research direction.

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learning method to speed up the design space exploration

process, which can judiciously sample representative and
hard-to-predict micro architecture choices and use them for
training the learning model; in [79], the authors use ML
to eliminate those points from the design space, which are
almost certainly non-optimal. To do so, in [79] the authors
propose a framework called Adaptive Threshold Non-Pareto
Elimination (ATNE). Instead of improving the learner’s
conventional accuracy, this work focuses on understanding
and estimating the risk of losing ‘‘good’’ designs due to
FIGURE 3. High level diagram of ML based DSE [36]. learning inaccuracy. Both these works use regression models
V. ML BASED DESIGN SPACE EXPLORATION OF HLS to predict the area and latency requirement of the HLS designs
DESIGNS and result in very fast exploration time. One drawback of [36]
In High-Level Synthesis, there are various methods that the is they tested their model only on 242 designs, which is a
designer can use to optimize their design in terms of area, very small subset of the actual design space of their tested
latency, and timing. The process by which the designer design. Sohrabizadeh et al. [81] proposed a bottleneck-guided
achieve the best set of designs in term of area and latency by gradient optimizer to find a better design point later used
changing the parameters of the HLS tool is called ‘‘Design in DSE systematically. They use a heuristic for ordering the
Space Exploration’’ (DSE). In HLS designs, there are three parameters, which can eliminate the redundant design points,
different ways known as ‘‘knobs’’, which the designer can thereby reducing the design space significantly.
use to optimize their designs [76]. The three knobs of HLS
B. DESIGN SPACE EXPLORATION USING TRANSFER
designs are:
LEARNING
1) Pragma-based local synthesis Transfer learning is widely applied in DSE of HLS. In transfer
2) Global Synthesis Options learning, the model is trained on one set of designs, and with
3) Functional Unit Constraints minor modifications, the model can be deployed on another
The main challenge HLS users face is setting these new set of designs for inference. In [35], [53] and [82], the
knobs to obtain a design with the desired characteristics, authors apply transfer learning to move knowledge from a set
considering that the total number of knob settings is of previously explored source designs to an unexplored target
extremely large. There are both traditional optimization design. In [53], ML is not used, but the authors use a novel
methods like simulated annealing based, genetic algorithm method, where mapping from the source design to the target
based, ant colony optimization and gradient decent [33], [77], design is done analytically for selecting the source design
[78] based methods and machine learning based methods and the source directives. Here, the authors propose a code
to perform DSE [33], [34], [35], [36], [79], [80]. Some of similarity matching model using string-similarity algorithms
the works combine both traditional methods and ML-based to quantify the similarity in terms of computational patterns
methods [33]. Thus, the goal of HLS DSE is not to find a that exist between a source design (from a library capturing
single solution but a set of designs, typically called Pareto prior knowledge) and the target design. After identifying
optimal designs or microarchitectures, which form the Pareto similar designs, the next step is selecting the designs with
frontier (P̄). P̄ can be defined as a set of dominating designs similar pragma settings. The authors select the Pareto-optimal
P̄ = d1 , d2 , . . . , dn such that for any design di ∈ P̄; A(di ) ≤ curve among the pragma settings in a source design and
A(dq ) and L(di ) ≤ L(dq ) [76]. There are twelve (Table 3) translate the Pareto-optimal curve from the source design to
very recent works in which ML is applied to find the Pareto the corresponding ones in a target.
optimal curve in DSE for HLS. The researchers mostly use In [35], Kwon et al. apply transfer learning (TL) to speed
regression and transfer and active learning-based methods to up the DSE process in HLS designs. The main theme of
perform DSE. In Fig. 3, we have shown the high-level flow of this paper is to extract the knowledge obtained from the
ML application to solve the DSE problem, which is common previously explored spaces of source designs and apply it to
to most of the discussed papers. As shown in Fig. 3, most the early stage of DSE of a new target design. In [82], the
of the ML-based DSE tools initially synthesize a portion of authors train a set of DSE points on ASIC, and using ML,
the designs in real-time, which becomes the sample training they predicted the performance of the same designs on FPGA.
dataset (shown in gray can in Fig. 3) and the rest are done They have transformed the learning model from ASIC DSE
using ML-based approach (shown in green can in Fig. 3). to predict on FPGA DSE.

A. DESIGN SPACE EXPLORATION USING STANDALONE ML C. DESIGN SPACE EXPLORATION USING COMBINATION
In [36] and [79], the authors use traditional ML algorithms to OF ML AND METAHEURISTICS METHODS
find the Pareto optimal curve. While [36], the authors have There are a few works [33], [34], which is a fusion of
proposed a transductive experimental design (TED) based both metaheuristics-based methods like Simulated Annealing

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TABLE 3. Machine learning based design space exploration works.

(SA), genetic algorithm (GA), gradient descent, Ant Colony good design space explorer. The larger this value is, the
Optimization (ACO) etc. and machine learning models. worse the performance of the explorer. An explorer aims
In [33], the authors use decision trees to speed up the to minimize the ADRS or runtime. This is done by either
simulated annealing algorithm. Here [33], the authors use minimizing the design space [35], [79] or by applying transfer
a decision tree to reduce the design space to speed up the learning from a different set of designs [35], [53] or from
DSE time and achieve comparable results to a non-pruned another platform like ASIC [82]. Most of the papers [34],
standard simulated annealing-based DSE. In the initial [35], [36], [53], [80], [82] measure the performance of
phases, standard simulated annealing generates designs based their DSE tool in terms of ADRS. In Table 3, column 3,
on the previous design’s cost function. The initial designs we show what QoR measures are being used to measure
are used to generate a decision tree to decide which of the performance of the DSE tools as discussed in the
the attributes contributes to maximizing the cost function. papers, while in column 4, we reported the average ADRS
The attributes from the decision tree, which shows high values of the various designs used in each paper. For papers
correlations, are fixed, while the less important attributes where QoR is measured using some other parameters like
are selected pseudo-randomly. This considerably reduces the runtime, resource or latency requirements, the average of
design space and allows finding the Pareto-front faster than those values is reported. In columns 5 and 6, the benchmarks’
a regular simulated annealer. In [34], the authors use ML to names and the design space’s maximum size are shown,
select the hyperparameters of the metaheuristic algorithms respectively. Although there are few standard benchmarks
used in the DSE. Some of the meta-heuristic parameter like Chstone [84], Machsuite [85], Polybench [86] and
examples selected in this work are the initial and final S2Cbench [87] are available, most of the researchers try to
temperature, the descent rate, the exit condition in simulated generate their dataset [35], [36], [79], [81], [83]. Even if they
annealing, and, in the GA case, the number of parent pairs and use the existing benchmarks, they generate their own design
the mutation and crossover rate. The authors also proposed versions. Hence, a fair comparison of the works is difficult
a combined SA, GA, and ACO concurrent multiheuristic to perform. Generating datasets to train ML models for PPA
design space explorer. In [80] Goswami et al. combined estimation or DSE is an extremely time-consuming process,
heuristics-based Simulated annealing and ML regression which can take weeks and months. To address this issue, [88],
model to design a fast design space explorer in real designs. [89], and [90] benchmarks have been created, specifically
The initial part of the DSE algorithm runs on logic synthesis- curated for ML training. These are large datasets similar to
based results, and once a sufficient amount of data (design computer vision datasets like Imagenet [91], or Cifar10 [92],
points) has been generated, they create an ML model and which are off-the-shelf datasets that the ML-based EDA
switch to fast ML-based predictive DSE. They used this work researchers can directly use for training purposes. Another
to run DSE on different CNN architectures [83]. In [26], new direction of research is to eliminate the synthesis
the authors created a fast DSE by applying GNN on LLVM tools from the loop by using methods like LLVM [93] or
IR graphs, which predicts a design’s resource and latency MLIR [94] methods, which was used in [26] and [80].
requirements.
VI. MACHINE LEARNING IN FPGA CAD TOOL
D. SUMMARY AND FUTURE DIRECTIONS FOR ML BASED PARAMETER SELECTION
DSE As the technology node decreases, the CAD tools used
One of the figures merits of measuring the performance to design the ICs are also becoming very complex. Many
of a DSE tool is called ‘‘Average Distance to Reference parameters are involved in EDA tools, which results in a huge
Set’’ (ADRS). This parameter measures how close the design space. The runtime complexity of the CAD tools is
predicted DSE points are to the exhaustive search-based DSE also very large, and designs take multiple weeks to synthesize
points. If the value of ADRS is close to zero, it is a very at each design point. Modern CAD tools used for logical

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FIGURE 4. High level diagram showing how ML is used to recommend CAD tool parameters.

synthesis and physical design have hundreds of parameters to suggest the best timing solutions. InTime is an iterative
in them, which are set to meet various timing and area algorithm organized as a series of concurrent CAD runs.
requirements of the designs. The design space of these tools is Each round, which consists of multiple concurrent runs,
humongous, and manually selecting the tool parameters will is an opportunity to generate candidate CAD parameter
take ages and may not always generate the optimum design combinations and acquire data for analysis. Within each
in terms of power, performance, and area. To recommend round, InTime uses a supervised learning approach to
tool parameters and minimize design space in EDA tools, train classifiers that evaluate the effectiveness of a given
researchers have used Bayesian optimization [29], [30], [95], combination of CAD parameter selections toward increasing
classification [28], [31], [54], Principal component analysis timing slack.
for design space pruning [95] and tensor decomposition and Reference [31] is an extension of Intime [28]. In this
regression [32]. Researchers minimized the tools’ runtime paper, the authors proposed a method to select the best
and generated area and timing-efficient designs using these CAD tool parameters using a classification problem. They
methods. This section discusses seven recent works in which have minimized the search space using the Principal
ML is applied to minimize search space in EDA tools and Component Analysis method. To train the model, they
generate optimized designs. In Fig. 4, we have shown the used the shelf ML models like Logistic regression (glm),
high-level diagram of how ML can recommend CAD tool Bagging (treebag), Random Forest (rf), Support
parameters for FPGA design. The input to the recommender Vector Machine (SVM) (svmRadial) and Neural Network
system is generally the RTL code, a set of logic synthesis (nnet). Here also, the authors minimized the clock period
and physical design parameters that need to be tuned, and using the suggested CAD parameters.
the desired specs in terms of area and performance. The Similar to [28] and [31], LAMBDA [55] also tries to
recommender system considers the specs and the RTL code, maximize TNS. In [28] and [31], parameters of single
and using ML, it suggests the best set of tool parameters to stage are tuned, i.e only for logic synthesis, placement or
be used. All the works discussed in this section use a variant routing. But in [55], parameters of multiple stages are tuned
of this flow. simultaneously. They combine the features from multiple
stages to predict post route QoR of the designs. They
A. RECOMMENDER SYSTEM TO SUGGEST PARAMETERS addressed the problem as a regression problem and used
TO MEET TIMING gradient boost regression to solve it.
The works discussed in [28], [31], and [55] propose methods
to suggest CAD tool parameters to maximize total negative B. GENERALIZED PPA RECOMMENDER SYSTEM
slack (TNS). InTime [28] is a plugin for FPGA CAD tools There are few other works [29], [30], [32], [54] which are
that can automatically select tool parameter assignments for much more generalized than those discussed in Section VI-A.
each design by using machine learning heuristics and cheap These works suggest parameters not only to optimize timing
cloud computing resources. While modern CAD tools have but also to optimize other metrics like power, timing, and
hundreds of parameters, InTime uses only 25 parameters area. Reference [29] proposed a method that is used to

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automate the flow selection in IC design using the Bayesian TABLE 4. Summary of CAD tool autotuning works.
optimization method. Their optimization function optimizes
a cost function consisting of power, performance, and area
values. They automate the flow selection at logic synthesis
and the place and route stage. They have used Gaussian
process regression as the surrogate function for the Bayesian
model. Using Bayesian optimization, the authors tuned six
parameters, four of which are during the logic synthesis
stage and two during the place and route stage. Similar
to [29] and [32] also suggests tool parameters both at logic VII. MACHINE LEARNING TO PREDICT POWER,
synthesis and place and route stage, using a two-step process. PERFORMANCE AND AREA ESTIMATION IN FPGA
In the first stage, an ML model is trained offline. They DESIGNS
have used macros and small partitions of large-scale, high- Power, performance, and area estimation are crucial in
performance server processor chips for training. Once the any VLSI physical design flow. The earlier we predict the
model is trained, in the second stage, the tool inputs the post-route QoR of design, the better it is so that the designer
macro name whenever a new macro comes. Suppose it is can go back and set the tool parameters to meet the specs.
previously seen macro, set of cost functions to be optimized, Few recent works use analytical or mathematical models
or some baseline synthesized results for new macro and or machine learning models to predict the post-route QoR
recommends the set of tool parameters to meet the objective of both HLS and RTL designs. Works like COMBA [20],
function. Although the paper presents a nice idea about the LinAnalyzer [19] and Aladdin [21] use analytical methods to
recommendation system, nothing has been mentioned about estimate the post route PPA of HLS designs, whole ‘‘Fast and
the ML model or feature sets. Also, the paper does not discuss Accurate’’ [22], Pyramid [25], XPPE [23], HLSPredict [23]
the accuracy of the resultants QoR of the recommendation and Powergear [63] use ML-based methods to estimate the
system. post route QoR of HLS designs. In [50] and [51] ML has been
Reference [54] proposes a totally new approach compared used to predict timing in RTL-based FPGA design, while
to the already discussed ones. Instead of suggesting hyper- in [62] and [63], GNN is used to predict power in FPGA
parameters for CAD tools, this work suggests which will be designs..
the best tool to use to meet the specs of a particular design.
They address the problem as a binary classification problem; A. ANAYTICAL METHODS FOR PPA ESTIMATION OF HLS
for placement purposes, they selected two popular academic DESIGNS
placers, gplace3.0 [75] and UTPlacef [74]. This work does Aladdin [21], Comba [20], and Lin Analyzer [19] are three
not discuss the quality of the generated placed circuits in recent works that estimate power, performance, or area
terms of timing, area, or power. for HLS designs either individually or together using
analytical and mathematical approaches without the need
of any ML models. Aladdin [21] is a pre-RTL power
C. SUMMARY AND FUTURE DIRECTIONS performance simulator designed to enable rapid design space
In Table 4, we have summarized the work done in exploration of accelerator-centric systems. This framework
the ML-based CAD tool parameter optimization domain. takes high-level language descriptions of algorithms as inputs
Except [29], all the other works are classification or and uses dynamic data dependence graphs (DDDG) to
regression. In the classification ones discussed in [28] and represent an accelerator without generating RTL. Starting
[31], the authors predict whether the QoR (area/timing, etc.) with an unconstrained program DDDG, which corresponds
will be met or not met using a certain set of tool parameters. to an initial representation of accelerator hardware, Aladdin
Similarly, in [54], a binary classification method is used to applies optimizations and constraints to the graph to create
suggest which of the two academic placers is suitable to a realistic model of accelerator activity. Alladin generates
place and route a certain design; most of the work [28], different optimized DDDG graphs and applies various
[29], [31] work only at one stage of the physical design mathematical calculations to estimate the cycle-wise power,
flow; i.e., either at synthesis, placement or routing. They timing, and area requirement.
cannot optimize parameters parallelly in multiple stages. COMBA [20] is an analytical engine that is used to
This issue is addressed in LAMBDA [55], where they try suggest pragmas during DSE. To generate the pragma
to simultaneously autotune the hyperparameters in multiple recommendations, COMBA uses a database called recursive
stages, from logic synthesis to routing. Bayesian optimization data collector (RDC) and a metric-guided design space
is a popular hyperparameter optimization method which is exploration (MGDSE) algorithm. In input to the tool is a
widely used in ML frameworks to select optimal parameters. high-level HLS code written in C/C++. COMBA converts
More research can be done in using Bayesian optimization the HLS code into LLVM IR [73] codes and corresponding
methods for recommending automatic parameters in EDA control and dataflow graphs (CDFG). By running analysis
flow at different stages. on the LLVM IR code and the CDFGs, they create a

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mathematical model to estimate an FPGA design’s latency Graphs (CDFG) to generate the graphs. They created a bunch
and resource requirement. Based on the estimated resource of microcircuits from the CHstone [84] benchmark suite
and latency requirement, the MGDSE suggests pragmas for to test their model and achieved 72% reduction in root-
the next iteration. One major drawback of this work is that mean-square error compared to operation delay estimation in
it compares their estimates against the estimation done by Vivado HLS.
Xilinx Vivado HLS after the C-synthesis stage. Since the Ironman [26] is a unified HLS PPA predictor and DSE tool
value reported by Vivado HLS is highly inaccurate [22], that uses ML in both stages. In the first stage, they use a graph
[25], [96], hence the estimation of COMBA is also wrong. neural network to estimate the LUT requirement and timing
However, their latency estimation is very good as compared of the HLS designs. In the second stage, Reinforcement
to post-HLS estimation by the Vivado HLS tool. Learning is used to create the DSE. They also created an
B. ML BASED METHODS
intermediate stage called Code Transformer (CT), which
converts the high-level HLS code into CDFGs. In this work,
In [22] and [25], the authors predicted post-route resource
they proposed a transformation methodology that maps the
and timing requirements of HLS designs by using regression
multiplication operation to LUT or DSPs in an optimized
models based on post-synthesis log files. Generally, the
manner depending on the latency and resource requirement.
QoR reported by an HLS tool after the C-synthesis stage
They tested on eight real and synthetic benchmarks from
varies significantly compared to post-route results. In [22],
CHstone and Machsuites benchmark suites and achieved
the authors analyzed the log files generated after the
less than 10% Mean Absolute Percentage Error (MAPE)
C-synthesis stage to extract various features to minimize
for both resource and timing requirements. Even though
the error. Later, they created regression models, which
they discussed a DSE, nothing has been mentioned about
include Artificial Neural Networks, Linear Regression, and
the ADRS values as compared to metaheuristics-based
XGBoost, to predict the post-route area and performance of
approaches like SA and GA. The strategy for DSE is also not
the designs. The work described in Pyramid [25] is very
properly discussed in the paper.
similar to [22]. Although the prediction results are good,
References [62] and [63] are two recent works in which
a major drawback of this work is we have to run C-synthesis
GNN has been applied to predict power in RTL and HLS
on the designs to extract features. Also, they did not report the
designs. In this work [63], the authors predicted early-stage
error/accuracy on individual benchmarks. The details of the
power estimation in HLS design using GNN. They considered
used features are also missing in the work. In [96], the authors
the impact of interconnects in power modeling to model
created regression models to predict post-route resource,
their predictor accurately. Here, they have created their graph
timing, and latency of HLS designs based on features from
from the HLS design. The HLS design is converted into
the high-level C++ code and LLVM IR codes, in, [97] the
graphs, where the nodes are represented as operations, and
authors constructed a regression model using four different
node features indicate micro-architectures. The edges are
regression models. They extracted the features from the post-
interconnected, and edge features are represented as netlist
high-level synthesis log files and the labels from a customized
activities. They later created a customized GNN to predict
activity generator. They later used the model to create a
dynamic and total power in an HLS design. Traditionally,
design space explorer for latency vs power consumption
in RTL-based designs, power is estimated using gate-level
and achieved very low ADRS values. However, the work
simulation of the synthesized netlist, switching activity
does not mention the details at which stage the labels are
estimation (SAE), and input-output register toggle rates. This
generated. A random forest-based ML is explored to predict
method is very slow and can take months. In [62], the authors
net delay in FPGA placement was proposed in [51]. Most of
used gate-level netlists and corresponding input port and
the features are extracted from the post-synthesized netlist,
register toggle rates over a power window from simulation as
which includes fanout, Half Perimeter Wirelenth (HPWL),
input as the training graph and the toggle rates from gate-level
congestion, critical path length etc. They later applied the
simulation as labels. They used the model to predict SAE,
Recursive Feature Elimination (RFE) method to reduce the
which can later be converted to power.
number of features to 20 and used it to predict delay in
RTL-based designs. D. CROSS PLATFORM BASED METHODS
C. GRAPH LEANING BASED METHODS In [23] and [24] use a methodology in which training is
References [26] and [27] use graph learning methods to pre- done on one set of architecture/platforms but prediction is
dict the post-route timing of HLS designs. In this work [27], done on FPGAs only. Unlike RTL code, HLS code written in
the authors proposed a graph-based learning method to high-level languages like C/C++ can run on any architectures
measure the delay of post-mapped arithmetic operations in like CPU, GPU and microcontrollers. The authors leveraged
HLS designs. They used Graph Neural Networks (GNN) to this in [23] and [24]. In [23], the authors run multiple
do so. Since GNNs can be used to predict the property of designs on different Xilinx FPGA devices and predict the
nodes and edges, they leveraged this property to predict the performance or speedup on Arm A9 devices. To create the
delay of mapped arithmetic operations. They convert the HLS model, they have extracted features from the post-C-synthesis
code into LLVM IR and corresponding Control and Dataflow log files, which are very similar to ‘‘Fast and Accurate’’ [22]

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TABLE 5. Summary of machine learning based power, performance and area prediction tools.

and Pyramid [25]. This model helps designers to create a are slower as compared to LLVM-based models like [20],
heterogeneous system to divide which portion of a design to [26], [27], and [96]. Most of the works discussed here use
run on the FPGA part and which part to run on Arm part. The their design entry as HLS because of the fast synthesis,
major drawback of this work is the authors did not consider implementation time, and large availability of benchmarks.
the effects of pragmas on their HLS designs. In the RTL-based works shown in Table 5 [21], [51], [62] they
In [24], the power and performance of an HLS design use features from synthesized gate-level netlists to predict
running on FPGA is predicted by creating a ML model based a design’s power and timing requirements. While most of
on features generated after running the design on CPUs. the works discussed here predict either resource or timing
HLSPredict ensures time synchronicity between the host or latency, the work in [96] and [98] is a comprehensive
CPU and the target FPGA accelerator by using sub-traces one that can predict all the four post route QoR metrics
for model training: sub-traces are epochs of workload of a design viz., Latency, Resource Requirement, Timing,
execution time in the form of CPU countermeasures for the and Power. There is no work in which more advanced ML
host, and FPGA cycle counts for the target. The authors models like BERT, Transformer, or Autoencoders are being
perform a detailed analysis of a design running on x86 CPU used to enhance and predict the performance of EDA tools.
by identifying the CPU microarchitectural subsystems and Using these modern techniques, post-route PPA estimations
correlating them with the post-route performance and power can be made faster and more accurate simultaneously. In a
when the same design runs on FPGA. very recent work [99] (August 2023), the Large Language
Model (LLM) has been used to generate Verilog code based
E. SUMMARY AND FUTURE DIRECTIONS on design description in pure English language. These codes
In Table 5, we have summarized the works done to predict can be synthesized on both FPGA and ASIC design tools.
FPGA designs’ PPA using analytical methods and ML-based In another work, the authors present their work, which, for
models. Most of the work discussed in Table 5 predicts the first time, shows how to generate hardware security
the post-route behavior of HLS designs. Models like XPPE, properties using LLMs automatically. They created their
‘‘Fast and Accurate’’ and Pyramid [22], [23], [25] rely on own BERT model, Hardware security-BERT, which can read
post-C-synthesis log files to extract features; hence they SoC design documentation and generate pertinent hardware
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security-relevant properties [100]. Even though these two

works are not directly applied to predict PPA in FPGA CAD
tools, these two are promising works to show how technology
is advancing towards LLM and other language models.

VIII. MACHINE LEARNING IN FPGA LOGICAL AND

PHYSICAL DESIGN FLOW
For decades, both FPGA and ASIC physical design has been
dominated by evolutionary algorithms like genetic algorithm, FIGURE 5. A generalized diagram of application of reinforcement
learning in physical design.
simulated annealing, and gradient descent algorithms [101],
[102], [103], [104], [105], [106], [107]. More recently, features from the post-synthesized netlist. They used a
these heuristic-based algorithms are replaced by analytical gradient boost algorithm to train their regression model.
solvers for improved timing [74], [75], [108], [109], [110]. However, they created the labels from the post-mapped
Similarly, most routing algorithms use either heuristic-based netlist, not from the post-placed or post-route stage. However,
or analytical methods [103], [104], [111], [112], [113], this work is after the synthesis stage, right before mapping.
[114]. But similar to any other EDA algorithms discussed There are few works in which RL is applied in Synthesis.
previously, the analytical and heuristic-based methods are In [121], Zhou and Anderson combined RL with ABC
very slow for large designs, taking days to run one design. synthesis [122] to design a RL-guided synthesis optimization.
A few works [115], [116], [117], [118] improve the runtime They used eight different optimization parameters provided
by invoking simulated annealing in multiple CPUs and GPUs. by resyn2 script to define their action state space, and
However, this work needs a very large runtime to converge the reward function is calculated as the difference between
a solution. To improve the runtime of simulated annealing the number of LUTs in the current state and the initial
or analytical methods, the researchers accelerate the SA state (first stage). Among other RL-based synthesis works,
or analytical placement using reinforcement learning (RL). Zhu et al. [123] propose the use of a graph convolutional
Kamakoti and Bhatia’s work [119] was one of the first works network on a circuit AIG (And-inverter-graph) to leverage
in which RL is combined with a Support Vector Machine graph structural information for an RL agent to select which
(SVM) to speed up the FPGA place and route process. optimization commands to use. The action space of [123] is
Recently, researchers combined heuristics and reinforcement very similar to [121] based on ABC resyn2. Drills [124]
learning (RL) in FPGA placement stage [56], [57], [58], [59]. is an RL-based design space explorer in the synthesis space
In [120], the authors used a convolution neural network to where they used advantage actor-critic (A2C) to guide their
improve placement, while RL has been applied to synthesis RL agent. The reward function used in this work is to find a
and routing in [61] and [121] respectively. In this section, minimum design area subject to delay constraints.
we will discuss how ML is applied to the three crucial
stages of FPGA physical design flow viz., (i) Synthesis, (ii) B. MACHINE LEARNING IN FPGA PLACEMENT
Placement, and (iii) Routing. In Fig. 5, we have shown a
Reinforcement learning has been widely used either stan-
high-level common flow of how RL is applied in different
dalone [60] or in combination with metaheuristic algorithms
FPGA/ASIC physical design stages. In RL-based IC design,
like simulated annealing [56], [57], [58], [59]. Most of these
a vector of performance features represents the state of
works use VTR [125] as their base placement algorithm
a circuit. The RL agent takes this vector as the input,
and use RL to guide the annealer. In [56], Elgammal et al.
executes an action by changing the design parameter values,
combines simulated annealing (SA) with reinforcement
computes the reward, and then moves to the new state (S(t+1) )
learning. In SA, all the moves may not always result in
(Fig. 5), if the reward has increased, else it explores different
improved timing or wirelength. The authors want their
available actions otherwise. The reward is computed from the
algorithm to ‘‘learn’’ the most effective perturbations using
EDA environment results like simulated annealing or genetic
reinforcement learning RL. The RLPlace algorithm uses
algorithm (shown in the top box of Fig. 5) [44]. Most works
seven directed moves to optimize both wirelength and critical
discussed in this section use a variant of the flow shown in
path delay. Here, RL guides the annealer to select the most
Fig. 5.
effective moves throughout the placement to explore large
placement solution space and achieve high-quality results
A. MACHINE LEARNING IN FPGA SYNTHESIS quickly. This work [57] is very similar to [56] with several
ML has not been widely applied in the Synthesis or mapping moves less than [56]. The proposed algorithm (directed
stage of FPGA physical synthesis since these stages are too moves + RL) explores the solution space more efficiently
early to predict QoR down the flow. In [50], the authors than traditional random moves, yielding better QoR for all
proposed a methodology to predict the timing characteristics tested designs. [58] is a precursor to [56] and [57] by Betz
of a circuit right after the technology mapping stage. Similar and his team. In [58], the authors combine SA and RL to
to [51] discussed in Section VII, in [50], the authors extracted guide the placement algorithm. But unlike [56] and [57],

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only one state is used to guide the agent instead of using TABLE 6. Summary of ML based physical design tools.
two state spaces at different temperatures of SA annealing.
Also, in [56] and [57], seven directed moves were used for
the annealer. In [58], only one move is selected: the Random
Move in [56]. Here, they guide the RL agent based on four
resource types in place of moves. Reference [59] is quite
similar to [56], [57], and [60]. Here also, the authors applied
RL to optimize moves of SA-based placer in VTR [101],
[125]. But the details of the moves are not discussed in the may include generative AI like GAN, which will generate
work, nor are the results shown very prominently here. the placed circuit based on description like the requirement
In this paper [60], Malappa et al. applied RL in the detailed for timing and area. Just like GAN is used to create virtual
placement stage. They addressed the detailed placement congestion in [40] and [41], GAN can also be used for routing
problem as two staged hierarchical problems: (i) Coarse- on the placed circuit in the future. In Table 6, we classified
grained refinement and (ii) Fine-grained refinement. They the three stages of physical design and what are the ML
applied RL in Stage 1 to select the optimal sliding window algorithms applied in each stage.
size and the order in which the sliding windows must
be rearranged. In Stage 2, Satisfiability Modulo Theories IX. CONCLUSION
(SMT) are applied for fine-grain refinement. This work is ML is a growing field in the current technology domain,
purely RL-based, and they did not combine with any meta- with many applications in computer vision, image processing,
heuristics-based methods like SA or Genetic Algorithm. audio and video processing, NLP, etc. This field is currently
In [120], the authors addressed the placement problem as a being applied in the EDA domain. CAD-based IC design
CNN problem based on electrostatic density. The authors pro- technology has been there since the 1980s, and we have
posed a CNN-inspired analytical global placement algorithm lots and lots of data available at various stages of the
for large-scale FPGAs. A novel density framework was physical design flow for various technology nodes. If we
constructed to remedy the high computation time by casting can utilize the data from past IC designs for ASIC and
the 2D electrostatic-based density constraints into CNN. This FPGA, we can make great tools using ML, resulting in fast
first and one of the only known works where CNN has been IC design tools. Another challenge of ML-based IC design
directly applied to the placement problem. tools is the availability of specialists. The designer must have
exceptionally good knowledge of VLSI design flow and ML
C. MACHINE LEARNING IN FPGA ROUTING technologies. As discussed in this chapter, almost all the
Although ML has been widely applied to predict congestion, available ML algorithms are now being applied in EDA tool
routing violations, or DRC violations in routing, as discussed design. However, most of the work discussed in this paper
in Section IV, very few works are where ML is directly is still nascent in academic labs, and commercially making
applied to guide the routing algorithm. RL has been applied them available with vendor-supplied tools may take some
to optimize the routing algorithm in one such work. In [61], time. Two recent tools from AMD Xilinx Vitis AI [126] and
the authors applied RL to optimize the routing algorithm and Synopsys DSO [127] use ML as part of their implementation
compared it against the conventional negotiated congestion algorithms.
routing method used in Pathfinder [111] routing algorithm.
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pp. 2330–2342, Dec. 2019. IEEE) received the B.Tech. degree in electron-
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design on heterogeneous FPGA (abstract only),’’ in Proc. ACM/SIGDA University, India, in 2012, and the M.S. and
Int. Symp. Field-Program. Gate Arrays, Feb. 2016, p. 275. Ph.D. degrees in electrical engineering from The
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for large-scale heterogeneous FPGAs,’’ in Proc. IEEE/ACM Int. Conf. respectively. He is currently a Software Engineer
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E. F. Y. Young, and B. Yu, ‘‘RippleFPGA: A routability-driven placement
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FPGAs.
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High-performance analytical mixed-size placer for FPGA,’’ in Proc. received the bachelor’s degree in electrical engi-
IEEE/ACM Int. Conf. Comput. Aided Design (ICCAD), Nov. 2021,
neering from the Regional Engineering College,
pp. 1–9.
Suratkal, India, in 1985, and the master’s and
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Ph.D. degrees in computer science from The
performance-driven router for FPGAs,’’ in Proc. 3rd Int. ACM Symp.
University of Texas at Dallas, TX, USA, in
Field-Program. Gate Arrays, Feb. 1995, pp. 111–117.
1987 and 1990, respectively. He is currently a
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Faculty Member with the Erik Jonsson School
intra-CLB rerouting,’’ in Proc. 28th Asia South Pacific Design Autom.
Conf. (ASP-DAC), Jan. 2023, pp. 529–534. of Engineering and Computer Science, The
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University of Texas at Dallas, where he directs
FPGA router,’’ in Proc. 25th Asia South Pacific Design Autom. Conf. research activities within the IDEA Laboratory. He has served on
(ASP-DAC), Jan. 2020, pp. 338–344. technical program committees of several international conferences related to
[114] M. Shen and G. Luo, ‘‘Corolla: GPU-accelerated FPGA routing based on field-programmable gate arrays (FPGAs), field-programmable technology,
subgraph dynamic expansion,’’ in Proc. ACM/SIGDA Int. Symp. Field- and system-level design using FPGAs. His research interests include system-
Program. Gate Arrays, Feb. 2017, pp. 105–114. level design, power and energy systems, and architecture and computer-aided
[115] Y. Lin, S. Dhar, W. Li, H. Ren, B. Khailany, and D. Z. Pan, design for FPGAs. He has served on the Editorial Board of the IEEE
‘‘DREAMPIace: Deep learning toolkit-enabled GPU acceleration for TRANSACTIONS ON COMPUTERS. He was a Distinguished Lecturer of the IEEE
modern VLSI placement,’’ in Proc. 56th ACM/IEEE Design Autom. Conf. Circuits and Systems Society, from 2007 to 2008.
(DAC), Jun. 2019, pp. 1–6.

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