a CDMA 3 V Transmitter IF Subsystem

with Integrated Voltage Regulator

AD6122
FEATURES range IF amplifiers with voltage-controlled gain and a power-
Fully Compliant with IS98A and PCS Specifications down control input. An integral low dropout regulator allows
Linear IF Amplifier operation from battery voltages from 2.9 V to 4.2 V.
–63 dB to +34 dB The gain control input accepts an external gain control voltage
Linear-in-dB Gain Control input from a DAC. It provides 97 dB of gain control with a
Temperature-Compensated Gain Control nominal 75 dB/V scale factor. Either an internal or an external
Quadrature Modulator reference may be used to set the gain-control scale factor.
Modulates IFs from 50 MHz to 350 MHz
Integral Low Dropout Regulator The I and Q modulator accepts differential quadrature base-
Accepts 2.9 V to 4.2 V Input from Battery band inputs from a CDMA baseband converter. The local oscil-
Low Power lator is injected at twice the IF frequency. A divide-by-two
10.4 mA at Midgain quadrature generator followed by dual polyphase filters ensures
<10 ␮A Sleep Mode Operation ± 1° quadrature accuracy.
Companion Receiver IF Chip Available (AD6121) The modulator provides a common-mode reference output to
bias the transmit DACs in the baseband converter to the same
APPLICATIONS
common-mode voltage as the modulator inputs, allowing dc
CDMA, W-CDMA, AMPS and TACS Operation
coupling between the two ICs and thus eliminating the need to
QPSK Transmitters
charge and discharge coupling capacitors. This allows the fastest
power-up and power-down times for the AD6122 and CDMA
GENERAL DESCRIPTION baseband ICs.
The AD6122 is a low power IF transmitter subsystem, specifi-
The AD6122 is fabricated using a 25 GHz f t silicon BiCMOS
cally designed for CDMA applications. It consists of an I and Q
process and is packaged in a 28-lead SSOP and a 32-leadless
modulator, a divide-by-two quadrature generator, high dynamic
LPCC chip scale package (5 mm × 5 mm).

FUNCTIONAL BLOCK DIAGRAM

VCC

QUADRATURE
MODULATOR IF AMPLIFIER
OUTPUT ATTENUATOR INPUT

QUADRATURE MODULATOR

I INPUT
IF AMPLIFIERS
LOCAL TRANSMIT
OSCILLATOR ⴜ2 OUTPUT
INPUT

Q INPUT AD6122
COMMON-MODE
REFERENCE
OUTPUT GAIN
CONTROL
VPOS VREG SCALE TEMPERATURE
LOW
FACTOR COMPENSATION
DROPOUT
REGULATOR

POWER- POWER-
DOWN 1 DOWN 2 1.23 V GAIN CONTROL GAIN CONTROL
REFERENCE REFERENCE VOLTAGE
OUTPUT VOLTAGE INPUT
INPUT

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD6122–SPECIFICATIONS (T = +25ⴗC, V
noted) NOTE: All powers shown in dBm are referred to 1 k⍀.
A CC = +3.0 V, LO = 2 ⴛ IF, REFIN = 1.23 V, LDO Enabled, unless otherwise

Specification Conditions Min Typ Max Unit

MODULATOR LO = 260.76 MHz (2 × IF), 100 mV p-p
500 mV p-p Differential I and Q Inputs;
Output Level Output Level Referred to a 1 kΩ Differential Load –21 dBm
Output Third Order Harmonic –50 dBc
I/Q Inputs
Differential Input Voltage Differential 500 mV p-p
Bandwidth –3 dB 20 MHz
Resistance 30 kΩ
Quadrature Accuracy ±1 °
Amplitude Balance ± 0.1 dB
Output Referred Noise 0.9 MHz to 5.0 MHz Offsets –169 dBm/Hz
Modulator Common-Mode Reference 1.408 V
LO Input Resistance Differential Input at 260.38 MHz 1.2 kΩ
LO Input Capacitance Differential Input at 260.38 MHz 2.4 pF
LO Carrier Leakage Bias I/Q Using MODCMREF –40 dBc
IF AMPLIFIER FIF = 130.38 MHz
Noise Figure VGAIN = 2.5 V, 1 kΩ Differential Load 10 dB
Input 1 dB Compression Point VGAIN = 2.5 V –32 dBm
Input Third-Order Intercept VGAIN = 2.5 V –24 dBm
Gain Flatness IF ± 630 kHz ± 0.25 dB
Input Capacitance Shunt Equivalent Model at 130.38 MHz 2.3 pF
Differential IF Input Resistance Shunt Equivalent Model at 130.38 MHz 680 Ω
Differential IF Output Resistance Per Pin at 130.38 MHz 4.2 kΩ
Differential IF Output Capacitance Per Pin at 130.38 MHz 2.0 pF
GAIN CONTROL INTERFACE
Gain Scaling Using Internal Reference 75 dB/V
Gain Scaling Linearity For a Typical Dynamic Range of 92 dB ±3 dB/V
Minimum Gain VGAIN = 0.5 V –63 dB
Maximum Gain VGAIN = 2.5 V +34 dB
Gain Control Response Time 90 dB Gain Change, Min Gain to Max Gain 0.7 µs
Input Resistance at REFIN 10 MΩ
Input Resistance at VGAIN 109 kΩ
POWER-DOWN INTERFACE
Logic Threshold High Power-Up on Logical High 1.34 V
Logic Threshold Low 1.30 V
Input Current for Logical High 0.1 µA
Turn-On Response Time Measure to Settling of AGC from Standby Mode 23 µs
Turn-Off Response Time To 200 µA Supply Current 187 ns
LOW DROPOUT REGULATOR External PNP Pass Transistor, VCE SAT = –0.4 V
Max, hFE = 100/300 Min/Max
Input Range 2.9–4.2 V
Nominal Output 2.70 V
Dropout Voltage 200 mV
Reference Output 1.23 V
POWER SUPPLY
Supply Range Bypassing Internal LDO 2.7–5.0 V
Supply Current VGAIN = 1.5 V (Unity Gain) 10.4 mA
Standby Current 7.8 µA
OPERATING TEMPERATURE
TMIN to TMAX –40 +85 °C
Specifications subject to change without notice.

–2– REV. B
 AD6122
ABSOLUTE MAXIMUM RATINGS 1 NOTES
1
Supply Voltage DVCC, IFVCC, TXVCC to DGND, Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
IFGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5 V device at these or any other conditions above those indicated in the operational
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 600 mW section of this specification is not implied. Exposure to absolute maximum rating
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C conditions for extended periods may affect device reliability.
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 2
Thermal Characteristics: 28-lead SSOP Package: θJA = 115.25°C/W.
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

PIN CONFIGURATIONS

SSOP Package LPCC Package

REFOUT
VGAIN
REFIN

IFVCC
LDOE
PD1 1 28 VGAIN

PD2
PD1

NC
PD2 2 27 REFIN

LDOE 3 26 REFOUT
32 31 30 29 28 27 26 25

LDOB 4 25 IFVCC LDOB 1 24 IFGND

LDOC 5 24 IFGND LDOC 2 23 IFGND

LDOGND 6 23 IIPP LDOGND 3 22 IIPP

AD6122
DGND 7 TOP VIEW 22 IIPN LDOGND 4 AD6122 Top View 21 IIPN
LOIPP 8 (Not to Scale) 21 MODCMREF DGND 5 (Not to Scale) 20 MODCMREF
LOIPN 9 20 QIPN LOIPP 6 19 QIPN
DVCC 10 19 QIPP LOIPN 7 18 QIPP
TXOPP 11 18 MODOPP
17 MODOPP
DVCC 8
TXOPN 12 17 MODOPN
9 10 11 12 13 14 15 16
TXVCC 13 16 IFINP
TXOPP

TXOPN

TXVCC
IFGND
IFGND
IFINN

IFINP

MODOPN
IFGND 14 15 IFINN

NC = NO CONNECT

ORDERING GUIDE

Temperature Package
Model Range Package Description Option
AD6122ARS –40°C to +85°C Shrink Small Outline Package (SSOP) RS-28
AD6122ARSRL –40°C to +85°C 28-Lead SSOP on Tape-and-Reel
AD6122ACP –40°C to +85°C Chip Scale Package (LPCC) CP-32
AD6122ACPRL –40°C to +85°C 32-Leadless LPCC on Tape-and-Reel

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD6122 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B –3–
AD6122
PIN FUNCTION DESCRIPTIONS

SSOP LPCC
Pin # Pin # Pin Label Description Function
1 30 PD1 Power-Down 1 IF Amplifier Power-Down Control Input; CMOS Com-
patible; HIGH = Entire IC Powers Down, LOW = IF
Amplifiers On.
2 31 PD2 Power-Down 2 Modulator Power-Down Control Input; CMOS Compat-
ible; HIGH = Modulator Off , LOW = Modulator On.
3 32 LDOE Low Dropout Regulator Pass Connects to Emitter of External PNP Pass Transistor
Transistor Emitter Connection and VCC.
4 1 LDOB Low Dropout Regulator Pass Connects to Base of External PNP Pass Transistor.
Transistor Base
5 2 LDOC Low Dropout Regulator Pass Connects to Collector of External PNP Pass Transistor.
Transistor Collector
6 3, 4 LDOGND Low Dropout Regulator Ground Ground.
7 5 DGND Digital Ground Ground.
8 6 LOIPP Local Oscillator “Positive” Input Connects to Local Oscillator; AC Coupled.
9 7 LOIPN Local Oscillator “Negative” Input Connects to Ground via Decoupling Capacitor.
10 8 DVCC Digital VCC Connects to Digital Supply.
11 9 TXOPP Transmit Output “Positive” Connects to Output Filter; AC Coupled.
12 10 TXOPN Transmit Output “Negative” Connects to Output Filter; AC Coupled.
13 11 TXVCC Transmit Output VCC Connects to LDO Output via Decoupling Network.
14 12, 13 IFGND IF Ground Ground.
15 14 IFINN IF Input “Negative” IF “Negative” Input from LC Roofing Filter.
16 15 IFINP IF Input “Positive” IF “Positive” Input from LC Roofing Filter.
17 16 MODOPN Modulator “Negative” If Output Output Modulator Output to LC Roofing Filter.
18 17 MODOPP Modulator “Positive” Output Modulator Output to LC Roofing Filter.
19 18 QIPP Q Input “Positive” Connects to Q “Positive” Output of Baseband IC.
20 19 QIPN Q Input “Negative” Connects to Q “Negative” Output of Baseband IC.
21 20 MODCMREF Modulator Common-Mode Connects to CDMA Baseband Converter Tx DAC
Reference Out Common-Mode Reference Input.
22 21 IIPN I Input “Negative” Connects to I “Negative” Output of Baseband IC.
23 22 IIPP I Input “Positive” Connects to I “Positive” Output of Baseband IC.
24 23, 24 IFGND Ground Connects to IF Ground.
25 NC No Connect
25 26 IFVCC IF VCC Connects to Decoupled Output of LDO Regulator.
26 27 REFOUT Gain Control Reference Output Provides 1.23 V Voltage Reference Output for DAC in
CDMA Baseband Converter and REFIN.
27 28 REFIN Gain Control Reference Input Accepts 1.23 V Reference Input from REFOUT or
External Reference.
28 29 VGAIN Gain Control Voltage Input Accepts Gain Control Input Voltage from External DAC.
Max Gain = 2.5 V; Min Gain = 0.5 V.

–4– REV. B
 AD6122
Test Figures
0.1␮F
+15V
8
1 X1 VP
MUST BE EQUAL 2 X2 V–1 OUT
LENGTHS 7
A=1 IIPP
3 Y1
MODCMREF 50⍀
4 Y2 V–1 AD830
VN
5 AD6122
–15V
I DATA 0.1␮F
50⍀
0.1␮F
+15V
8
1 X1 VP

2 X2 V–1 OUT
7
A=1 IIPN
3 Y1 50⍀
MODCMREF
4 Y2 V–1 AD830 VREG OUT
VN
5
–15V 0.1␮F
0.1␮F
450⍀
MODOPP MOD_OUT
0.1␮F 10nF 205⍀
+15V
8 MODOPN
VP 10nF 450⍀
1 X1
MUST BE EQUAL 2 X2 V–1 OUT
LENGTHS 7
A=1 QIPP
3 Y1 0.1␮F
MODCMREF 50⍀
4 Y2 V–1 AD830 VREG OUT
VN
5
–15V
Q DATA 0.1␮F
50⍀
0.1␮F
+15V
8
1 X1 VP
MODCMREF
2 X2 V–1 OUT
7
A=1 QIPN
3 Y1
MODCMREF 50⍀
4 Y2 V–1 AD830
VN
5
–15V
0.1␮F
LOIPP LOIPN

LO INPUT

Figure 1. Quadrature Modulator’s Characterization Input and Output Impedance Matches

REV. B –5–
AD6122
VREG OUT
PULL-UP INDUCTORS CHOSEN
FOR PEAK RESPONSE AT THE
TEST FREQUENCY. 0.1␮F

1:8 383⍀ IFINP TXOPP 453⍀ 4:1 TO

RF SOURCE SPECTRUM
10nF 10nF ANALYZER
511⍀ 205⍀
IFINN
383⍀ TXOPN 453⍀
10nF 10nF
AD6122

0.1␮F
VREG OUT

Figure 2. IF Amplifier’s Characterization Input and Output Impedance Matches

NOTE: RF CABLES FOR I AND Q PATHS MUST BE OF EQUAL LENGTH

TEST BED MOTHERBOARD

R&S FSEA20/30
I DATA SPECTRUM
I CHANNEL
TEKTRONIX RF ANALYZER
500mVp-p DIFFERENTIAL MOD OUT INPUT
AFG2002
Q CHANNEL
Q DATA
AUX MEAS
IFTX OUT
R&S LO INPUT PORT
SMT03
RF
RF SOURCE 1 IF IN

TO RF SWITCHES

R&S HP34970A
SMT03 DATA ACQUISITION
RF & SWITCH CONTROL
RF SOURCE 2 HPE3610
POWER SUPPLY DC MEASUREMENTS
& CONTROL BITS

Figure 3. General Test Set

–6– REV. B
 AD6122
VREG OUT
PULL-UP INDUCTORS CHOSEN
FOR PEAK RESPONSE AT THE
0.1␮F
TEST FREQUENCY.

REACTIVE 1:8 IFINP TXOPP 453⍀ 4:1 TO NOISE

NOISE
CONJUGATE FILTER
SOURCE
MATCH 10nF 10nF 205⍀ METER
IFINN
TXOPN 453⍀
10nF 10nF
AD6122

0.1␮F
VREG OUT

Figure 4. IF Amplifier’s Noise Figure Test Set

HP8116A HP8116A
FUNCTION GEN. ROHDE & SCHWARZ FUNCTION GEN. ROHDE & SCHWARZ
SMT03 SMT03
4 kHz, 0.5V TO 2.5V 4kHz, 0V TO 2.7V
SQ. WAVE 100MHz, –30dBm SQ. WAVE 100kHz, –30dBm

AGC IFIN TEKTRONIX TDS 744A PD1, IFIN TEKTRONIX TDS 744A
PD2
CH 1 WITH X10 PROBE CH 1 WITH X10 PROBE

IFOUT CH 2 WITH COAX CABLE IFOUT CH 2 WITH COAX CABLE

50⍀ 50⍀
AD6122 TEST BED AD6122 TEST BED

a. Response Time from Gain Control to IF Output b. Response Time from PD1 and PD2 Control to IF Output

Figure 5. Response Time Setup

REV. B –7–
AD6122 –Typical Performance Characteristics
RBW 30kHz
REF LEV VBW 100kHz
–40dBm SWT 2s UNIT dBm
–40 –30
1 1 (T1) –49.18dBm A
–50 130.67458918MHz
CH PWR –33.92dBm
ACP UP –77.32dB
–60 AVE LOW 77.46dB

UNDESIRED SIDEBAND – dBc

–70 –35
POWER – dBm

–80

–90

–100
–40
–110

–120 CL1
CU1
–130

–140 –45
50 100 150 200 250 300 350
CENTER 130.38MHz 519kHz/DIV SPAN 5.19MHz
OUTPUT FREQUENCY – MHz

Figure 6. Spectral Plot at Modulator Outputs: ACPR Figure 9. Modulator Output Undesired Sideband vs.
Output Frequency

–35 –10
MODULATOR OUTPUT – dBm REFERRED

–15
TO A 1k⍀ DIFFERENTIAL LOAD
LO LEAKAGE – dBc

–40
–20

–25
–45

–30

–50 –35
50 100 150 200 250 300 350 –14.0 –12.0 –10.0 –8.0 –6.0 –4.0 –2.0
FREQUENCY – MHz MODULATOR, I = Q – dBV

Figure 7. Modulator LO Leakage vs. Output Frequency Figure 10. Modulator Gain: Input (dBV) vs. Output (dBm)

–15 –45
OUTPUT DESIRED SIDEBAND LEVEL –

–20
–50
THIRD HARMONIC – dBc
dBm REFERRED TO 1k⍀

–25

–55

–30

–60
–35

–40 –65
50 100 150 200 250 300 350 50 100 150 200 250 300 350
OUTPUT FREQUENCY – MHz OUTPUT FREQUENCY – MHz

Figure 8. Modulator Output Desired Sideband vs. Figure 11. Modulator Third Harmonic
Output Frequency Without Roofing Filter

–8– REV. B
 AD6122
40 –24

20
GAIN – dB With a 1k⍀ Load

–25

IIP3 – dBm Referred to 1k⍀

0

TA = –40ⴗC
–20 –26

TA = +85ⴗC
–40

–27
–60

TA = +25ⴗC
–80 –28
0.5 1.0 1.5 2.0 2.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7
VGAIN – V SUPPLY VOLTAGE – V

Figure 12. IF Amplifier Response Curve: Gain vs. Figure 15. IF Amplifier Input IP3 vs. Supply Voltage
VGAIN, TA = –40 °C, +25 °C, +85 °C

45 6.0 –23

35 5.0
ERROR FROM PREDICTED VALVE – dB

25 4.0
15 3.0
GAIN ERROR

IIP3 – dBm Referred to 1k⍀

5 2.0 –24
GAIN – dB

–5 1.0

–15 0

–25 –1.0

–35 –2.0 –25

GAIN
–45 –3.0

–55 –4.0

–65 –5.0

–75 –6.0 –26

0.5 0.9 1.3 1.7 2.1 2.5 50 100 150 200 250 300 350
VGAIN – V FREQUENCY – MHz

Figure 13. IF Amplifier Gain and Error vs. VGAIN Figure 16. IF Amplifier Input IP3 vs. Frequency

5.0 30.0

0
25.0
IIP3 – dBm Referred to 1k⍀

NOISE FIGURE – dB

–5.0
20.0
133MHz
–10.0 313MHz

15.0
–15.0 238MHz

10.0
–20.0

–25.0 5.0
0.5 0.9 1.3 1.7 2.1 2.5 –10.0 0 10.0 20.0 30.0 40.0
VGAIN – V GAIN – dB

Figure 14. IF Amplifier Input IP3 vs. VGAIN Figure 17. IF Amplifier Noise Figure vs. Gain

REV. B –9–
AD6122
40 18.0

TOTAL CURRENT CONSUMPTION – mA

VGAIN = 2.5V
20
16.0
VGAIN = 2.0V

0
14.0
GAIN – dB

–20 VGAIN = 1.5V

12.0
–40

VGAIN = 1.0V
10.0
–60

VGAIN = 0.5V
–80 8.0
50 100 150 200 250 300 350 0.5 1.0 1.5 2.0 2.5
FREQUENCY – MHz VGAIN – V

Figure 18. IF Amplifier Gain vs. Frequency for Figure 19. Total Current Consumption vs. VGAIN
VGAIN = 2.5 V, 2.0 V, 1.5 V, 1.0 V

RBW 30kHz
REF LEV VBW 300kHz
–30dBm SWT 2s UNIT dBm
–30
1 (T1) –46.78dBm A
–40 130.38000000MHz
1 CH PWR –31.93dBm
1
ACP UP –66.95dB
–50
AVE LOW –68.95dB
1 (T1) –0.28 dB
–60 330.66132265kHz
POWER – dBm

–70

–80

–90

–100

–110 CL1
CO CO CU1
–120

–130
CENTER 130.38MHz 600kHz/DIV SPAN 6MHz

Figure 20. ACPR of Cascaded Modulator, 20 dB Pad and IF

Amplifier: Spectral Plot

–10– REV. B
 AD6122
VCC

QUADRATURE
MODULATOR IF AMPLIFIER
OUTPUT ATTENUATOR INPUT

QUADRATURE MODULATOR

I INPUT
IF AMPLIFIERS
LOCAL TRANSMIT
OSCILLATOR ⴜ2 OUTPUT
INPUT

Q INPUT AD6122
COMMON-MODE
REFERENCE
OUTPUT GAIN
CONTROL TEMPERATURE
VPOS SCALE COMPENSATION
LOW VREG FACTOR
DROPOUT
REGULATOR

POWER- POWER- GAIN CONTROL

DOWN 1 DOWN 2 1.23 V GAIN CONTROL VOLTAGE
REFERENCE REFERENCE INPUT
OUTPUT VOLTAGE
INPUT

Figure 21. Block Diagram

THEORY OF OPERATION IF Amplifiers and Gain Control

The CDMA Transmitter IF Subsystem (Figure 21) consists of The IF amplifiers provide an 86 dB linear in dB gain control
an I and Q modulator with a divide-by-two quadrature genera- range. The input stage uses a differential, continuously variable
tor, high dynamic range IF amplifiers with voltage-controlled attenuator based on Analog Devices’ patented X-AMP™ topol-
gain, a low dropout regulator and power-down control inputs. ogy. This low noise attenuator consists of a differential R-2R
I and Q Modulator ladder network, linear interpolator and a fixed gain amplifier.
The I and Q modulator accepts differential quadrature baseband The IF amplifier’s input impedance is 1 kΩ differential. Similar
inputs from CDMA baseband converters. The LO is injected at to the I and Q modulator’s output, the IF amplifier’s output is a
twice the IF frequency. A divide-by-two quadrature generator differential current, which will vary depending upon the gain
followed by dual polyphase filters ensures ± 1° quadrature accu- control voltage. In order to achieve the specified gain, the out-
racy (Figure 22). put of the IF amplifiers should be loaded with a 1 kΩ differen-
tial load.
For 500 mV p-p differential I and Q input signals, the output
power of the modulator will be –21 dBm referred to 1 kΩ when The gain control circuits contain both temperature compensa-
the output of the modulator is loaded with a 1 kΩ differential tion circuitry and a choice of internal or external reference for
load. With the maximum input conditions stated above, the adjusting the gain scale factor. The gain control input accepts
modulator outputs are a 225 µA p-p differential current; conse- an external gain control voltage input from a DAC. It provides
quently, the output load will greatly affect the output power of 97 dB of gain control range with a nominal 75 dB/V scale factor.
the modulator. The external gain control input signal should be a clean signal.
It is recommended to filter this signal in order to eliminate the
I
noise that results from the DAC. If a noisy signal is used for the
2 ⴛ IF ⴜ2
LO INPUT
I gain control voltage, VGAIN inband and adjacent channel noise
POLYPHASE
QUADRATURE peaking can occur at the output of the AD6122. A simple RC
OUTPUT TO
FILTERS
MODULATOR filter can be employed, but care should be taken with its design.
Q If too big a resistor is used, a large voltage drop may occur
180ⴗ ⴜ2 Q
across the resistor, resulting in lower gain than expected (as a
Figure 22. Simplified Quadrature Generator Circuit result of a lower voltage reaching the AD6122). An RC filter
with a 20 kHz bandwidth, employing a 1 kΩ resistor is appropri-
The I and Q modulator also provides a common mode reference ate. This results in an 8.2 nF capacitor. The resulting circuit
signal at the MODCMREF pin. This voltage is a dc voltage set is shown in Figure 23. Note that the input resistance at the
to 1.408 V when a 2.7 V supply is used. It is used to dc bias VGAIN pin is approximately 100 kΩ.
the output of the DAC that provides I and Q inputs to the
modulator. FROM
AD6122
1k⍀
BASEBAND VGAIN
CONVERTER 8.2nF 109k⍀

Figure 23. Gain Voltage Filtering

X-AMP is a trademark of Analog Devices, Inc.
REV. B –11–
AD6122
The AD6122’s overall gain, expressed in decibels, is linear in up. The control is provided via two control pins, PD1 and PD2.
dB with respect to the automatic gain control (AGC) voltage, Table I shows the operating modes of the AD6122.
VGAIN. Either REFOUT or an external reference voltage con-
nected to REFIN may be used to set the voltage range for VGAIN. Table I. Operating Modes
When the internal 1.23 V reference, REFOUT, is connected to
REFIN , VGAIN will control the entire AGC range when it is PD1 PD2 IF Amp Modulator
typically set between 0.5 V and 2.5 V. Minimum gain occurs at 0 0 ON ON
minimum voltage on VGAIN and maximum gain occurs at maxi- 0 1 ON OFF
mum voltage on VGAIN. The maximum and minimum gain 1 0 INVALID STATE INVALID STATE
will not change with a change in voltage at REFIN. Rather, the 1 1 OFF OFF
slope of the gain curve will change as a result of a change in the
required range for VGAIN. Figure 24 shows the piecewise linear Low Dropout Regulator
approximation of the gain curve for the AD6122. The AD6122 incorporates an integrated low dropout regulator.
The regulator accepts inputs from 2.9 V to 4.2 V and supplies a
constant 2.7 V reference output at LDOC. The 2.7 V signal can
MAXIMUM be used to provide the dc voltages required for the DVCC,
GAIN
TXVCC and IFVCC dc supplies. In order to configure the low
dropout regulator, an external pass transistor is required. A pnp
GAIN – V/V

bipolar junction transistor with a minimum hFE of 100 and a

maximum hFE of 300 and a VCESAT of –0.4 V is required. In
order to use the low dropout regulator, configure the transistor as
shown in Figure 25. The 18 pF capacitor in Figure 25 is used for
MINIMUM
GAIN decoupling the 2.7 V dc signal.
In addition to the low dropout regulator, a band-gap voltage
VGAIN – V
reference produces a 1.23 V reference voltage at REFOUT.
This reference voltage will be present whenever a 2.7 V dc sig-
Figure 24. Piecewise Linear Approximation for the nal is present on pin LDOC. This 1.23 V reference voltage can
AD6122 Gain Curve then be used to provide the gain reference signal required for
Because the minimum and maximum gain from the AD6122 REFIN and the reference voltage for the transmit DACs in a
are constant, we can approximate the VGAIN range for a baseband converter.
given REFIN voltage by using Equation 1.
(GAIN – MinGain) × 1.6REFIN AD6122
VGAIN = + 0.4 REFIN (1)
MaxGain – MinGain 2.9V – 4.2V LDOE

Where MaxGain is the maximum gain (+34 dB) in dB, MinGain PASS
is the minimum gain (–63 dB) in dB, REFIN is the reference TRANSISTOR LDOB

input voltage, in volts, VGAIN is the gain control voltage input,

2.7V LDOC
in volts, and GAIN is the particular gain, in dB, we would have
18pF
for a given REFIN and VGAIN. Consequently, for any REFIN
we choose, we can calculate the VGAIN range by solving REFOUT 1.23V

Equation 1 for VGAIN. For example, in order to determine the

VGAIN value for the maximum gain condition, given a 1.23 V
REFIN, we can solve Equation 1 for VGAIN by substituting Figure 25. Configuring the Low Dropout Regulator
+34 dB for GAIN and MaxGain, –63 dB for MinGain and 1.23 V It is possible to bypass the low dropout regulator on the AD6122
for REFIN. VGAIN can then be calculated to be 2.46 V, or and use an external regulator instead. In order to bypass the
approximately 2.5 V. For the minimum gain condition, we can integrated low dropout regulator, connect pins LDOE, LDOB
determine the VGAIN value by substituting 34 dB for MaxGain, and LDOC together and then connect them all to the 2.7 V
–63 dB for GAIN and MinGain and 1.23 V for REFIN. VGAIN external regulator voltage. This configuration is shown in
can then be calculated to be 0.492 V or approximately 0.5 V. Figure 26. Even when the low dropout regulator is bypassed,
Power-Down Control the 1.23 V reference voltage at pin REFOUT is still present.
The AD6122 can be operated with the IF amplifiers and quadra-
ture modulator both powered up, both powered down or with
the IF amplifiers powered up and the modulator powered down.
The AD6122 cannot operate with only the modulator powered

–12– REV. B
 AD6122
The attenuator is discussed in the next section entitled Measur-
AD6122
ing Adjacent Channel Protection Ratio (ACPR).
LDOE In order to confirm whether the roofing filter has been correctly
designed, sweep the LO frequency and view the output of the IF
FROM EXTERNAL
VOLTAGE REGULATOR
LDOB amplifier on a spectrum analyzer. The signal should peak at the
IF frequency if the inductor value is correct. The Q of the filter
LDOC should be low enough so that variations in the parasitic capaci-
tances should be negligible.
REFOUT 1.23V
The value of inductor required will be a function of the IF fre-
quency at which we are operating. The values of inductors used
during characterization at Analog Devices are shown in Table
Figure 26. Configuration for Bypassing the Low Dropout II. Because the exact value will also be a function of printed
Regulator circuit board layout, we will have to vary the value from those in
Table II to those required for our board.
ROOFING FILTER
Because the outputs of the AD6122 modulator are open collec- Table II. Roofing Filter Inductor Values
tor, the parasitic capacitances seen at the output of the modula-
tor, and inputs of the IF amplifiers, are high enough to create a Value of Roofing Filter
low-pass filter, which may attenuate the IF signal. Consequently, IF Frequency (MHz) Inductor (nH)
the parasitic capacitance must be cancelled by using external
inductors to form a parallel resonant circuit. The external in- 50–125 470
ductors and the internal parasitic capacitors form what is known 126–200 150
as the roofing filter, with the resonant frequency given by 201–275 68
Equation 2. 276–350 27

1 It should be noted that the roofing filter is only required when

f0 = (2) cascading the output from the I/Q modulator to the input of the
2 π LCPAR IF amplifiers. If we are driving into the IF amplifiers directly, no
where f0 is the IF frequency, in Hertz, CPAR is the total parasitic roofing filter is required, however, pull-up inductors are required
capacitance in Farads, and L is the value of external inductors, in order to set the dc voltage of the open collector modulator
in henrys. outputs.

The roofing filter may be composed of the pull-up inductors MEASURING ADJACENT CHANNEL POWER RATIO
required on the open collector outputs of the I and Q modula- (ACPR)
tor. This configuration is shown in Figure 27. The 10 nF ca- At maximum IF gain and specified input conditions (500 mV
pacitors are used for ac coupling. p-p baseband inputs), the output of the I/Q modulator is 11 dB
greater than the P1 dB (one dB compression point) of the IF
amplifiers. This configuration maximizes the ratio of signal to
AD6122 LO feedthrough and also maximizes the signal to noise ratio.
MODOPP Once these ratios are maximized, we can attenuate the noise,
signal and LO feedthrough without affecting the ratios. There-
2CPAR VCC
L/2 fore, attenuation is required between the I/Q modulator and the
IF amplifiers.
L/2 10nF
2CPAR
In order to determine exactly how much attenuation is required,
MODOPN PARALLEL we must recognize that ACPR is a function of the attenuation
RESONANT from the modulator outputs to the IF amplifier inputs. As a
CIRCUIT
result, in order to determine how much attenuation is required,
10nF
IFINN
we must first know how good an ACPR performance is desired.
If too much attenuation is applied, the ACPR will be very good,
but, the IF amplifier’s output power level will be low, possibly
resulting in poor signal to noise ratio and possibly requiring
IFINP
10nF ATTENUATOR additional amplification external to the AD6122.
An appropriate method that can be used to provide the correct
Figure 27. Roofing Filter Configuration amount of attenuation between the modulator outputs and the
IF amplifier inputs is a simple differential voltage divider. The
topology and its design equations are shown in Figure 28 and
Equations 3 and 4. The input impedance of the IF amplifiers is
typically 1 kΩ. As a result, if we design resistor R2 to be much
less than 1 kΩ, we can neglect the effects of the IF amplifier’s
input impedance on the attenuator.

REV. B –13–
AD6122
This circuit is very sensitive to parasitic capacitances. As a re-
AD6122 sult, extra care should be taken to ensure minimum and equal
printed circuit board transmission lines. We should also try to
MODOPP R1 IFINP keep R2 small in order to minimize the effects of printed circuit
board parasitic capacitance on loading the output of the pad.
ZIN R2 RSHUNT >>R2 In conclusion, we have to develop a system-level ACPR budget
MODOPN R1 IFINN for our radio, and from that budget determine how much ACPR
performance we desire from the AD6122. We then need to imple-
ment the appropriate attenuation network to get that ACPR
performance.
Figure 28. Pad Topology
LEVEL DIAGRAM
Figure 29 is provided to better understand the different voltage
 1  levels you can expect to see at different points of the AD6122. It
 R1 
L = 20 log  represents the voltage and power levels expected for a maximum
1 1  (3) input condition of 500 mV p-p at the I and Q modulator and
 + 
 R1 R2 / 2 maximum gain in the IF amplifiers. When trying to make these
measurements, a high impedance (10 MΩ) active FET probe
Z IN = 2R1+ R2 (4) (for example, the Tek P6204, from Tektronix) should be used to
minimize the effects of loading the circuit with the probe.
where L is the transducer loss (or loss through the pad) in dB
and ZIN is the desired input resistance in ohms. Using these In order to produce these results, the attenuator is designed to
equations, we can design the attenuator circuit to provide what- have a 1 kΩ input impedance and the output of the IF amplifiers
ever amount of attenuation we require. are loaded with 1 kΩ. The roofing filter is designed to resonate
the parasitic capacitance at the IF frequency.

MODULATORS
–41dBm
I –21dBm (REFERRED TO 1k⍀) –7dBm
(REFERRED TO 1k⍀) 25.21mV p-p (REFERRED TO 1k⍀)
500mV p-p 252.1mV p-p DIFFERENTIAL DIFFERENTIAL IF AMPLIFIERS 1.263V p-p DIFFERENTIAL
DIFFERENTIAL
MODOP IFIN TRANSMIT
LO ⴜ2
OUTPUT
VCC
100mV p-p
DIFFERENTIAL
Q
500mV p-p
DIFFERENTIAL VGAIN = 2.5V
GAIN = +34dB
1k⍀

20dB
ATTENUATOR
ZIN = 1k⍀ ZOUT = 1k⍀

Figure 29. Level Diagram

–14– REV. B
 AD6122
INPUT INTERFACES
The AD6122 interfaces to CDMA baseband converters provid-
ing either IF or baseband outputs. The baseband input is pro-
vided by direct connection of the baseband converter’s baseband
output to the baseband input of the AD6122 (Figure 30). The
IF amplifier’s gain control is provided by connection of the
transmit AGC DAC’s output on the baseband converter, through a
low-pass filter to the VGAIN pin on the AD6122.

PD1
VGAIN
TX AGC DAC
GAIN
PD2 TEMPERATURE CONTROL
COMPENSATION SCALE
REFIN
FACTOR
EXT REF IN
LDOE
VCC
LDOB REFOUT
LOW
LDOC DROPOUT
IFVCC
REGULATOR
LDOGND IFGND

IIPP
DGND I OUTPUT
Q IIPN
I OUTPUT
LOIPP MODCMREF
ⴜ2 VCM REF IN
LOIPN
I QIPN
Q OUTPUT
Q OUTPUT
DVCC QIPP
MODOPP
MODOPN
VCC
AD6122 VCC

CDMA
BASEBAND
IC

IFINP
TXOPP
TXOPN
IFINN
TXVCC

IFGND

Figure 30. Typical Connections to Baseband IC Using I and Q Inputs with SSOP Package

REV. B –15–
AD6122
AD6122 Evaluation Board The IF output port impedance match used during characteriza-
The AD6122 Evaluation Board consists of an AD6122, I/O con- tion at Analog Devices is as follows:
nectors, a 20-pin dual header, 2-pin headers and four AD830
high speed video difference amplifiers. It allows the user to
AD6122
evaluate the AD6122’s IF amplifier and modulator together or 453⍀ 4:1 50⍀
separately. Because the AD6122 may be used at any IF from 50 TXOPP
205⍀
MHz to 350 MHz, pads are provided on the LOIPP input,
TXOPN SPECTRUM
TXOP output, MODOP output and IFIP inputs to allow the 453⍀ ANALYZER
user to add matching networks. The board is configured for an
IF frequency of 130.38 MHz when shipped. There is no differ- 1k⍀
ence between the configuration of the boards with the SSOP or
LPCC package. Figure 32. IF Output Port Impedance Match Used During
Characterization at ADI
The AD830s are used to provide single-ended to differential
conversion and the appropriate phase shift for the I and Q data This is a broadband lossy output match for the 50 MHz to
input pins. As a result, a single-ended signal generator can be 350 MHz frequency range. The 4:1 ratio in Figure 32 is an
used to generate these signals. impedance ratio and not a voltage ratio.

In order to test the power-down modes of the AD6122, locate As shipped, the board is configured as follows:
the two pin headers on the AD6122 evaluation boards labeled 1. J1 is open and J2 is shorted. This enables the LDO regulator.
PD1 and PD2. By open-circuiting the pins labeled PD1, the IF The external PNP transistor should remain in place even
amplifiers power down. By open-circuiting the pins labeled when the regulator is bypassed (the Pin LDOB is pulled up
PD2, the modulator powers down. Note that the IF amplifiers by the transistor).
and modulator are powered down unless the pins on the two pin 2. X11, X25, X18 and X26 are shorted and X12, X14, X19
headers, PD1 and PD2, are short circuited. and X21 are opened in order to connect the output of the
The IF input port impedance match used during characteriza- modulator to the input of the IF amplifiers.
tion of the AD6122 at Analog Devices is as follows: 3. L4 and L5, the roofing filter components are optimized for
an IF frequency of 130.38 MHz.
AD6122 4. R14, R15 and R16 set the attenuation between the modula-
50⍀ 1:8 383⍀
IFINP tor outputs and the IF amplifier inputs to 20 dB.
511⍀
SIGNAL
5. PD1 and PD2 are pulled low by the jumpers on the two pin
IFINN
GENERATOR 383⍀ headers. To power down the chip, set PD1 and PD2 high by
removing the jumpers.
1k⍀ In order to look at the modulator and IF amplifiers separately,
Figure 31. IF Input Port Impedance Match Used During disconnect the output of the modulator from the input of the IF
Characterization at ADI amplifiers. This is accomplished by short circuiting X12, X14,
X19 and X20 and open circuiting X11, X18, X25 and X26.
This is a broadband lossy match used for characterization over
the 50 MHz to 350 MHz frequency range. All dBm references
in the characterization data collected using this match are refer-
enced to 1 kΩ. Note that the 1:8 ratio in Figure 31 is an imped-
ance ratio and not a voltage ratio.

–16– REV. B
 AD6122
Table III describes the high frequency signal connectors on the Table IV lists the connections for the 20-pin power-supply
AD6122 customer sample boards. connector.

Table III. Evaluation Board SMA Signal Connector Table IV. 20-Pin Power Supply Connection Information
Description
Pin # Function
Connector Description
1 VPOS for AD6122; 2.9 V to 4.2 V using regulator; 2.7 V
I CH I Modulator Input. 250 mV p-p into 50 Ω to 4.2 V bypassing regulator.
termination, dc coupled. The level shifting and 2 VPOS for AD6122; 2.9 V to 4.2 V using regulator; 2.7 V
phase splitting is done on board by the AD830 to 3.6 V bypassing regulator.
amplifiers.
3 Ground.
Q CH Q Modulator Input. 250 mV p-p into 50 Ω 4 Ground.
termination, ac coupled. The level shifting and 5 Ground.
phase splitting is done on board by the AD830
6 Regulated Output or Input Voltage; Connects to Pin 5
amplifiers.
on AD6122.
MODOP Modulator Output. The differential-to-single 7 Ground.
ended conversion is performed by a balun on
8 Ground.
the board. Impedance matched to 50 Ω for
130.38 MHz IF frequency. 9 Ground.
10 Ground.
IFIP IF Amplifier Input. Single-ended-to-differential
11 Ground.
conversion performed by a balun on board.
Impedance matched to 50 Ω for 130.38 MHz IF 12 PD1; Power-Down 1 Input.
frequency. 13 Ground.
14 1.23 V Reference Voltage from AD6122.
TXOP IF Amplifier Output. Differential-to-single-
ended conversion performed by a balun on 15 Ground.
board. Impedance matched to 50 Ω for 130.38 16 VGAIN; Gain Control Voltage Input.
MHz IF frequency. 17 –15 V Supply for AD830 Differential Amplifier.
LOIPP Local oscillator positive input at 2 × IF 18 +15 V Supply for AD830 Differential Amplifier.
frequency. 19 MODCMREF; common-mode reference output for
baseband converter common-mode reference input.
20 PD2; Power-Down 2 Input.

A schematic diagram of the evaluation board is on the next two

pages.

REV. B –17–
AD6122

AD6122 R12
0⍀
PD1 PD1 VGAIN VGAIN
C28
10nF
PD2 PD2 REFIN
J2
0⍀ FMMT4403CT-ND
VPOS
LDOE REFOUT REFOUT
2.9V – 4.2V C29
10nF
Q1 LDOB IFVCC IFVCC
J1

VREG OUT LDOC IFGND

C23
18pF
LDOGND IIPP IIPP
VREG OUT VREG OUT
DGND IIPN IIPN
X2 C1 C26
0⍀ 10nF C27
10nF 10nF
LOIPP LOIPP MODCMREF MODCMREF
C2
X1 X3 VCC 10nF
C24
0.1␮F LOIPN QIPN QIPN L4 L5
180nH 180nH
DVCC DVCC QIPP QIPP
X5 L2
X8 C3 220nH
X16
100nH 0⍀ 10nF 100nH MODOP
1:8 8:1
TXOP TXOPP MODOPP
X6 C8 X12 X15
X4 3pF C9
X7 X9 10nF 10nF X13 4pF
TXOPN MODOPN X17
C10
10nF X14 T2
T1 X10 C4 X11
0⍀ 10nF TXVCC TXVCC IFINP
0⍀ L6 X25
L3 0⍀
220nH
IFGND IFINN C30
VCC C25
10nF C11
10nF R13

R14 = 442⍀ R14 R16

R15 = 100⍀ R15
R16 = 442⍀ X23
X18
0⍀ X19 27nH
8:1
IFIP
X26 X22
X20 56nH
0⍀
X24
X21 T3

Figure 33. Schematic Diagram of the Evaluation Board

–18– REV. B
 AD6122
C15 C19
0.1␮F 0.1␮F
+15V +15V

8 SOIC PACKAGE 8 SOIC PACKAGE

1 U2 1 U4
2 V–1 R7 V–1 R10
2
7 50⍀ 7 50⍀
A=1 TO A=1 TO
3 IIPP 3 QIPP
MODCMREF MODCMREF
4 V–1 4 V–1
AD830 AD830
5 5

–15V –15V
ICH C16 QCH
C20
R6 0.1␮F R9 0.1␮F
50⍀ 50⍀

C17 C21
0.1␮F 0.1␮F
+15V +15V

1 8 1 8
U3 U5
V–1 R8 V–1 R11
2 2
7 50⍀ 7 50⍀
A=1 TO A=1 TO
3 IIPN 3 QIPN
MODCMREF MODCMREF
4 V–1 4 V–1
AD830 AD830
5 5

–15V –15V
C18 C22
0.1␮F 0.1␮F

TO P1 P2 L1
TXVCC VREG OUT 470nH
C6 R1 VPOS FROM VPOS
18pF 10⍀ 1 2 2.9V–4.2V
C13 3 4 R4 R5
0.01␮F
10k⍀ 10k⍀
5 6 VREG OUT
TO
DVCC 7 8
C5 R2
18pF 10⍀ 9 10
C12 PD1
11 12
0.01␮F
13 14 REFOUT
TO
IFVCC C7 R3 15 16 VGAIN
18pF 10⍀ PD1 PD2
–15V 17 18 +15V
C14
0.01␮F MODCMREF 19 20
PD2

NOTES:
1. TO USE THE LDO REGULATOR, SHORT J2 AND OPEN J1.
2. TO BYPASS THE REGULATOR, SHORT J1 AND OPEN J2
3. TO CONNECT THE OUTPUT OF THE MODULATOR TO THE
INPUT OF THE IF AMP, SHORT J5 AND J6.
TO TEST THE MODULATOR AND THE IF AMP SEPARATELY,
OPEN J5 AND J6.
4. INDICATES A 50⍀ TRACE.

Figure 34. Schematic Diagram of the Evaluation Board

REV. B –19–
AD6122
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

28-Lead SSOP
(RS-28)

C00946a–.5–6/00 (rev. B)
0.407 (10.34)
0.397 (10.08)

28 15

0.212 (5.38)
0.205 (5.21)
0.301 (7.64)
0.311 (7.9)

1 14

0.078 (1.98) PIN 1 0.07 (1.79)

0.068 (1.73) 0.066 (1.67)

8° 0.03 (0.762)
0.008 (0.203) 0.0256 0.015 (0.38)
SEATING 0.009 (0.229) 0° 0.022 (0.558)
(0.65) 0.010 (0.25)
0.002 (0.050) BSC PLANE
0.005 (0.127)

32-Leadless Chip Scale Package (LPCC)

(CP-32)

0.205 (5.20) 0.128 (3.25)

0.197 (5.00) SQ 0.106 (2.70) SQ
0.189 (4.80) 0.049 (1.25)
25 32
1
PIN 1
24 INDICATOR

0.015 (0.38)
BOTTOM 0.012 (0.30)
VIEW 0.009 (0.23)

17 8 0.018 (0.45)
16 9 0.016 (0.40)
0.138 (3.50) BSC 0.014 (0.35)

0.039 (1.00)
0.010 0.035 (0.90)
(0.25) 0.031 (0.80)
REF 0.002 (0.05)
0.020 (0.50)
BSC 0.001 (0.02)
0.000 (0.00)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS MEET JEDEC MO-220-VHHD-2

PRINTED IN U.S.A.

–20– REV. B