MT7628 DATASHEET

© 2014 MediaTek Inc.

This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.

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 MT7628
Chip Name
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Overview
The MT7628 router-on-a-chip includes an 802.11n MAC and baseband, a 2.4 GHz radio and FEM, a 580 MHz
MIPS® 24K™ CPU core, a 5-port 10/100 fast ethernet switch. The MT7628 includes everything needed to build
an AP router from a single chip. The embedded high performance CPU can
process advanced applications effortlessly, such as routing, security and VoIP. The Applications:
MT7628 also includes a selection of interfaces to support a variety of applications,  Routers
such as a USB port for accessing external storage.  NAS devices
 Dual band
Features concurrent routers
 Embedded MIPS24KEc (580 MHz) with 64 KB I-  5-port 10/100 FE PHY
Cache and 32 KB D-Cache  Internet Of Thing
 2T2R 2.4 GHz with 300 Mbps PHY data rate  An optimized PMU
 Legacy 802.11b/g and HT 802.11n modes  Green AP
 20/40 MHz channel bandwidth  Intelligent Clock Scaling (exclusive)
 Legacy 802.11b/g and HT 802.11n modes  DDRII: ODT off, Self-refresh mode
 Reverse Data Grant (RDG)  I2C, I2S, SPI, PCM, UART, JTAG, GPIO
 Maximal Ratio Combining (MRC)  16 Multiple BSSID
 Space Time Block Coding (STBC)  WEP64/128, TKIP, AES, WPA, WPA2, WAPI
 MCM 8 Mbytes DDR1 KGD (MT7628KN)  QoS: WMM, WMM-PS
 16-bit DDR1/2 up to 128/256 Mbytes  WPS: PBC, PIN
(MT7628AN/KN)  Voice Enterprise: 802.11k+r
 SPI/SD-XC/eMMC  AP Firmware: Linux 2.6 SDK, eCOS with IPv6
 x1 USB 2.0 Host, x1 PCIe Root Complex
Functional Block Diagram
EJTAG 16-Bit DDR1/DDR2 To CPU
interrupts
MIPS 24KEc DRAM INTC
64 KB I-Cache Controller
Timer
32 KB D-Cache OCP_IF
(580 MHz) OCP Bridge Arbiter
SPI SPI
NFC NAND
PBUS

RBUS (SYS_CLK) UART UART

GPIO
PBUS GPIO
/LED
SDHC Single Port PCIe 1.1 WLAN Switch I2C I2C
GDMA
USB 2.0 PHY PHY 11n 2x2 (5FE)
I2S I2S
PCIe x1 5-Port EPHY
SD Host X1 2.4 GHz PCM x4 PCM
RJ45 x5

Ordering Information

Part Number Package

(Green/RoHS Compliant)
MT7628AN DR-QFN 156 pin
(12 mm x 12 mm)
MT7628KN DR-QFN 120 pin
(10 mm x 10 mm)

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Table of Contents
1. MAIN FEATURES 6
2. PINS 7
2.1 MT7628AN DR-QFN (12 MM X 12 MM) 156-PIN PACKAGE DIAGRAM 7
2.1.1 UP-LEFT SIDE 7
2.1.2 DOWN-LEFT SIDE 8
2.1.3 DOWN-RIGHT SIDE 9
2.1.4 UP-RIGHT SIDE 10
2.1.5 PIN DESCRIPTION 11
2.2 MT7628KN DR-QFN (10 MM X 10 MM) 120-PIN PACKAGE DIAGRAM 17
2.2.1 LEFT SIDE VIE 17
2.2.2 RIGHT SIDE VIEW 19
2.2.3 PIN DESCRIPTION 20
2.3 PIN SHARING SCHEMES 23
2.3.1 GPIO PIN SHARE SCHEME 23
2.3.2 UART1 PIN SHARE SCHEME 26
2.3.3 MT7628AN EPHY LED PIN SHARE SCHEME 26
2.3.4 MT7628AN WLAN LED PIN SHARE SCHEME 26
2.3.5 MT7628KN EPHY LED PIN SHARE SCHEME 26
2.3.6 MT7628KN WLAN LED PIN SHARE SCHEME 27
2.3.7 PERST_N PIN SHARE SCHEME 27
2.3.8 WDT_RST_N PIN SHARE SCHEME 27
2.3.9 REF_CLKO PIN SHARE SCHEME 27
2.3.10 UART0 PIN SHARE SCHEME 28
2.3.11 GPIO0 PIN SHARE SCHEME 28
2.3.12 SPI PIN SHARE SCHEME 28
2.3.13 SPI_CS1 PIN SHARE SCHEME 28
2.3.14 I2C PIN SHARE SCHEME 28
2.3.15 I2S PIN SHARE SCHEME 28
2.3.16 SD PIN SHARE SCHEME 30
2.3.17 UART2 PIN SHARE SCHEME 30
2.3.18 PWM_CH0 PIN SHARE SCHEME 30
2.3.19 PWM_CH1 PIN SHARE SCHEME 30
2.3.20 SPIS PIN SHARE SCHEME 30
2.3.21 PIN SHARE FUNCTION DESCRIPTION 31
2.4 BOOTSTRAPPING PINS DESCRIPTION 31
3. MAXIMUM RATINGS AND OPERATING CONDITIONS 33
3.1 ABSOLUTE MAXIMUM RATINGS 33
3.2 MAXIMUM TEMPERATURES 33
3.3 OPERATING CONDITIONS 33
3.4 THERMAL CHARACTERISTICS 33
3.5 STORAGE CONDITIONS 34
3.6 EXTERNAL XTAL SPECFICATION 34
3.7 DC ELECTRICAL CHARACTERISTICS 34
3.8 AC ELECTRICAL CHARACTERISTICS 35
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 MT7628
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3.8.1 DDR2 SDRAM INTERFACE 36

3.8.2 SPI INTERFACE 38
2
3.8.3 I S INTERFACE 39
3.8.4 PCM INTERFACE 40
3.8.5 POWER ON SEQUENCE 41
3.9 PACKAGE PHYSICAL DIMENSIONS 42
3.9.1 DR-QFN (10 MM X 10 MM) 128 PINS 42
3.9.2 DR-QFN (12 MM X 12 MM) 156 PINS 44
3.9.3 MT7628 AN/KN MARKING 46
3.9.4 REFLOW PROFILE GUIDELINE 48
4. ABBREVIATIONS 49
5. REVISION HISTORY 52

Table of Figures
FIGURE 2-1 MT7628AN DR-QFN PIN DIAGRAM (UP-LEFT VIEW) ...................................................................................... 7
FIGURE 2-2 MT7628AN DR-QFN PIN DIAGRAM (DOWN-LEFT VIEW) ................................................................................. 8
FIGURE 2-3 MT7628AN DR-QFN PIN DIAGRAM (DOWN-RIGHT VIEW) ............................................................................... 9
FIGURE 2-4 MT7628AN DR-QFN PIN DIAGRAM (UP-RIGHT VIEW) .................................................................................. 10
FIGURE 2-5 MT7628KN DR-QFN PIN DIAGRAM (LEFT VIEW) ......................................................................................... 18
FIGURE 2-6 MT7628KN DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW) ................................................................................. 19
FIGURE 3-1 DDR2 SDRAM COMMAND ....................................................................................................................... 36
FIGURE 3-2 DDR2 SDRAM WRITE DATA ...................................................................................................................... 36
FIGURE 3-3 DDR2 SDRAM READ DATA ....................................................................................................................... 36
FIGURE 3-4 SPI INTERFACE ......................................................................................................................................... 38
FIGURE-3-5 I2S INTERFACE ......................................................................................................................................... 39
FIGURE 3-6 PCM INTERFACE ....................................................................................................................................... 40
FIGURE 3-7 POWER ON SEQUENCE .............................................................................................................................. 41
FIGURE 3-8 TOP VIEW................................................................................................................................................ 42
FIGURE 3-9 SIDE VIEW ............................................................................................................................................... 42
FIGURE 3-10 “B” EXPANDED....................................................................................................................................... 43
FIGURE 3-11 BOTTON VIEW ........................................................................................................................................ 43
FIGURE 3-12 TOP VIEW.............................................................................................................................................. 44
FIGURE 3-13 SIDE VIEW ............................................................................................................................................. 44
FIGURE 3-14 “B” EXPANDED....................................................................................................................................... 44
FIGURE 3-15 BOTTOM VIEW ....................................................................................................................................... 45
FIGURE 3-16 MT7620AN TOP MARKING...................................................................................................................... 47
FIGURE 3-17 MT7628KN TOP MARKING ...................................................................................................................... 47
FIGURE 3-18 REFLOW PROFILE FOR MT7628 ................................................................................................................ 48

List of Tables
TABLE 1-1 MAIN FEATURES........................................................................................................................................... 6
TABLE 3-1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 33
TABLE 3-2 MAXIMUM TEMPERATURES .......................................................................................................................... 33
TABLE 3-3 OPERATING CONDITIONS ............................................................................................................................. 33
TABLE 3-4 THERMAL CHARACTERISTICS ......................................................................................................................... 34
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 MT7628
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TABLE 3-5 EXTERNAL XTAL SPECIFICATIONS .................................................................................................................... 34

TABLE 3-6 DC ELECTRICAL CHARACTERISTICS .................................................................................................................. 34
TABLE 3-7 VDD 2.5V ELECTRICAL CHARACTERISTICS ........................................................................................................ 35
TABLE 3-8 VDD 1.8V ELECTRICAL CHARACTERISTICS ........................................................................................................ 35
TABLE 3-9 VDD 3.3V ELECTRICAL CHARACTERISTICS ........................................................................................................ 35
TABLE 3-10 DDR2 SDRAM INTERFACE DIAGRAM KEY .................................................................................................... 37
TABLE 3-11 SPI INTERFACE DIAGRAM KEY ..................................................................................................................... 38
TABLE 3-12 I2S INTERFACE DIAGRAM KEY ..................................................................................................................... 39
TABLE 3-13 PCM INTERFACE DIAGRAM KEY .................................................................................................................. 40
TABLE 3-14 POWER ON SEQUENCE DIAGRAM KEY.......................................................................................................... 41

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 MT7628
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1. Main Features
The following table covers the main features offered by the MT7628KN and MT7628AN. Overall, the
MT7628KN supports the requirements of an entry-level AP/router, while the more advanced MT7628AN
supports a number of interfaces together with a large maximum RAM capacity.

Features MT7628KN MT7628AN

CPU MIPS24KEc (580 MHz) MIPS24KEc (580 MHz)
Total DMIPs 580 x 1.6 DMIPs 580 x 1.6 DMIPs
I-Cache, D-Cache 64 KB, 32 KB 64 KB, 32 KB
L2 Cache n/a n/a
Memory
DRAM Device width support 16 bits 16 bits
DDR1 64 Mb (MCM), 193 MHz 2 Gb, 193 MHz
DDR2 n/a 2 Gb, 193 MHz
SPI Flash 3B addr mode (max 128Mbit) 3B addr mode (max 128Mbit)
4B addr mode (max 512Mbit) 4B addr mode (max 512Mbit)
SD n/a SD-XC (class 10)
RF 2T2R 802.11n 2.4 GHz 2T2R 802.11n 2.4 GHz
PCIe 1 1
USB 2.0 1 1
Switch 5p FE SW 5p FE SW

I2S 1 1
PCM 1 1
I2C 1 1
UART 2 (Lite) 2 (Lite)
JTAG 1 1
Package DR-QFN120- 10 mm x 10 mm DR-QFN156- 12 mm x 12 mm

Table 1-1 Main Features

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2. Pins

2.1 MT7628AN DR-QFN (12 mm x 12 mm) 156-Pin Package Diagram

2.1.1 Up-left side

AVDD33_WF_RFDIG
XTALIN

WLED_N
UART_RXD1

UART_TXD1

PORST_N

PERST_N
EPHY_LED1_N_JTDI

EPHY_LED2_N_JTMS

WDT_RST_N

REF_CLK0
EPHY_LED0_N_JTDO
CLKOUTP

AVSS33_XTAL

AVDD33_XTAL

EPHY_LED4_N_JTRST_N

AVDD33_PCIE
WF0_LNA_EXT

SOC_IO_V33D_2

SOC_CO_V12D_5

EPHY_LED3_N_JTCLK
AVDD33_WF0_TRX

AVDD33_WF_SX

DR-QFN 12X12
156 pin

156 154 152 150 148 146 144 142 140 138 136 134
155 153 151 149 147 145 143 141 139 137 135
DIG
AVSS33_RF_1 1
AVSS33_RF_2 2
WF0_RFION_1 3
WF0_RFION_2 4
WF0_RFIOP_1 5
WF0_RFIOP_2 6 RF
AVSS33_RF_3 7
AVDD33_WF0_TX 8
WF1_LNA_EXT 9
AVSS33_RF_4 10
WF1_RFION 11
WF1_RFIOP 12
AVSS33_RF_5 13
AVDD33_WF1_TX 14
AVDD33_WF1_TRX 15
I2S_SDI 16
I2S_SDO 17
I2S_WS 18
I2S_CLK 19

Figure 2-1 MT7628AN DR-QFN Pin Diagram (up-left view)

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2.1.2 Down-left side

I2C_SCLK 20
I2C_SD 21 DIG
SOC_CO_V12D_1 22
SOC_IO_V33D_1 23
SPI_CS1 24
SPI_CLK 25
SPI_MISO 26
SPI_MOSI 27
SPI_CS0 28
GPIO0 29
UART_TXD0 30
UART_RXD0 31
AVDD33_TX_P0 32
MDI_RP_P0 33
MDI_RN_P0 34
MDI_TP_P0 35
MDI_TN_P0 36
NC1 37
AVDD33_COM 38
EPHY_VRT 39
EPHY USB
41 43 45 47 49 51 53 55 57 59 61
40 42 44 46 48 50 52 54 56 58 60 62
AVDD33_TX_P1234_1

AVDD33_TX_P1234_2

SOC_CO_V12D_2

AVDD33_USB
MDI_RN_P1

MDI_RN_P2

MDI_RN_P3

MDI_RN_P4
MDI_TN_P1

MDI_TN_P2

MDI_TN_P3

MDI_TN_P4
MDI_RP_P1

MDI_RP_P2

MDI_RP_P3

MDI_RP_P4
MDI_TP_P1

MDI_TP_P2

MDI_TP_P3

MDI_TP_P4

USB_VRT

USB_DM
USB_DP
Figure 2-2 MT7628AN DR-QFN Pin Diagram (down-left view)

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2.1.3 Down-right side

98 DDR_IO_1V8D_2 DDR_IO_1V8D_2
97 MA3 MBA1
96 MA12 MBA0
95 MA7 MCS
94 MA9 MRAS
93 MA5 MCAS
92 MA10 MWE
91 SOC_CO_V12D_4 SOC_CO_V12D_4
90 DDR_IO_VREF_1 DDR_IO_VREF_1
89 SOC_CO_V12D_3 SOC_CO_V12D_3
88 MA1 MA13
87 MA2 MCKE
86 MA6 MA12
85 MA11 MA11
84 MA8 MA9
83 MA13 MA8
82 MA4 MA7
81 MRAS MA6
80 MA0 MA5
79 DDR_IO_1V8D_1 DDR_IO_1V8D_1
DDR
63 65 67 69 71 73 75 77
64 66 68 70 72 74 76 78
DDR_IO_VSS_1

MDQM1

MDQS1

MCK_N

MCK_P
MODT
MD15

MD13

MD10

MCAS
MD8

MD2

MD7

MD0

MD5

MCS

[ DDR2 ]
DDR_IO_VSS_1

DDR_IO_VSS_2

DDR_IO_VSS_3
MDQM1
MDQS1

MCK_N

MCK_P
MD15

MD14

MD13

MD12

MD11

MD10

MD9

MD8

MA4

[ DDR1 ]

Figure 2-3 MT7628AN DR-QFN Pin Diagram (down-right view)

Note: DR-QFN support DDR1 and DDR2 pin shuffle depend on the bootstrap.

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2.1.4 Up-right side PCIE_RXP0

VOUT_FB

LXBK_2

LXBK_1
PCIE_CKP0

PCIE_TXN0
PCIE_CKN0

PCIE_RXN0

PCIE_TXP0

DDRLDO
AVDD12_PCIE

AVDD33_DDRLDO_2

AVDD33_DDRLDO_1

AVSS33_SMPS_2

AVSS33_SMPS_1
PCIE_IO_VSS

[ DDR2 ] [ DDR1 ]

132 130 128 126 124 122 120 118

133 131 129 127 125 123 121 119
PCIE PMU
117 AVDD33_SMPS
116 DDR_IO_1V8D_3 DDR_IO_1V8D_3
115 DDR_IO_VSS_2 DDR_IO_VSS_4
114 MD14 MD0
113 MDQS0 MDQS0
112 MD9 MD1
111 MD12 MD2
110 MD11 MD3
109 MD6 MD4
108 MDQM0 MD5
107 MD1 MD6
106 MD4 MD7
105 MD3 MDQM0
104 DDR_IO_VREF_2 DDR_IO_VREF_2
103 MCKE MA3
102 MWE MA2
101 MBA2 MA1
DDR 100 MBA0 MA0
99 MBA1 MA10

Figure 2-4 MT7628AN DR-QFN Pin Diagram (up-right view)

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2.1.5 Pin Description

Pins Name Type Driv. Description
RF
3,4 WF0_RFION_1 A WF0 main path RF I/O
WF0_RFION_2
5,6 WF0_RFIOP_1 A WF0 main path RF I/O
WF0_RFIOP_2
11 WF1_RFION A WF1 main path RF I/O
12 WF1_RFIOP A WF1 main path RF I/O
9 WF1_LNA_EXT A WF1 aux. path LNA input
156 WF0_LNA_EXT A WF0 aux. path LNA input
151 XTALIN I Crystal oscillator input
153 CLKOUTP O XO reference clock output
152 AVDD33_XTAL P 3.3V XTAL Power Supply Pin
150 AVSS33_XTAL G 3.3V XTAL Ground Pin
8 AVDD33_WF0_TX P 3.3V RF Channel 0 Suppoly Power
14 AVDD33_WF1_TX P 3.3V RF Channel 1 Suppoly Power
15 AVDD33_WF1_TRX P 1.65V to 3.3V RF Channel 1 Suppoly Power
149 AVDD33_WF_RFDIG P 1.65V to 3.3V RF DIG and AFE Suppoly Power
154 AVDD33_WF_SX P 1.65V to 3.3V RF Supply Power
155 AVDD33_WF0_TRX P 1.65V to 3.3V RF Channel 0 Suppoly Power
1,2 AVSS33_RF G 3.3V RF Shielding Ground Pin
7,13
WLAN LED
144 WLED_N O 4 mA WLAN Activity LED
UART0 Lite
31 RXD0 I 4 mA UART0 Lite RXD
30 TXD0 O, IPD 4 mA UART0 Lite TXD
UART1 Lite
147 TXD1 O, IPU 4 mA UART1 Lite TXD
148 RXD1 I 4 mA UART1 Lite RXD
I2S
16 I2S_SDI O 4 mA I2S data input
17 I2S_SDO I/O, IPD 4 mA I2S data output
18 I2S_WS O 4 mA I2S word select
19 I2S_CLK I/O 4 mA I2S clock
I2C
21 I2C_SD 4 mA I2C Data

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Pins Name Type Driv. Description

20 I2C_SCLK I/O 4 mA I2C Clock
SPI
26 SPI_MISO I/O 4 mA SPI Master input/Slave output
27 SPI_MOSI I/O, IPD 4 mA SPI Master output/Slave input
25 SPI_CLK O, IPU 4 mA SPI clock
28 SPI_CS0 O 4 mA SPI chip select0
24 SPI_CS1 O, IPD 4 mA SPI chip select1
GPIO
29 GPIO0 I/O, IPD 4 mA General Purpose I/O
5-Port EPHY
143 EPHY_LED0 _N_JTDO I/O 4 mA 10/100 PHY Port #0 activity LED, JTAG_TDO
142 EPHY_LED1 _N_JTDI I/O 4 mA 10/100 PHY Port #1 activity LED, JTAG_TDI
141 EPHY_LED2 _N_JTMS I/O 4 mA 10/100 PHY Port #2 activity LED, JTAG_TMS
140 EPHY_LED3 _N_JTCLK I/O 4 mA 10/100 PHY Port #3 activity LED, JTAG_CLK
139 EPHY_LED4 I/O, 4 mA 10/100 PHY Port #4 activity LED, JTAG_TRST_N
_N_JTRST_N
39 EPHY_VRT A Connect to an external resistor to provide accurate bias
current
33 MDI_RP_P0 A 10/100 PHY Port #0 RXN
34 MDI_RN_P0 A 10/100 PHY Port #0 RXP
35 MDI_TP_P0 A 10/100 PHY Port #0 TXN
36 MDI_TN_P0 A 10/100 PHY Port #0 TXP
40 MDI_TP_P1 A 10/100 PHY Port #1 RXN
42 MDI_TN_P1 A 10/100 PHY Port #1 RXP
43 MDI_RP_P1 A 10/100 PHY Port #1 TXN
44 MDI_RN_P1 A 10/100 PHY Port #1 TXP
45 MDI_RP_P2 A 10/100 PHY Port #2 RXN
46 MDI_RN_P2 A 10/100 PHY Port #2 RXP
47 MDI_TP_P2 A 10/100 PHY Port #2 TXN
48 MDI_TN_P2 A 10/100 PHY Port #2 TXP
49 MDI_TP_P3 A 10/100 PHY Port #3 RXN
50 MDI_TN_P3 A 10/100 PHY Port #3 RXP
51 MDI_RP_P3 A 10/100 PHY Port #3 TXN
52 MDI_RN_P3 A 10/100 PHY Port #3 TXP
54 MDI_RP_P4 A 10/100 PHY Port #4 RXN
55 MDI_RN_P4 A 10/100 PHY Port #4 RXP
56 MDI_TP_P4 A 10/100 PHY Port #4 TXN

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Pins Name Type Driv. Description

57 MDI_TN_P4 A 10/100 PHY Port #4 TXP
32 AVDD33_TX_P0 P 3.3V Supply Power for P0
38 AVDD33_COM P 3.3V Supply Power for EPHY COM
41 AVDD33_TX_P1234_1 P 3.3V Supply Power for P1 ~ P4
AVDD33_TX_P1234_2
Misc.
136 REF_CLKO O, IPD 4 mA Reference Clock Ouptut
138 PORST_N I, IPU 4 mA Power on reset
137 WDT_RST_N O 4 mA Watchdog timeout reset
USB PHY
129 AVDD33_USB P 3.3 V USB PHY analog power supply
130 USB _VRT I/O Connect to an external 5.1 kΩ resistor for band-gap
reference circuit
62 USB_DM I/O USB Port0 data pin Data-
61 USB _DP I/O USB Port0 data pin Data+
PCIe PHY
135 PERST_N O, IPD 4mA PCIe device reset
134 AVDD12_PCIE P 1.2 V PCIE PHY digital power supply
129 AVDD33_PCIE P 3.3 V USB PHY analog power supply
128 PCIE_IO_VSS P PCIE PHY Ground Pin
133 PCIE_CKP0 I/O External reference clock output (positive)
132 PCIE_CKN0 I/O External reference clock output (negative)
127 PCIE_TXP0 I/O PCIe0 differential transmit TX -
126 PCIE_TXN0 I/O PCIe0 differential transmit TX -
129 PCIE_TXP0 I/O PCIe0 differential receiver RX -
130 PCIE_TXN0 I/O PCIe0 differential receiver RX -
DDR2
65 MD15 I/O 8 mA DDR2 Data bit #15
114 MD14 I/O 8 mA DDR2 Data bit #14
67 MD13 I/O 8 mA DDR2 Data bit #13
111 MD12 I/O 8 mA DDR2 Data bit #12
110 MD11 I/O 8 mA DDR2 Data bit #11
68 MD10 I/O 8 mA DDR2 Data bit #10
112 MD9 I/O 8 mA DDR2 Data bit #9
66 MD8 I/O 8 mA DDR2 Data bit #8
70 MD7 I/O 8 mA DDR2 Data bit #7
109 MD6 I/O 8 mA DDR2 Data bit #6

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 MT7628
Chip Name
Confidential B

Pins Name Type Driv. Description

73 MD5 I/O 8 mA DDR2 Data bit #5
106 MD4 I/O 8 mA DDR2 Data bit #4
105 MD3 I/O 8 mA DDR2 Data bit #3
69 MD2 I/O 8 mA DDR2 Data bit #2
107 MD1 I/O 8 mA DDR2 Data bit #1
71 MD0 I/O 8 mA DDR2 Data bit #0
83 MA13 O 8 mA DDR2 Address bit #13
96 MA12 O 8 mA DDR2 Address bit #12
85 MA11 O 8 mA DDR2 Address bit #11
92 MA10 O 8 mA DDR2 Address bit #10
94 MA9 O 8 mA DDR2 Address bit #9
84 MA8 O 8 mA DDR2 Address bit #8
95 MA7 O 8 mA DDR2 Address bit #7
86 MA6 O 8 mA DDR2 Address bit #6
93 MA5 O 8 mA DDR2 Address bit #5
82 MA4 O 8 mA DDR2 Address bit #4
97 MA3 O 8 mA DDR2 Address bit #3
87 MA2 O 8 mA DDR2 Address bit #2
88 MA1 O 8 mA DDR2 Address bit #1
80 MA0 O 8 mA DDR2 Address bit #0
101 MBA2 O 8 mA DDR2 MBA #2
99 MBA1 O 8 mA DDR2 MBA #1
100 MBA0 O 8 mA DDR2 MBA #0
74 MODT O 8 mA DDR2 ODT
81 MRAS O 8 mA DDR2 MRAS_N
75 MCAS O 8 mA DDR2 MCAS_N
102 MWE O 8 mA DDR2 MWE_N
77 MCK_P O 8 mA DDR2 MCK_P
76 MCK_N O 8 mA DDR2 MCK_N
64 MDQM1 O 8 mA DDR2 MDQM#1
108 MDQM0 O 8 mA DDR2 MDQM#0
78 MCS O 8 mA DDR2 MCS
72 MDQS1 I/O 8 mA DDR2 MDQS#1
113 MDQS0 I/O 8 mA DDR2 MDQS#0
103 MCKE O 8 mA DDR2 MCKE
63 DDR_IO_VSS_1 G DDR IO Ground pins
115 DDR_IO_VSS_2

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 MT7628
Chip Name
Confidential B

Pins Name Type Driv. Description

79 DDR_IO_1V8D_1 P DDR io Supply power
98 DDR_IO_1V8D_2
116 DDR_IO_1V8D_3
90 DDR_IO_VREF_1 A DDR reference voltage
104 DDR_IO_VREF_2
DDR1
64 MD15 I/O 8 mA DDR1 Data bit #15
65 MD14 I/O 8 mA DDR1 Data bit #14
66 MD13 I/O 8 mA DDR1 Data bit #13
67 MD12 I/O 8 mA DDR1 Data bit #12
68 MD11 I/O 8 mA DDR1 Data bit #11
69 MD10 I/O 8 mA DDR1 Data bit #10
70 MD9 I/O 8 mA DDR1 Data bit #9
71 MD8 I/O 8 mA DDR1 Data bit #8
106 MD7 I/O 8 mA DDR1 Data bit #7
107 MD6 I/O 8 mA DDR1 Data bit #6
108 MD5 I/O 8 mA DDR1 Data bit #5
109 MD4 I/O 8 mA DDR1 Data bit #4
110 MD3 I/O 8 mA DDR1 Data bit #3
111 MD2 I/O 8 mA DDR1 Data bit #2
112 MD1 I/O 8 mA DDR1 Data bit #1
114 MD0 I/O 8 mA DDR1 Data bit #0
88 MA13 O 8 mA DDR1 Address bit #13
86 MA12 O 8 mA DDR1 Address bit #12
85 MA11 O 8 mA DDR1 Address bit #11
99 MA10 O 8 mA DDR1 Address bit #10
84 MA9 O 8 mA DDR1 Address bit #9
83 MA8 O 8 mA DDR1 Address bit #8
82 MA7 O 8 mA DDR1 Address bit #7
81 MA6 O 8 mA DDR1 Address bit #6
80 MA5 O 8 mA DDR1 Address bit #5
74 MA4 O 8 mA DDR1 Address bit #4
103 MA3 O 8 mA DDR1 Address bit #3
102 MA2 O 8 mA DDR1 Address bit #2
101 MA1 O 8 mA DDR1 Address bit #1
100 MA0 O 8 mA DDR1 Address bit #0
97 MBA1 O 8 mA DDR1 MBA #1

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 MT7628
Chip Name
Confidential B

Pins Name Type Driv. Description

96 MBA0 O 8 mA DDR1 MBA #0
94 MRAS O 8 mA DDR1 MRAS_N
93 MCAS O 8 mA DDR1 MCAS_N
92 MWE O 8 mA DDR1 MWE_N
77 MCK_P O 8 mA DDR1 MCK_P
76 MCK_N O 8 mA DDR1 MCK_N
73 MDQM1 O 8 mA DDR1 MDQM#1
105 MDQM0 O 8 mA DDR1 MDQM#0
95 MCS O 8 mA DDR1 MCS
72 MDQS1 I/O 8 mA DDR1 MDQS#1
113 MDQS0 I/O 8 mA DDR1 MDQS#0
87 MCKE O 8 mA DDR1 MCKE
63 DDR_IO_VSS_1 G DDR IO Ground pins
75 DDR_IO_VSS_2
78 DDR_IO_VSS_3
115 DDR_IO_VSS_4
79 DDR_IO_1V8D_1 P DDR IO Supply power
98 DDR_IO_1V8D_2
116 DDR_IO_1V8D_3
90 DDR_IO_VREF_1 A DDR reference voltage
104 DDR_IO_VREF_2
PMU
118 LXBK_1 O Buck Switching node
119 LXBK_2
122 VOUT_FB A Buck vout feedback pin
59 AVDD33_SMPS P Buck 3.3V Supply power
120 AVSS33_SMPS_1 G Buck Gound pin
121 AVSS33_SMPS_2
123 AVDD33_DDRLDO_1 G DDRLDO 3.3V Supply power
124 AVDD33_DDRLDO_2
56 DDRLDO O DDRLDO 1.8V/2.5V output voltage
Power
23 SOC_IO_V33D_1 P 3.3 V digital I/O power supply
146 SOC_IO_V33D_2
22 SOC_CO _V12D_1 P 1.2 V digital core power supply
58 SOC_CO _V12D_2
89 SOC_CO _V12D_3
91 SOC_CO _V12D_4
145 SOC_CO _V12D_5
EPAD GND G Ground pin
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 MT7628
Chip Name
Confidential B

Pins Name Type Driv. Description

Total: 156 pins

Note:
IPD : Internal pull-down
IPU : Internal pull-up
I : Input
O : Output
IO : Bi-directional
P : Power
G : Ground
NC : Not connected

2.2 MT7628KN DR-QFN (10 mm x 10 mm) 120-Pin Package Diagram

2.2.1 Left side vie AVDD33_WF_RFDIG

XTALIN

UART_RXD1

UART_TXD1

PORST_N

WDT_RST_N

PERST_N
REF_CLK0
AVSS33_XTAL_2

AVSS33_XTAL_1

AVDD33_XTAL

SOC_IO_V33D_3

SOC_CO_V12D_8
AVDD33_WF0_TRX

AVDD33_WF_SX

CLKOUTP

DR-QFN 10X10
120 pin

120 118 116 114 112 110 108 106

119 117 115 113 111 109 107 105
DIG
WF0_LNA_EXT 1
WF0_RFION_1 2
WF0_RFION_2 3
WF0_RFIOP_1 4
WF0_RFIOP_2 5
AVDD33_WF0_TX 6 RF
WF1_LNA_EXT 7
WF1_RFION_1 8
WF1_RFION_2 9
WF1_RFIOP_1 10
WF1_RFIOP_2 11
AVDD33_WF1_TX 12
AVDD33_WF1_TRX 13
I2S_SDI 14
I2S_SDO 15
I2S_WS 16
I2S_CLK 17
I2C_SCLK 18
I2C_SD 19
SOC_CO_V12D_1 20
SOC_IO_V33D_1 21 DIG
SPI_CS1 22
SPI_CLK 23
SPI_MISO 24
SPI_MOSI 25
SPI_CS0 26
GPIO0 27
UART_TXD0 28
UART_RXD0 29

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 MT7628
Chip Name
Confidential B

AVDD33_TX_P0 30
EPHY
32 34 36 38 40 42 44 46
31 33 35 37 39 41 43 45

AVDD33_TX_P1234_1
AVDD33_COM
MDI_RN_P0

MDI_RN_P1

MDI_RN_P2
MDI_TN_P0

MDI_TN_P1

MDI_TN_P2
MDI_RP_P0

MDI_RP_P1

MDI_RP_P2
MDI_TP_P0

MDI_TP_P1

MDI_TP_P2

MDI_TP_P3
EPHY_VRT
Figure 2-5 MT7628KN DR-QFN Pin Diagram (left view)

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 MT7628
Chip Name
Confidential B

2.2.2 Right side view

PCIE_RXP0

VOUT_FB
PCIE_CKP0

PCIE_TXN0
PCIE_CKN0

PCIE_RXN0

PCIE_TXP0

DDRLDO
AVDD33_PCIE

AVDD12_PCIE

AVDD33_DDRLDO

AVSS33_SMPS_2

AVSS33_SMPS_1
PCIE_IO_VSS

104 102 100 98 96 94 92

103 101 99 97 95 93 91
PCIE PMU
90 LXBK_2
PMU 89 LXBK_1
88 AVDD33_SMPS_2
87 AVDD33_SMPS_1
86 SOC_IO_V33D_2
85 WLED_N
84 EPHY_LED0_N_JTDO
83 EPHY_LED1_N_JTDI
DIG 82 EPHY_LED2_N_JTMS
81 EPHY_LED3_N_JTCLK
80 EPHY_LED4_N_JTRST_N
79 DDR_IO_1V8D_4
78 DDR_IO_1V8D_3
77 DDR_IO_VREF_3
76 DDR_IO_VREF_2
75 SOC_CO_V12D_7
74 SOC_CO_V12D_6
DDR 73 DDR_IO_VREF_1
72 SOC_CO_V12D_5
71 SOC_CO_V12D_4
70 NC5
69 NC4
68 NC3
67 DDR_IO_1V8D_2
66 DDR_IO_1V8D_1
65 NC2
64 NC1
63 DDR_IO_VSS_3
62 DDR_IO_VSS_2

61 DDR_IO_VSS_1
USB
48 50 52 54 56 58
47 49 51 53 55 57 59 60
AVDD33_TX_P1234_2

SOC_CO_V12D_2

SOC_CO_V12D_3

AVDD33_USB
MDI_RN_P3

MDI_RN_P4
MDI_TN_P3

MDI_TN_P4
MDI_RP_P3

MDI_RP_P4

MDI_TP_P4

USB_VRT

USB_DM
USB_DP

Figure 2-6 MT7628KN DR-QFN Pin Diagram (right side view)

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 MT7628
Chip Name
Confidential B

2.2.3 Pin Description

Pins Name Type Driv. Description
RF
2 WF0_RFION_1 A WF0 main path RF I/O
3 WF0_RFION_2
4 WF0_RFIOP_1 A WF0 main path RF I/O
5 WF0_RFIOP_2
8 WF1_RFION_1 A WF1 main path RF I/O
9 WF1_RFION_2
10 WF1_RFIOP_1 A WF1 main path RF I/O
11 WF1_RFIOP_2
7 WF1_LNA_EXT A WF1 aux. path LNA input
1 WF0_LNA_EXT A WF0 aux. path LNA input
116 XTALIN I Crystal oscillator input
118 CLKOUTP O XO reference clock output
114 AVDD33_XTAL P 3.3V XTAL Power Supply Pin
115 AVS33_XTAL_1 G 3.3V XTAL Ground Pin
117 AVS33_XTAL_2
6 AVDD33_WF0_TX P 3.3V RF Channel 0 Suppoly Power
12 AVDD33_WF1_TX P 3.3V RF Channel 1 Suppoly Power
13 AVDD33_WF1_TRX P 1.65V to 3.3V RF Channel 1 Suppoly Power
113 AVDD33_WF_RFDIG P 1.65V to 3.3V RF DIG and AFE Suppoly Power
119 AVDD33_WF_SX P 1.65V to 3.3V RF Supply Power
120 AVDD33_WF0_TRX P 1.65V to 3.3V RF Channel 0 Suppoly Power
WLAN LED
85 WLED_N O 4 mA WLAN Activity LED
UART0 Lite
28 TXD0 O, IPD 4 mA UART0 Lite TXD
29 RXD0 I UART0 Lite RXD
UART1 Lite
111 TXD1 O, IPU 4 mA UART1 Lite TXD
112 RXD1 I UART1 Lite RXD
I2S
14 I2S_SDI I/O 4 mA I2S data input
15 I2S_SDO O, IPD 4 mA I2S data output
16 I2S_WS O 4 mA I2S word select
17 I2S_CLK I/O 4 mA I2S clock
I2C
19 I2C_SD I/O 4 mA I2C Data

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 MT7628
Chip Name
Confidential B

Pins Name Type Driv. Description

18 I2C_SCLK I/O 4 mA I2C Clock
SPI
24 SPI_MISO I/O 4 mA SPI Master input/Slave output
25 SPI_MOSI I/O, IPD 4 mA SPI Master output/Slave input
22 SPI_CLK O, IPU 4 mA SPI clock
26 SPI_CS0 O 4 mA SPI chip select0
22 SPI_CS1 O, IPD 4 mA SPI chip select1
GPIO
27 GPIO0 I/O, IPD 4 mA General Purpose I/O
5-Port EPHY
84 EPHY_LED0 _N_JTDO I/O 4 mA 10/100 PHY Port #0 activity LED, JTAG_TDO
83 EPHY_LED1 _N_JTDI I/O 4 mA 10/100 PHY Port #1 activity LED, JTAG_TDI
82 EPHY_LED2 _N_JTMS I/O 4 mA 10/100 PHY Port #2 activity LED, JTAG_TMS
81 EPHY_LED3 _N_JTCLK I/O 4 mA 10/100 PHY Port #3 activity LED, JTAG_CLK
80 EPHY_LED4 I/O, 4 mA 10/100 PHY Port #4 activity LED, JTAG_TRST_N
_N_JTRST_N
35 EPHY_VRT A Connect to an external resistor to provide accurate bias
current
31 MDI_RP_P0 A 10/100 PHY Port #0 RXN
32 MDI_RN_P0 A 10/100 PHY Port #0 RXP
33 MDI_TP_P0 A 10/100 PHY Port #0 TXN
34 MDI_TN_P0 A 10/100 PHY Port #0 TXP
37 MDI_TP_P1 A 10/100 PHY Port #1 RXN
39 MDI_TN_P1 A 10/100 PHY Port #1 RXP
40 MDI_RP_P1 A 10/100 PHY Port #1 TXN
41 MDI_RN_P1 A 10/100 PHY Port #1 TXP
42 MDI_RP_P2 A 10/100 PHY Port #2 RXN
43 MDI_RN_P2 A 10/100 PHY Port #2 RXP
44 MDI_TP_P2 A 10/100 PHY Port #2 TXN
45 MDI_TN_P2 A 10/100 PHY Port #2 TXP
46 MDI_TP_P3 A 10/100 PHY Port #3 RXN
47 MDI_TN_P3 A 10/100 PHY Port #3 RXP
48 MDI_RP_P3 A 10/100 PHY Port #3 TXN
49 MDI_RN_P3 A 10/100 PHY Port #3 TXP
51 MDI_RP_P4 A 10/100 PHY Port #4 RXN
52 MDI_RN_P4 A 10/100 PHY Port #4 RXP
53 MDI_TP_P4 A 10/100 PHY Port #4 TXN

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 MT7628
Chip Name
Confidential B

Pins Name Type Driv. Description

54 MDI_TN_P4 A 10/100 PHY Port #4 TXP
30 AVDD33_TX_P0 P 3.3V Supply Power for P0
36 AVDD33_COM P 3.3V Supply Power for EPHY COM
38 AVDD33_TX_P1234_1 P 3.3V Supply Power for P1 ~ P4
50 AVDD33_TX_P1234_2
Misc.
106 REF_CLKO O, IPD 4 mA Reference Clock Ouptut
108 PORST_N I Power on reset
107 WDT_RST_N O 4 mA Watchdog Reset
USB PHY
58 AVDD33_USB P 3.3 V USB PHY analog power supply
57 USB _VRT A Connect to an external 5.1 kΩ resistor for band-gap
reference circuit
60 USB_DM I/O USB Port0 data pin Data-
59 USB _DP I/O USB Port0 data pin Data+
PCIe PHY
105 PERST_N O, IPD 4mA PCIe device reset
98 PCIE_IO_VSS G PCIe Ground pin
101 AVDD12_PCIE P 1.2 V PCIE PHY digital power supply
104 AVDD33_PCIE P 3.3 V USB PHY analog power supply
103 PCIE_CKP0 O External reference clock output (positive)
102 PCIE_CKN0 O External reference clock output (negative)
97 PCIE_TXP0 I/O PCIe0 differential transmit TX -
96 PCIE_TXN0 I/O PCIe0 differential transmit TX -
99 PCIE_RXP0 I/O PCIe0 differential receiver RX -
100 PCIE_RXN0 I/O PCIe0 differential receiver RX -
PMU
89 LXBK_1 O Buck Switching node
90 LXBK_2
93 VOUT_FB A Buck vout feedback pin
87 AVDD33_SMPS_1 P Buck 3.3V Supply power
88 AVDD33_SMPS_2
91 AVSS33_SMPS_1 G Buck Gound pin
92 AVSS33_SMPS_2
94 AVDD33_DDRLDO P DDRLDO 3.3V Supply power
95 DDRLDO O DDRLDO 1.8V/2.5V output voltage
Power

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 MT7628
Chip Name
Confidential B

Pins Name Type Driv. Description

21 SOC_IO_V33D_1 P 3.3 V digital I/O power supply
86 SOC_IO_V33D_2
110 SOC_IO_V33D_3
20 SOC_CO _V12D_1 P 1.2 V digital core power supply
55 SOC_CO _V12D_2
56 SOC_CO _V12D_3
71 SOC_CO _V12D_4
72 SOC_CO _V12D_5
74 SOC_CO _V12D_6
75 SOC_CO _V12D_7
109 SOC_CO _V12D_8
EPAD GND G Ground pin

Total: 120 pins

Note:
IPD : Internal pull-down
IPU : Internal pull-up
I : Input
O : Output
IO : Bi-directional
P : Power
G : Ground
NC : Not connected

2.3 Pin Sharing Schemes

Some pins are shared with GPIO to provide maximum flexibility for system designers. The MT7628 provides up
to 41 GPIO pins. Users can configure GPIO1_MODE and GPIO2_MODE registers in the System Control block to
specify the pin function, or they can use the registers specified below. For more information, see the
Programmer’s Guide. Unless specified explicitly, all the GPIO pins are in input mode after reset.

2.3.1 GPIO pin share scheme

I/O Pad Group Normal Mode GPIO Mode
UART1 UART_RXD1 GPIO#46
UART_TXD1 GPIO#45
WLED_AN WLED_N (7628AN) GPIO#44
P0_LED_AN EPHY_LED0_N_JTDO (7628AN) GPIO#43
P1_LED_AN EPHY_LED1_N_JTDI (7628AN) GPIO#42
P2_LED_AN EPHY_LED2_N_JTMS (7628AN) GPIO#41
P3_LED_AN EPHY_LED3_N_JTCLK (7628AN) GPIO#40
P4_LED_AN EPHY_LED4_N_JTRST_N (7628AN) GPO#39
WDT WDT_RST_N GPO#38
REFCLK REF_CLKO GPIO#37

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 MT7628
Chip Name
Confidential B

I/O Pad Group Normal Mode GPIO Mode

PERST PERST_N GPIO#36
WLED_KN WLED_N (7628KN) GPIO#35
P0_LED_KN EPHY_LED0_N_JTDO (7628KN) GPIO#34
P1_LED_KN EPHY_LED1_N_JTDI (7628KN) GPIO#33
P2_LED_KN EPHY_LED2_N_JTMS (7628KN) GPIO#32
P3_LED_KN EPHY_LED3_N_JTCLK (7628KN) GPIO#31
P4_LED_KN EPHY_LED4_N_JTRST_N (7628KN) GPIO#30
SD MDI_TN_P4 GPIO#29
MDI_TP_P4 GPIO#28
MDI_RN_P4 GPIO#27
MDI_RP_P4 GPIO#26
MDI_RN_P3 GPIO#25
MDI_RP_P3 GPIO#24
MDI_TN_P3 GPIO#23
MDI_TP_P3 GPIO#22
UART2 MDI_TN_P2 GPIO#21
MDI_TP_P2 GPIO#20
PWM1 MDI_RN_P2 GPO#19
PWM0 MDI_RP_P2 GPO#18
SPIS MDI_RN_P1 GPIO#17
MDI_RP_P1 GPIO#16
MDI_TN_P1 GPO#15
MDI_TP_P1 GPIO#14
UART0 UART_RXD0 GPIO#13
UART_TXD0 GPIO#12
GPIO GPIO0 GPIO#11
SPI SPI_CS0 GPIO#10
SPI_MISO GPIO#9
SPI_MOSI GPIO#8
SPI_CLK GPIO#7
SPI_CS1 SPI_CS1 GPIO#6
I2C I2C_SD GPO#5
I2C_SCLK GPO#4
I2S I2S_CLK GPIO#3
I2S_WS GPIO#2
I2S_SDO GPIO#1
I2S_SDI GPO#0
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 MT7628
Chip Name
Confidential B

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2.3.2 UART1 pin share scheme

Controlled by the UART1_MODE register.
Pin Name 2’b00 2’b01 2’b10 2’b11
UART-Lite #1 GPIO PWM TRX_SW
UART1_RXD UART1_RXD GPIO#46 PWM_CH1
UART1_TXD UART1_TXD GPIO#45 PWM_CH0

2.3.3 MT7628AN EPHY LED pin share scheme

Controlled by the P#_LED_AN_MODE registers
Pin Name Bootstrapping Bootstrapping
(DBG_JTAG_MODE=1) (DBG_JTAG_MODE=0)
P4_LED_AN_MODE P4_LED_AN_MODE
=2’b00 =2’b01
EPHY_LED4_N_JTRST_N JTAG_RST_N EPHY_LED4_N GPIO#39
P3_LED_AN_MODE P3_LED_AN_MODE
=2’b00 =2’b01
EPHY_LED3_N_JTCLK JTAG_CLK EPHY_LED3_N GPIO#40
P2_LED_AN_MODE P2_LED_AN_MODE
=2’b00 =2’b01
EPHY_LED2_N_JTMS JTAG_TMS EPHY_LED2_N GPIO#41
P1_LED_AN_MODE P1_LED_AN_MODE
=2’b00 =2’b01
EPHY_LED1_N_JTDI JTAG_TDI EPHY_LED1_N GPIO#42
P0_LED_AN_MODE P0_LED_AN_MODE
=2’b00 =2’b01
EPHY_LED0_N_JTDO JTAG_TDO EPHY_LED0_N GPIO#43

2.3.4 MT7628AN WLAN LED pin share scheme

Controlled by the WLED_AN_MODE registers
Pin Name 2’b00 2’b01
WLED_N WLED_N GPIO#44

2.3.5 MT7628KN EPHY LED pin share scheme

Controlled by the P#_LED_KN_MODE registers
Pin Name Bootstrapping Bootstrapping
(DBG_JTAG_MODE=1) (DBG_JTAG_MODE=0)
P4_LED_KN_MODE P4_LED_KN_MODE
=2’b00 =2’b01

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Pin Name Bootstrapping Bootstrapping

(DBG_JTAG_MODE=1) (DBG_JTAG_MODE=0)
P4_LED_KN_MODE P4_LED_KN_MODE
=2’b00 =2’b01
EPHY_LED4_N_JTRST_N JTAG_RST_N EPHY_LED4_N GPIO#30
P3_LED_KN_MODE P3_LED_KN_MODE
=2’b00 =2’b01
EPHY_LED3_N_JTCLK JTAG_CLK EPHY_LED3_N GPIO#31
P2_LED_KN_MODE P2_LED_KN_MODE
=2’b00 =2’b01
EPHY_LED2_N_JTMS JTAG_TMS EPHY_LED2_N GPIO#32
P1_LED_KN_MODE P1_LED_KN_MODE
=2’b00 =2’b01
EPHY_LED1_N_JTDI JTAG_TDI EPHY_LED1_N GPIO#33
P0_LED_KN_MODE P0_LED_KN_MODE
=2’b00 =2’b01
EPHY_LED0_N_JTDO JTAG_TDO EPHY_LED0_N GPIO#34

2.3.6 MT7628KN WLAN LED pin share scheme

Controlled by the WLED_KN_MODE registers
Pin Name 2’b00 2’b01
WLED_N WLED_N GPIO#35

2.3.7 PERST_N pin share scheme

Controlled by the PERST_ MODE register.
Pin Name 1’b0 1’b1
PERST_N PERST_N GPIO#36

2.3.8 WDT_RST_N pin share scheme

Controlled by the WDT _MODE register.
Pin Name 1’b0 1’b1
WDT_RST_N WDT_RST_N GPIO#37

2.3.9 REF_CLKO pin share scheme

Controlled by the REFCLK _MODE register.
Pin Name 1’b0 1’b1
REF_CLKO REF_CLKO GPIO#38

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2.3.10 UART0 pin share scheme

Controlled by the UART0 _MODE register.
Pin Name 1’b0 1’b1
UART_TXD0 UART_TXD0 GPIO#12
UART_TXD0 UART_RXD0 GPIO#13

2.3.11 GPIO0 pin share scheme

Controlled by GPIO_MODE register.
Pin Name 2’b00 2’b01 2’b10 2’b11
GPIO0 GPIO#11 GPIO#11 REF_CLKO PERST_N

2.3.12 SPI pin share scheme

Controlled by SPI_ MODE register.
Pin Name 1’b0 1’b1
SPI_CLK SPI_CLK GPO#7
SPI_MOSI SPI_MOSI GPO#8
SPI_MISO SPI_MISO GPIO#9
SPI_CS0 SPI_CS0 GPIO#10

2.3.13 SPI_CS1 pin share scheme

Controlled by SPI_CS1_MODE register.
Pin Name 2’b00 2’b01 2’b10
SPI_CS1 SPI_CS1 GPIO#6 REF_CLKO

2.3.14 I2C pin share scheme

Controlled by I2C_MODE register.
Pin Name 2’b00 2’b01
I2C_SCLK I2C_SCLK GPIO#4
I2C_SD I2C_SD GPIO#5

2.3.15 I2S pin share scheme

Controlled by I2S_MODE register.
Pin Name 2’b00 2’b01 2’b10
I2S_SDI I2C_SCLK GPIO#0 PCMDRX
I2S_SDO I2C_SD GPIO#1 PCMDTX
I2S_WS I2C_SCLK GPIO#2 PCMCLK
I2S_CLK I2C_SD GPIO#3 PCMFS

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2.3.16 SD pin share scheme

Controlled by the EPHY_APGIO_AIO_EN[4:1] and SD_MODE registers
EPHY_APGIO_AIO_EN[4:1] EPHY_APGIO_AIO_EN[4:1]
=4’b0000 =4’b1111
Pin Name SD_MODE SD_MODE
=2’b00 =2’b01
MDI_TP_P3 MDI_TP_P3 SD_WP GPIO#22
MDI_TN_P3 MDI_TN_P3 SD_CD GPIO#23
MDI_RP_P3 MDI_RP_P3 SD_D1 GPIO#24
MDI_RN_P3 MDI_RN_P3 SD_D0 GPIO#25
MDI_RP_P4 MDI_RP_P4 SD_CLK GPIO#26
MDI_TN_P4 MDI_TN_P4 SD_D2 GPIO#27
MDI_RN_P4 MDI_RN_P4 SD_CMD GPIO#28
MDI_TP_P4 MDI_TP_P4 SD_D3 GPIO#29

2.3.17 UART2 pin share scheme

Controlled by the EPHY_APGIO_AIO_EN[4:1] and UART2_MODE registers
4’b0000 4’b1111
Pin Name 2’b00 2’b01 2’b10 2’b11
MDI_TP_P2 MDI_TP_P2 UART_TXD2 GPIO#20 PWM_CH2 SD_D5
MDI_TN_P2 MDI_TN_P2 UART_RXD2 GPIO#21 PWM_CH3 SD_D4

2.3.18 PWM_CH0 pin share scheme

Controlled by the EPHY_APGIO_AIO_EN[4:1] and PWM0_MODE registers
4’b0000 4’b1111
Pin Name 2’b00 2’b01 2’b10 2’b11
MDI_RP_P2 MDI_RP_P2 PWM_CH0 GPIO#18 SD_D7

2.3.19 PWM_CH1 pin share scheme

Controlled by the EPHY_APGIO_AIO_EN[4:1] and PWM1_MODE registers
4’b0000 4’b1111
Pin Name 2’b00 2’b01 2’b10 2’b11
MDI_RN_P2 MDI_RN_P2 PWM_CH1 GPIO#19 SD_D6

2.3.20 SPIS pin share scheme

Controlled by the EPHY_APGIO_AIO_EN[4:1] and SPIS_MODE registers
4’b0000 4’b1111
Pin Name 2’b00 2’b01 2’b10 2’b11

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4’b0000 4’b1111
Pin Name 2’b00 2’b01 2’b10 2’b11
MDI_TP_P1 MDI_TP_P1 SPIS_CS GPIO#14 PWM_CH0
MDI_TN_P1 MDI_TN_P1 SPIS_CLK GPIO#15 PWM_CH1
MDI_RP_P1 MDI_RP_P1 SPIS_MISO GPIO#16 UART_TXD2
MDI_RN_P1 MDI_RN_P1 SPIS_MOSI GPIO#17 UART_RXD2

2.3.21 Pin share function description

Pin Share Name I/O Pin Share Function description
PCMDTX O PCM Data Transmit
DATA signal sent from the PCM host to the external codec.
PCMDRX I PCM Data Receive
DATA signal sent from the external codec to the PCM host.
PCMCLK I/O PCM Clock
The clock signal can be generated by the PCM host (Output direction), or
provided by an external clock (input direction). The clock frequency should match
the slot configuration of the PCM host.
e.g.
4 slots, PCM clock out/in should be 256 kHz.
8 slots, PCM clock out/in should be 512 kHz.
16 slots, PCM clock out/in should be 1.024 MHz.
32 slots, PCM clock out/in should be 2.048 MHz.
64 slots, PCM clock out/in should be 4.096 MHz.
128 slots, PCM clock out/in should be 8.192 MHz.
PCMFS I/O PCM SYNC signal.
In our design, the direction of this signal is independent of the direction of
PCMCLK. Its direction and mode is configurable.
PWM_CH0 O Pulse Width Modulation Channle 0
PWM_CH1 O Pulse Width Modulation Channle 1
PWM_CH2 O Pulse Width Modulation Channle 2
PWM_CH3 O Pulse Width Modulation Channle 3

2.4 Bootstrapping Pins Description

Pin Name Boot Strapping Signal Description
Name
UART_TXD1 DBG_JTAG_MODE 0: JTAG_MODE
1: EPHY_LED (default)
PERST_N XTAL_FREQ_SEL 0: 25 MHz DIP
1: 40 MHz SMD

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Pin Name Boot Strapping Signal Description

Name
I2S_SDO DRAM_TYPE 1: DDR1
0: DDR2
[note] This pin is valid for MT7628AN only. It needs to be pull-low for
7628KN which only supports DDR1.
{SPI_CS1 CHIP_MODE[2:0] A vector to set chip function/test/debug modes.
SPI_CLK, 000: Boot from PLL (boot from SPI 3-Byte Addr)
SPI_MOSI} 001: Boot from PLL (boot from SPI 4-Byte Addr)
010: Boot from XTAL (boot from SPI 3-Byte Addr)
011: Boot from XTAL (boot from SPI 4-Byte Addr)
PAD_TXD0 EXT_BGCK 1: Test Mode
0: Normal (default)

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3. Maximum Ratings and Operating Conditions

3.1 Absolute Maximum Ratings

I/O supply voltage 3.63 V
Input, Output, or I/O Voltage GND -0.3 V to Vcc +0.3 V

Table 3-1 Absolute Maximum Ratings

3.2 Maximum Temperatures

Maximum Junction Temperature (Plastic Package) 125 °C
Maximum Lead Temperature (Soldering 10 s) 260 °C

Table 3-2 Maximum Temperatures

3.3 Operating Conditions

I/O supply voltage 3.3 V +/- 10%

DDR1 supply voltage 2.5 V +/- 5%
DDR2 supply voltage 1.8 V +/- 5%
Core supply voltage 1.2 V +/- 10%
Ambient Temperature Range -20 to 55 °C

Table 3-3 Operating Conditions

3.4 Thermal Characteristics

Thermal characteristics without an external heat sink in still air conditions.

MT7628KN:
Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB 26.1°C/W
Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB 17.72°C/W
Thermal Resistance θJC (°C /W) for JEDEC 6.5°C/W
Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB 1.81°C/W
Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB 1.18°C/W

MT7628AN:
Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB 27.01°C/W
Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB 18.15°C/W
Thermal Resistance θJC (°C /W) for JEDEC 6.9°C/W
Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB 2.41 °C/W
Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB 1.51 °C/W

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Table 3-4 Thermal Characteristics

3.5 Storage Conditions

The calculated shelf life in a sealed bag is 12 months if stored between 0 °C and 40 °C at less than 90% relative
humidity (RH). After the bag is opened, devices that are subjected to solder reflow or other high temperature
processes must be handled in the following manner:
 Mounted within 168 hours of factory conditions, i.e. < 30 °C at 60% RH.
 Storage humidity needs to maintained at < 10% RH.
 Baking is necessary if the customer exposes the component to air for over 168 hrs, baking conditions: 125
°C for 8 hrs.

3.6 External Xtal Specfication

Frequency 25 MHz/ 40 Mhz
Frequency offset +/-20 ppm
VIH/VIL Vcc-0.3 V/0.3 V
Duty cycle 45% to 55%

Table 3-5 External Xtal Specifications

3.7 DC Electrical Characteristics

Parameters Sym Conditions Min Typ Max Unit

3.3 V supply voltage (IO) Vddc33 2.97 3.3 3.63 V
2.5V supply voltage (DDR1) Vdd25 2.375 2.5 2.625 V
1.8 V supply voltage (DDR2) Vdd18 1.71 1.8 1.89 V
1.2 V supply voltage Vdd12 1.08 1.2 1.32 V
3.3 V current consumption Icc33 mA
1.5 V current consumption Icc15 mA
1.2 V current consumption Icc12 mA
DDR2 Current Icc18 mA

Table 3-6 DC Electrical Characteristics

Vdd=2.5V Typ
Min Max
(DDR2)
Vdd 2.375 2.5 2.625
VIH VREF+0.15 Vdd25+0.3
VIL -0.3 VREF-0.15
VOH 0.8*Vdd25
VOL 0.2*Vdd25
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IOL
IOH

Table 3-7 Vdd 2.5V Electrical Characteristics

Vdd=1.8V Typ
Min Max
(DDR2)
Vdd 1.71 1.8 1.89
VIH VREF+0.125 Vdd18+0.3
VIL -0.3 VREF-0.125
VOH 1.42
VOL 0.28
IOL
IOH

Table 3-8 Vdd 1.8V Electrical Characteristics

Vdd=3.3V Min Typ Max

Vdd 2.97V 3.3V 3.63V
VIH 2.0V Vdd33+0.3
VIL -0.3 0.8V
VOH 2.4V
VOL 0.4V
IOL
IOH

Table 3-9 Vdd 3.3V Electrical Characteristics

3.8 AC Electrical Characteristics

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3.8.1 DDR2 SDRAM Interface

The DDR2 SDRAM interface complies with 200 MHz timing requirements for standard DDR2 SDRAM. The
interface drivers are SSTL_18 drivers matching the EIA/JEDEC standard JESD8-15A.
tCH tCL
CLK
CLK#
tIS tIH
MCS_N
tIS tIH
MRAS_N
tIS tIH
MCAS_N
tIS tIH
MWE_N
tIS tIH
MA0 to MA13
tIS tIH
MBA0, MBA1

Figure 3-1 DDR2 SDRAM Command

tWPRE tDQSH tDQSL tWPST

MDQS
tDS tDH

MD D1 D2 D3 D4

tDS tDH

MDQM

Figure 3-2 DDR2 SDRAM Write data

tRPRE tRPST

MDQS

MD D1 D2 D3

tDQSQ (max) tQH

Figure 3-3 DDR2 SDRAM Read data

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Symbol Description Min Max Unit Remark

tCK(avg) Clock cycle time 5 - ns
tAC DQ output access time from SDRAM CLK -0.6 0.6 ns
tDQSCK DQS output access time from SDRAM CLK -0.5 0.5 ns
tCH SDRAM CLK high pulse width 0.48 0.52 tCK(avg)
tCL SDRAM CLK low pulse width 0.48 0.52 tCK(avg)
tHP SDRAM CLK half period Min(tCH,tCL) - ns
tIS Address and control input setup time 0.75 - ns
tIH Address and control input hold time 0.75 - ns
tDQSQ Data skew of DQS and associated DQ - 0.4 ns
tQH DQ/DQS output hold time from DQS tHP-0.5 - ns
tRPRE DQS read preamble 0.9 1.1 tCK
tRPST DQS read postamble 0.4 0.6 tCK
tDQSS DQS rising edge to CK rising edge -0.25 0.25 tCK
tDQSH DQS input-high pulse width 0.35 - tCK
tDQSL DQS input-low pulse width 0.35 - tCK
tDSS DQS falling edge to SDRAM CLK setup time 0.2 - tCK
tDSH DQS falling edge hold time from SDRAM CLK 0.2 - tCK
tWPRE DQS write preamble 0.35 - tCK
tWPST DQS write postamble 0.4 0.6 tCK
tDS DQ and DQM input setup time *0.4 - ns
tDH DQ and DQM input hold time *0.4 - ns

Table 3-10 DDR2 SDRAM Interface Diagram Key

NOTE: Depends on slew rate of DQS and DQ/DQM for single ended DQS.

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3.8.2 SPI Interface

Write operation (driven by clock rising edge)

SPI_CLK

SPI_CS

SPI_MOSI

t_SPI_OVLD (max) T_SPI_OVLD (min)

Read operation (Driven by clock rising edge (slave-device) and latched by clock rising edge)

SPI_CLK

SPI_CS

SPI_MISO

t_SPI_IS t_SPI_IH
NOTE: 1) SPI_CLK is a gated clock.
2) SPI_CS is controlled by software

Figure 3-4 SPI Interface

Symbol Description Min Max Unit Remark

t_SPI_IS Setup time for SPI input 6.0 - ns
t_SPI_IH Hold time for SPI input -1.0 - ns
t_SPI_OVLD SPI_CLK to SPI output valid -2.0 3.0 ns output load: 5 pF

Table 3-11 SPI Interface Diagram Key

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2
3.8.3 I S Interface

Transmitter

SCK

WS & SD

t_I2S_OVLD (min) t_I2S_OVLD (max)

Receiver

SCK

WS & SD

t_I2S_IS t_I2S_IH

Figure-3-5 I2S Interface

Symbol Description Min Max Unit Remark

t_I2S_IS Setup time for I2S input 3.5 - ns
(data & WS)
t_I2S_IH Hold time for I2S input 0.5 - ns
(data & WS)
t_I2S_OVLD I2S_CLK to I2S output 2.5 10.0 ns output load: 5 pF
(data & WS) valid

Table 3-12 I2S Interface Diagram Key

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3.8.4 PCM Interface

PCMCLK

DTX

t_PCM_OVLD

PCMCLK

DRX &
FSYNC

t_PCM_IS t_PCM_IH

Figure 3-6 PCM Interface

Symbol Description Min Max Unit Remark

t_PCM_IS Setup time for PCM input to 3.0 - ns
PCM_CLK fall
t_PCM_IH Hold time for PCM input to PCM_CLK 1.0 - ns
fall
t_PCM_OVLD PCM_CLK rise to PCM output valid 10.0 35.0 ns output load: 5 pF

Table 3-13 PCM Interface Diagram Key

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3.8.5 Power On Sequence

Figure 3-7 Power ON Sequence

Table 3-14 Power ON Sequence Diagram Key

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3.9 Package Physical Dimensions

3.9.1 DR-QFN (10 mm x 10 mm) 128 pins

3.9.1.1 Top View

Figure 3-8 Top View

3.9.1.3 “B” Expanded

3.9.1.2 Side View

Figure 3-9 Side View

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Figure 3-10 “B” Expanded

3.9.1.5 Package Diagram Key

3.9.1.4 Bottom View

Figure 3-11 Botton view

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3.9.2 DR-QFN (12 mm x 12 mm) 156 pins

3.9.2.1 Top View

Figure 3-12 Top View

3.9.2.2 Side View 3.9.2.3 “B” Expanded

Figure 3-13 Side View

Figure 3-14 “B” Expanded

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3.9.2.4 Bottom View

Figure 3-15 Bottom View

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3.9.2.5 Package Diagram Key

3.9.3 MT7628 AN/KN marking

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MEDIATEK
MT7628AN
YYWW-XXXX
LLLLLLLLL

YYWW: Date code

LLLLLLLLL : Lot number
“.” : Pin #1 dot
Figure 3-16 MT7620AN top marking

MEDIATEK
MT7628KN
YYWW-XXXX
LLLLLLLLL

YYWW: Date code

LLLLLLLLLL : Lot number
“.” : Pin #1 dot

Figure 3-17 MT7628KN top marking

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3.9.4 Reflow profile guideline

Figure 3-18 Reflow profile for MT7628

Notes;
1. Reflow profile guideline is designed for SnAgCulead-free solder paste.
2. Reflow temperature is defined at the solder ball of package/or the lead of package.
3. MTK would recommend customer following the solder paste vendor’s guideline to design a profile
appropriate your line and products.
4. Appropriate N2 atmosphere is recommended since it would widen the process window and mitigate the risk
for having solder open issues.

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4. Abbreviations
Abbrev. Description Abbrev. Description
AC Access Category CPU Central Processing Unit
ACK Acknowledge/ Acknowledgement CRC Cyclic Redundancy Check
ACPR Adjacent Channel Power Ratio CSR Control Status Register
AD/DA Analog to Digital/Digital to Analog CTS Clear to Send
converter CW Contention Window
ADC Analog-to-Digital Converter CWmax Maximum Contention Window
AES Advanced Encryption Standard CWmin Minimum Contention Window
AGC Auto Gain Control DAC Digital-To-Analog Converter
AIFS Arbitration Inter-Frame Space DCF Distributed Coordination Function
AIFSN Arbitration Inter-Frame Spacing DDONE DMA Done
Number
DDR Double Data Rate
ALC Asynchronous Layered Coding
DFT Discrete Fourier Transform
A-MPDU Aggregate MAC Protocol Data Unit
DIFS DCF Inter-Frame Space
A-MSDU Aggregation of MAC Service Data
DMA Direct Memory Access
Units
DSP Digital Signal Processor
AP Access Point
DW DWORD
ASIC Application-Specific Integrated Circuit
EAP Expert Antenna Processor
ASME American Society of Mechanical
Engineers EDCA Enhanced Distributed Channel Access
ASYNC Asynchronous EECS EEPROM chip select
BA Block Acknowledgement EEDI EEPROM data input
BAC Block Acknowledgement Control EEDO EEPROM data output
BAR Base Address Register EEPROM Electrically Erasable Programmable
Read-Only Memory
BBP Baseband Processor
eFUSE electrical Fuse
BGSEL Band Gap Select
EESK EEPROM source clock
BIST Built-In Self-Test
EIFS Extended Inter-Frame Space
BSC Basic Spacing between Centers
EIV Extend Initialization Vector
BJT
EVM Error Vector Magnitude
BSSID Basic Service Set Identifier
FDS Frequency Domain Spreading
BW Bandwidth
FEM Front-End Module
CCA Clear Channel Assessment
FEQ Frequency Equalization
CCK Complementary Code Keying
FIFO First In First Out
CCMP Counter Mode with Cipher Block
Chaining Message Authentication FSM Finite-State Machine
Code Protocol GF Green Field
CCX Cisco Compatible Extensions GND Ground
CF-END Control Frame End GP General Purpose
CF-ACK Control Frame Acknowledgement GPO General Purpose Output
CLK Clock GPIO General Purpose Input/Output

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Abbrev. Description Abbrev. Description

HCCA HCF Controlled Channel Access NAV Network Allocation Vector
HCF Hybrid Coordination Function NAS Network-Attached Server
HT High Throughput NAT Network Address Translation
HTC High Throughput Control NDP Null Data Packet
ICV Integrity Check Value NVM Non-Volatile Memory
IFS Inter-Frame Space ODT On-die Termination
iNIC Intelligent Network Interface Card Oen Output Enable
IV Initialization Vector OFDM Orthogonal Frequency-Division
2
IC Inter-Integrated Circuit Multiplexing
2
IS Integrated Inter-Chip Sound OSC Open Sound Control
I/O Input/Output PA Power Amplifier
IPI Idle Power Indicator PAPE Provider Authentication Policy
Extension
IQ In phase/Quadrature phase
PBC Push Button Configuration
JEDEC Joint Electron Devices Engineering
Council PBF Packet Buffer
JTAG Joint Test Action Group PCB Printed Circuit Board
kbps kilo (1000) bits per second PCF Point Coordination Function
KB Kilo (1024) Bytes PCM Pulse-Code Modulation
LDO Low-Dropout Regulator PHY Physical Layer
LDODIG LDO for DIGital part output voltage PIFS PCF Interframe Space
LED Light-Emitting Diode PLCP Physical Layer Convergence Protocol
LNA Low Noise Amplifier PLL Phase-Locked Loop
LO Local Oscillator PME Physical Medium Entities
L-SIG Legacy Signal Field PMU Power Management Unit
MAC Medium Access Control PN Packet Number
MCU Microcontroller Unit PROM Programmable Read-Only Memory
MCS Modulation and Coding Scheme PSDU Physical layer Service Data Unit
MDC Management Data Clock PSI Power supply Strength Indication
MDIO Management Data Input/Output PSM Power Save Mode
MEM Memory PTN Packet Transport Network
MFB MCS Feedback QoS Quality of Service
MFS MFB Sequence RDG Reverse Direction Grant
MIC Message Integrity Code RAM Random Access Memory
MIMO Multiple-Input Multiple-Output RF Radio Frequency
MLNA Monolithic Low Noise Amplifier RGMII Reduced Gigabit Media Independent
Interface
MM Mixed Mode
RH Relative Humidity
MOSFET Metal Oxide Semiconductor Field
Effect Transistor RoHS Restriction on Hazardous Substances
MPDU MAC Protocol Data Units ROM Read-Only Memory
MSB Most Significant Bit

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Abbrev. Description Abbrev. Description

RSSI Received Signal Strength Indication TSSI Transmit Signal Strength Indication
(Indicator) Tx Transmit
RTS Request to Send TxBF Transmit Beamforming
RvMII Reverse Media Independent Interface TXD Transmitted Data
Rx Receive TXDAC Transmit Digital-Analog Converter
RXD Received Data TXINFO Transmit Information
RXINFO Receive Information TXOP Opportunity to Transmit
RXWI Receive Wireless Information TXWI Tx Wireless Information
S Stream UART Universal Asynchronous Rx/ Tx
SDXC Secure Digital eXtended Capacity USB Universal Serial Bus
SDIO Secure Digital Input Output UTIF Universal Test Interface
SDRAM Synchronous Dynamic Random Access VGA Variable Gain Amplifier
Memory
VCO Voltage Controlled Amplifier
SEC Security
VIH High Level Input Voltage
SGI Short Guard Interval
VIL Low Level Input Voltage
SIFS Short Inter-Frame Space
VoIP Voice over IP
SoC System-on-a-Chip
WCID Wireless Client Identification
SPI Serial Peripheral Interface
WEP Wired Equivalent
SRAM Static Random Access Memory
WI Wireless Information
SSCG Spread Spectrum Clock Generator
WIV Wireless Information Valid
STBC Space–Time Block Code
WMM Wi-Fi Multimedia
SW Switch Regulator
WPA Wi-Fi Protected Access
TA Transmitter Address
WPDMA Wireless Polarization Division Multiple
TBTT Target Beacon Transmission Time Access
TDLS Tunnel Direct Link Setup WS Word Select
TKIP Temporal Key Integrity Protocol
TRSW Tx/Rx Switch
TSF Timing Synchronization Function

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5. Revision History

Rev Date Description

1.0 2012/07/09 Initial Release
1.1 2012/07/18 Update SPI_WP/SPI_HOLD GPO table
1.2 2012/08/20 Fix DRQFN internal pad size typo
1.3 2012/09/12 Add IR reflow guideline

This product is not designed for use in medical and/or life support applications. Do not use this product in these
types of equipment or applications. This document is subject to change without notice and Ralink assumes no
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responsibility for any inaccuracies that may be contained in this document. Ralink reserves the right to make
changes in its products to improve function, performance, reliability, and to attempt to supply the best product
possible.

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