IP Verification JD - Cadence Design Systems, Noida
IP Verification JD - Cadence Design Systems, Noida
• The person should be an Electrical, Electronics or Computer Science Engineer with very good
understanding of HDLs (Verilog and/ or VHDL).
• Prior experience in simulation/emulation using these languages. He/ she should have a good
working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/
verification problems using these tools.
• Experience in process automation with scripting.
• Experience with System Verilog, C++, UVM.
• Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with
a Hardware Verification Language (HVL) like System Verilog.
• Experience designing and implementing complex functional verification environments is
required.
• Must have solid experience on any of the protocols like Ethernet, PCIe, DDR, USB3/4,
DisplayPort (DP), MIPI, UCIe, NVMe, HDMI.