DATA SHEET

MOS INTEGRATED CIRCUIT

V850E/PHC3

V850E/PHC3
32-Bit Single-Chip Microcontroller

DESCRIPTION
With its high performance V850E CPU core and its compact feature set the V850E/PHC3 is especially
suited for embedded control applications.
The V850E/PHC3 devices provide an excellent combination of general purpose peripheral functions
like serial communication interfaces, timers/counters, measurement and control functions, with dedi-
cated motor control timers and full CAN network support.
Thus equipped, the V850E/PHC3 product is ideally suited for automotive control applications, such as
electric power steering (EPS). It is also an excellent choice for other embedded applications where a
combination of sophisticated peripheral functions and CAN network support is required.

FEATURE

• 32-bit RISC CPU incl. single-precision FPU • Auxiliary Frequency Output

• Internal flash memory: 480 KB • I/O lines: 76 + 5 input only
• Internal RAM: 32 KB • Clock Monitor
• Data Flash: 32 KB • Power Save Mode: HALT
• Operating Clocks • On Chip Debug: N-Wire
CPU Frequency: 80 MHz • Power supply:
MainOsc: operates on 16MHz crystal 3.3V +/- 0.3V and 1.5V +/- 10%
2 x PLL: ratio 5, 2 • Temperature range: -40°C to +125°C
• Timers • Package: 144 pin LQFP
10 ch 16-bit general purpose timer/counter
2 ch 16-bit timer for Motor Control
2 ch 16-bit general purpose timer/counter with
encoder function
• A/D Converter: 2 x 10 channels
10 bit resolution
• CAN Interface: 2 channel (AFCAN)
• Serial Interfaces: 6 channels
- synchronous: 2 channels (CSIB)
- synchronous with FIFO: 2 channels (CSIE)
- asynchronous: 2 channels (UARTC)
• DMA: 10 channels

ORDERING INFORMATION

Product Name Product Family Package Flash Data Flash RAM

μPD70F3485GJ(A2)-GAE V850E/PHC3 144 pin LQFP 480 KB 32 KB 32 KB

The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative
for availability and additional information.

© NEC Electronics 2010

Document No. U19538EE2V0DS00
Date Published: February 2010
V850E/PHC3

Notes for CMOS Devices

1. Precaution against ESD for semiconductors
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2. Handling of unused input pins for CMOS

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to
the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

3. Status before initialization of MOS devices

Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset
signal is received. Reset operation must be executed immediately after power-on for devices having
reset function.

2 DATA SHEET U19538EE2V0DS00

 V850E/PHC3

Legal Notes
• The information in this document is current as of February 2010. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC sales represen-
tative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
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may appear in this document.
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intellectual property rights of third parties by or arising from the use of NEC Electronics products
listed in this document or any other liability arising from the use of such NEC Electronics products.
No license, express, implied or otherwise, is granted under any patents, copyrights or other intellec-
tual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorpora-
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under the full responsibility of customer. NEC Electronics assumes no responsibility for any losses
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and “Specific”.
The "Specific" quality grade applies only to NEC Electronics products developed based on a
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must check the quality grade of each NEC Electronics product before using it in a particular
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"Standard": Computers, office equipment, communications equipment, test and
measurement equipment, audio and visual equipment, home electronic
appliances, machine tools, personal electronic equipment and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control
systems, anti-disaster systems, anti-crime systems, safety equipment and
medical equipment (not specifically designed for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control
systems, life support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is “Standard” unless otherwise expressly specified in
NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products
in applications not intended by NEC Electronics, they must contact NEC Electronics sales
representative in advance to determine NEC Electronics 's willingness to support a given application.

Notes: 1. "NEC Electronics" as used in this statement means NEC Electronics Corporation and also
includes its majority-owned subsidiaries.
2. "NEC Electronics products" means any product developed or manufactured by or for NEC
Electronics (as defined above).
3. SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several coun-
tries including the United States and Japan. This product uses SuperFlash® technology
licensed from Silicon Storage Technology, Inc.

DATA SHEET U19538EE2V0DS00 3

V850E/PHC3

Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and com-
ponents, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.) NEC Electronics Hong Kong Ltd.

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4 DATA SHEET U19538EE2V0DS00

 V850E/PHC3

Table of Contents

1. Electrical Target Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.2 Pin Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5.3 Operation and HALT Mode Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.6.1 Power Supply Turning On / Interception Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6.2 Reset And Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6.3 Clocked Serial Interface B (CSIB) Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.4 Clocked Serial Interface E (CSIE) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.6.5 UARTC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.6 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.7 AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.8 Flash Memory Programming Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2. Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 Package Dimension of µPD70F3485GJ(A2)-GAE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DATA SHEET U19538EE2V0DS00 5

V850E/PHC3
1. Electrical Target Specification

1.1 Absolute Maximum Ratings

Ta = 25°C
VSS15 = CVSS= VSS30 = AVSS0,1 = 0V

Table 1-1: Absolute Maximum Ratings

Parameter Symbol Conditions Ratings Unit
VDD15 -0.5 to +2.0 V
CVDD -0.5 to +2.0 V
Supply voltage
VDD30 -0.5 to +4.6 V
AVDD -0.5 to +4.6 V

Input voltage VI The pin X1 is excluded. -0.5 to VDD30+0.3 a V

Analog input ANI00 to ANI09

VIN -0.3 to AVDD+0.3 a V
voltage ANI10 to ANI19
A/D Converter AVREF0,1 -0.3 to AVDD+0.3 a V

High level For 1 pin 1 pin -4.0 mA

IOH
output current Total of all pins b Total -75 mA

Low level For 1 pin 1 pin 4.0 mA

IOL
output current Total of all pins b Total 75 mA

Operating Normal operating mode (Package) c -40 to +125 °C

ambient Ta Flash programming mode, when flash memory is
temperature -40 to +125 °C
written. (Package) c

Storage In tray. -65 to +125 °C

Tstg
temperature Off tray, mounted but not powered. -65 to + 150 °C
a. Please do not exceed absolute maximum rating (max. +4.6V) of each power supply voltage.
b. Total sum of all input and output currents of all pins. Please observe addtionally the Table 1-7 on page 11,
footnotes b. and c.
c. Measured on JEDEC 4 layer PCB.

Cautions: 1. Do not directly connect output (or I/O) pins of IC products to each other, or to
VDD, VSS, and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even
momentarily for any parameter. That is, the absolute maximum ratings are rated
values at which the product is on the verge of suffering physical damage, and
therefore the product must be used under conditions that ensure that the abso-
lute maximum ratings are not exceeded. The ratings and conditions shown below
for DC characteristics and AC characteristics are within the range for normal
operation and quality assurance.

6 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
1.2 Pin Capacitance

Ta = 25°C
VDD15 = CVDD = VDD30 = AVDD = VSS15 = CVSS = VSS30 = AVSS0,1 = 0V

Table 1-2: Pin Capacitance

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input capacitance CI fc=1MHz 15 pF
Input/output
CIO All pins are at 0V excluding the pin that is measured. 15 pF
capacitance
Output capacitance CO 15 pF

1.3 Operation Conditions

Table 1-3: Operating Conditions

Internal system
Operating Temperature Power Supply Voltage
clock frequency
VDD15 = CVDD = 1.5V±0.15V
80MHz Ta = -40 to +125°C Normal operating mode
VDD30 = AVDD = 3.3V±0.3V

DATA SHEET U19538EE2V0DS00 7

V850E/PHC3
1.4 Oscillator Characteristics

Figure 1-1: Oscillator Recommendations

X1 X2

C1' C2'

Remark: Values of capacitors C1’ and C2’ depend on used crystal and must be specified in coopera-
tion with the crystal manufacturer.

Cautions: 1. External clock input is prohibited.

2. Wire as follows in the area enclosed by the broken lines in the above figure to
avoid an adverse effect from wiring capacitance.
• Place the oscillation circuit as close as possible to X1 and X2 pins.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating cur-
rent flows.
• Always make the ground point of the oscillator capacitor the same potential as
CVSS15.
• Do not ground the capacitor to a ground pattern through which a high current
flows.
• Do not fetch signals from the oscillator.

Table 1-4: Operating Conditions

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Oscillation frequency fOSC 16 MHz
The oscillation stabilization time depends
on the crystal and circuit and must be
specified in cooperation with the crys-
tal manufacturer.
Ensure that all conditions and tolerances
Oscillation stabilization of all components are considered for deter-
tOST n/a n/a n/a
time mination of oscillation stabilization time:
Resistance value
Capacity value
Voltage
Temperature
Manufacturing range
Internal digital counter, counting with fosc
PLL lockup time PSTC
(fx=fosc) frequency. 214/fx s

8 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
1.5 DC Characteristics

1.5.1 Input/Output Level

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V

Table 1-5: Input/Output Level

Parameter Symbol Conditions MIN. TYP. MAX. Unit
DDI, DMS, DCK 0.7·VDD30 VDD30+0.3 V
Input P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11 0.7·VDD30 VDD30+0.3 V
voltage, VIH
high DRST 0.75·VDD30 VDD30+0.3 V
MODE0, MODE1, RESET 0.8·VDD30 VDD30+0.3 V
DDI, DMS, DCK -0.5 0.3·VDD30 V
Input P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, -0.5 0.3·VDD30 V
voltage, VIL
low DRST -0.5 0.3·VDD30 V
MODE0, MODE1, RESET -0.5 0.2·VDD30 V
Output IOH=-2.5 mA a VDD30-1.0 V
voltage, VOH
high IOH=-0.1 mA VDD30-0.4 V
Output IOL=2.5mA a 0.8 V
voltage, VOL
low IOL=0.1mA 0.4 V
Build in
pull down RL DRST pin only 10 50 120 KΩ
resistor
a. Max ± 2.5 mA x 12 of output current simultaneously. Only the output port pins have to be considered.

DATA SHEET U19538EE2V0DS00 9

V850E/PHC3
1.5.2 Pin Leakage Current

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V

Table 1-6: Pin Leakage Current

Parameter Symbol Conditions MIN. TYP. MAX. Unit
All pins except
VI = VDD30 10.0 µA
ANI00 to ANI09, ANI10 to ANI19
ANI00 to ANI09, ANI10 to ANI19
1.0 µA
Input leakage VI = AVDD -40°C < Ta ≤ 90°C
ILIH ANI00 to
current, high ANI00 to ANI09, ANI10 to ANI19
ANI09, 1.2 µA
+90°C < Ta ≤ 95°C
ANI10 to
ANI19 ANI00 to ANI09, ANI10 to ANI19
3.0 µA
+95°C < Ta ≤ 125°C
All pins except
Input leakage VI = 0 V -10.0 µA
ILIL ANI00 to ANI09, ANI10 to ANI19
current, low
VI = 0 V ANI00 to ANI09, ANI10 to ANI19 -1.0 µA
Output leakage
ILOH VO = VDD30 All pins 10.0 µA
current, high
Output leakage
ILOL VO = 0 V All pins -10.0 µA
current, low

10 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
1.5.3 Operation and HALT Mode Supply Current

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V

Table 1-7: Power Supply Current

Parameter Conditions Symbol TYP.a MAX. Unit

VDD15, CVDD
IDD15 130 245 mA
Normal Operation fCPU = 80MHz
mode
VDD30b, c IDD30 21 mA

Supply VDD15, CVDD

IDDF15 140 265 mA
current Flash programming fCPU = 80MHz
mode
VDD30b, c IDDF30 46 mA

VDD15, CVDD
Halt mode IDDH15 122 227 mA
fCPU = 80MHz

a. The typical value is a reference value at Ta = 25 °C, VDD15 = 1.5 V and VDD30 = 3.3 V
b. No external loads considered (CL = 0 pF). External loads cause additional pin currents. Pin current
for each pin can be calculated according to following formular:

Ipin [mA] = 0.0057[V] × CL[pF] × f [MHz]

IDD30_total = Σ (Ipin) + IDD30

Where CL is the onboard load capacitance and f is the average pin toggle frequency. Load-depen-
dent pin currents must be summed up and added to IDD30. The maximum value for IDD30_total must
not exceed 75mA.

Example:
Only the pin A, B and C may operate in output mode, with the following conditions.
pin A: 8 MHz toogle frequency, on board load capacity CLA = 30 pF
pin B: 2 MHz toogle frequency, on board load capacity CLB = 40 pF
pin C: 1 MHz toogle frequency, on board load capacity CLC = 50 pF

IDD30_total, the VDD30 supply current (in normal operation mode), is then calculated as follows:

IDD30_total = Ipin_A + Ipin_B + Ipin_C + IDD3

= (0.0057 × 30 × 8) mA + (0.0057 × 40 ×2) mA+ (0.0057 × 50 × 1) mA + 21 mA
= 23.109 mA

c. Stationary DC load currents of the port pins (IOH/IOL) are not included (e.g. current which flows
through external pull-down / pull-up resistors). Ensure that the sum of VDD30 supply current from
above calculation formula and stationary DC load current of ports (IOH/IOL) will be less than 75 mA.
(refer to 1.1 Absolute Maximum Ratings)

DATA SHEET U19538EE2V0DS00 11

V850E/PHC3
1.6 AC Characteristics

AC Test Input Measurement Points,

VIH VIH
Measurement points
VIL VIL

AC Test Output Measurement Points

VOH VOH
Measurement points
VOL VOL

Load Conditions

DUT
CL = 35 pF

Caution: If the load capacitance exceeds 35 pF due to the circuit configuration, bring the load
capacitance of the device to 35 pF or less by inserting a buffer or by some other
means.

12 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
1.6.1 Power Supply Turning On / Interception Timing

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V

Table 1-8: Turning On / Interception Timing

Parameter Symbol Conditions MIN. MAX. Unit
VDD15 to VDD30 tRLI 0 1 s
VDD30 to VDD15 tRIL 0 1 s

VDD15 to RESET tRLR 0.5 + tOSC a ms

VDD30 to RESET tRIR 0.5 + tOSC a ms

VDD30 to MODE1-0 tRIM 0.2 ms

MODE1-0 to RESET tRMR 0 ns
RESET to MODE1-0 tFRM 0 ns
RESET to VDD30 tFRI 500 ns
RESET to VDD15 tFRL 500 ns
VDD30 to VDD15 tFLI 0 1 s
VDD15 to VDD30 tFIL 0 1 s

a. tOSC depends on the external oscillator's stabilization time, crystal type and circuit and should be specified /
evaluated in cooperation with the oscillator manufacturer

Figure 1-2: Turning On / Interception Timing

1.35V 1.35V
VDD15
(CVDD)

tRIL tRLI tFLI tFIL

VDD30 3.0V 3.0V

(AVDD)
tRIR tFRI

tRLR tFRL

RESET
DRST VIL VIL

tRMR tFRM

VIH VIH

Mode3-0 VIL

tRIM

DATA SHEET U19538EE2V0DS00 13

V850E/PHC3
1.6.2 Reset And Interrupt Timing

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V

Table 1-9: Reset And Interrupt Timing

Parameter Symbol Conditions MIN. MAX. Unit

RESET input low level width tWRSL except for power on 500 ns

NMI input low level width tWNIL (analog filter) 500 ns

NMI input high level width tWNIH (analog filter) 500 ns

n=0,1 (analog filter) 500 ns

INTPn input low level width tWITL
Sampling
n=2...12 (digital filter) ns
clock × 5T

n=0,1 (analog filter) 500 ns

INTPn input high level width tWITH
Sampling
n=2...12 (digital filter) ns
clock × 5T

Figure 1-3: Reset And Interrupt Timing

tWRSL

RESET

tWNIH tWNIL

NMI

tWITH tWITL

INTPn

Remark: n = 0 to 12

14 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
1.6.3 Clocked Serial Interface B (CSIB) Characteristics

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V
The load capacity of the output terminal is CL = 35pF.

Table 1-10: CSIB Characteristics (Master Mode)

CBnCKS2 to CBnCKS0 ≠ 111B

Parameter Symbol MIN. MAX. Unit

SCKBn cycle time tCYSKM 125 ns

SCKBn high level width tWSKHM 0.5 · tCYSKM - 10 ns

SCKBn low level width tWSKLM 0.5 · tCYSKM - 10 ns

SIBn setup time tSSISKM 20 ns

SIBn hold time tHSKSIM 10 ns

SOBn delay tDSKSOM 10 ns

SOBn hold time tHSKSOM 0.5 · tCYSKM - 10 ns

Table 1-11: CSIB Characteristics (Slave Mode)

CBnCKS2 to CBnCKS0 = 111B

Parameter Symbol MIN. MAX. Unit

SCKBn clock cycle time tCYSKS 125 ns

SCKBn high level width tWSKHS 0.5 · tCYSKS - 10 ns

SCKBn low level width tWSKLS 0.5 · tCYSKS - 10 ns

SIBn setup time tSSISKS 5 ns

SIBn hold time tHSKSIS 10 ns

SOBn delay tDSKSOS 25 ns

SOBn hold time tHSKSOS tWSKHS ns

Remark: n = 0, 1

DATA SHEET U19538EE2V0DS00 15

V850E/PHC3
Figure 1-12: CSIB Master/Slave Mode Timing

tCYSK
tWSKL tWSKH

SCKBn

tSSISK tHSKSI

SIBn Input data

tDSKSO tHSKSO

SOBn Output data

16 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
1.6.4 Clocked Serial Interface E (CSIE) Timing

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V
The load capacity of the output terminal is CL = 35pF.

Table 1-13: CSIE Characteristics (Master Mode)

Parameter Symbol MIN. MAX. Unit

Macro operation clock, cycle time tKCY 31.25 ns

SCKEn cycle time tKCYM 125 ns

SCKEn high, low width tKWHM, tKCYM/2 - 10 ns

tKWLM

SIEn input setup time (vs. SCKEn) tSSIM 20 ns

SIEn input hold time (vs. SCKEn) tHSIM 10 ns

SOEn output delay (vs. SCKEn) tDSOM 10 ns

SOEn output hold time (vs. SCKEn) tHSOM tKCYM/2 - 10 ns

CEnSIT=x ns
CEnOPE=0 tWSCSB0 tKCYM/2 - 10
CEnMD=x
SCSEnm inactive (High) width
CEnSIT=x ns
CEnOPE=1 tWSCSB1 (CSIDLE + 0.5) · tKCYM - 10
CEnMD=x

CEnSIT=x ns
CEnOPE=0
tSSCSB0 tKCY - 10
CEnIDL=x
CEnMD=0

CEnSIT=x ns
SCSEnm setup time (vs. CEnOPE=1
tSSCSB1 CSSETUP · tKCYM + tKCY - 10
SCKEn) CEnIDL=0
CEnMD=0

CEnSIT=x ns
CEnOPE=1
tSSCSB2 CSSETUP · tKCYM + tKCY - 10
CEnIDL=1
CEnMD=1

CEnSIT=0 ns
CEnOPE=0 tHSCSB0 tKCY - 10
CEnMD=x

CEnSIT=1 ns
CEnOPE=0 tHSCSB1 tKCYM/2 - 10
SCSEnm hold time CEnMD=x
(vs. SCKEn) CEnSIT=0 ns
CEnOPE=1 tHSCSB2 CSHOLD · tKCYM - 10
CEnMD=x

CEnSIT=1 ns
(CSHOLD + 0.5) · tKCYM - 10
CEnOPE=1 tHSCSB3
CEnMD=x

DATA SHEET U19538EE2V0DS00 17

V850E/PHC3
Table 1-13: CSIE Characteristics (Master Mode)

Parameter Symbol MIN. MAX. Unit

CEnSIT=x ns
CEnOPE=1 tINTER CSINTER · tKCYM
CEnMD=x
SCSEnm interframe time
CEnSIT=x ns
CEnOPE=0 - Not Applicable
CEnMD=x

Remark: n = 0, 1
m = 7 - 0 (n = 0), 3 - 0 (n = 1)
CSSETUP,CSINTER: are set by register CEnOPT0
CSIDLE,CSHOLD: are set by register CEnOPT1

Table 1-14: CSIE Characteristics (Slave Mode)

Parameter Symbol MIN. MAX. Unit

Macro operation clock, cycle time tKCY 31.25 ns

SCKEn cycle time tKCYS 125 ns

SCKEn high, low width tKWHS, tKCYS/2 - 10 ns

tKWLS

SIEn input setup time (vs. SCKEn) tSSIS 10 ns

SIEn input hold time (vs. SCKEn) tHSIS tKCY · 1.5 + 10 ns

SOEn output delay (vs. SCKEn) tDSOS 20 ns

SOEn output hold time (vs. SCKEn) tHSOS tKCYS/2 - 10 ns

Remark: n=0, 1

18 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
Figure 1-15: CSIEn Timings
(a) [SCKEn/SIEn/SOEn] Pins In Master Mode: (CEnCTL1: CEnCKP/CEnDAP=0/0 or 1/1)
t KCY

Clock

t KCYM
t KWLM t KWHM

SCKEn

t DSOM t HSOM

SOEn

t SSIM t HSIM

SIEn

Remark: n = 0, 1

(b) [SCKEn/SIEn/SOEn] Pins In Master Mode: (CEnCTL1: CEnCKP/CEnDAP=1/0 or 0/1)

t KCYM
t KWHM t KWLM

SCKEn

t DSOM t HSOM

SOEn

t SSIM t HSIM

SIEn

Remark: n = 0, 1

DATA SHEET U19538EE2V0DS00 19

V850E/PHC3
(c) [SCKEn/SIEn/SOEn] Pins In Slave Mode: (CEnCTL1: CEnCKP/CEnDAP=0/0 or 1/1)
t KCY

Clock

t KCYS
t KWLS t KWHS

SCKEn

t DSOS t HSOS

SOEn

t SSIS t HSIS

SIEn

Remark: n = 0, 1

(d) [SCKEn/SIEn/SOEn] Pins In Slave Mode: (CEnCTL1: CEnCKP/CEnDAP=1/0 or 0/1)

t KCYS
t KWHS t KWLS

SCKEn

t DSOS t HSOS

SOEn

t SSIS t HSIS

SIEn

Remark: n = 0, 1

20 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
Figure 1-16: CSEn7 - CSEn0 Pin Timings
(e) Only In Master Mode (CEnCTL0:CEnSIT/CEnWE=0/0 & CEnCTL4:CEnOPE=0)
Continuous transfer start
(SOEn output timing)

SCKEn

t HSCSB0
t SSCSB0

SCSEnm

INTCEnC

Remark: n = 0, 1
m = 7 - 0 (n = 0), 3 - 0 (n = 1)
INTCEnC: CSIEn transfer end interrupt

(f) Only In Master Mode (CEnCTL0:CEnSIT/CEnWE/CEnCSM=0/1/0 & CEnCTL4:CEnOPE=0)

(SOEn output timing)

SCKEn

t HSCSB0
t SSCSB1

SCSEnm

INTCEnC

Remark: n = 0, 1
m = 7 - 0 (n = 0), 3 - 0 (n = 1)
INTCEnC: CSIEn transfer end interrupt

DATA SHEET U19538EE2V0DS00 21

V850E/PHC3
(g) Only In Master Mode (CEnCTL0:CEnSIT/CEnWE/CEnCSM=0/1/1 & CEnCTL4:CEnOPE=0)
(SOEn output timing)

SCKEn

t HSCSB0
t WSCSB t SSCSB2

SCSEnm

INTCEnC

Remark: n = 0, 1
m = 7 - 0 (n = 0), 3 - 0 (n = 1)
INTCEnC: CSIEn transfer end interrupt

(h) Only In Master Mode (CEnCTL0:CEnSITCEnWE/CEnCSM=1/1/0 & CEnCTL4:CEnOPE=0)

(SOEn output timing)

SCKEn

t HSCSB1 t SSCSB0

SCSEnm

INTCEnC

Remark: n = 0, 1
m = 7 - 0 (n = 0), 3 - 0 (n = 1)
INTCEnC: CSIEn transfer end interrupt

22 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
(i) Only In Master Mode (CEnCTL0:CEnSIT/CEnWE/CEnCSM=1/1/0 & CEnCTL4:CEnOPE=0)
(SOEn output timing)

SCKEn

t HSCSB1 t SSCSB1

SCSEnm

INTCEnC

Remark: n = 0, 1
m = 7 - 0 (n = 0), 3 - 0 (n = 1)
INTCEnC: CSIEn transfer end interrupt

(j) Only In Master Mode (CEnCTL0:CEnSIT/CEnWE/CEnCSM=1/1/1 & CEnCTL4:CEnOPE=0) Or

(CEnCTL0:CEnSIT=1 & CEnCTL4:CEnOPE=1)
(SOEn output timing)

SCKEn

t HSCSB1 t WSCSB t SSCSB2

SCSEnm

INTCEnC

Remark: n = 0, 1
m = 7 - 0 (n = 0), 3 - 0 (n = 1)
INTCEnC: CSIEn transfer end interrupt

DATA SHEET U19538EE2V0DS00 23

V850E/PHC3
1.6.5 UARTC Timing

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V
The load capacity of the output terminal is CL = 35pF.

Table 1-17: UARTC Timing

Parameter Symbol Conditions MIN. MAX. Unit

Transfer rate TUARTC 4 Mbps

1.6.6 CAN Timing

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V
The load capacity of the output terminal is CL=35pF.

Table 1-18: CAN Timing

Parameter Symbol Conditions MIN. MAX. Unit

Internal transmit to receive data delay tnode tnode = toutput + tinput 75 ns

Figure 1-19: CAN Timing

Note 1
FCAN internal clock

t output

FCTXDn (n=0-1) pin

(Transfer data)

t input
FCRXDn (n=0-1) pin
(Receive data)

Notes: 1. The FCAN internal clock corresponds to the FCAN macro clock.

Figure 1-20: Internal Delay

This product FCTXDn pin (n=0-1)
Internal transfer delay
{{

CAN macro

Internal receive delay

FCRXDn pin (n=0-1)
Image figure of internal delay

24 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
1.6.7 AD Converter

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = AVREF0,1 = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVDD = 0V

Table 1-21: AD Converter Characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 10 bit

Overall errora TOE ±4 LSB

Quantization error ±0.5 LSB

Conversion timeb tCONV 2.0 8.0 µs

Sampling timec tSAMP 3 · tCONV / 16 s

Analog input voltage VIAN AVSS0,1 AVREF0,1 V

AVREFn input voltage AVREF0,1 AVREF0,1 = AVDD AVDD V
AVREFn input current AIREF0,1 60 300 µA
AVDD supply current AIDD 6 mA

a. The quantization error is not included.

b. The conversion time depends on register setting ADMn1. For ADMn1 register setting please refer to the users
manual.
c. The sampling time depends on the conversion time and thus from the ADMn1 register seeting. For ADMn1
register setting please refer to the users manual.

DATA SHEET U19538EE2V0DS00 25

V850E/PHC3
1.6.8 Flash Memory Programming Characteristics

(1) Basic Characteristics

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V
The load capacity of the output terminal is CL = 35pF.

Table 1-22: Flash Programming Characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operating Frequency fCPU 80 MHz

High Level Input Voltage VIH FLMD0 0.8·VDD30 VDD30

Low Level Input Voltage VIL FLMD0 -0.5 0.2·VDD30

Rewrite count CERWRa 100 times

Code Flash
Data retention 15 years

Rewrite count CERWRa 10000 times

Data Flash
Data retention 3 years
a. The initial write when the product is shipped, any erase → write set of operations, or any programming oper-
ation is counted as one rewrite.
Example: (P: Program(write) E: Erase)
Product is shipped → P → E → P → E → P : Rewrite count: 3
Product is shipped → E → P → E → P → E → P : Rewrite count: 3

(2) Serial Writing Operating Conditions

Ta = -40 to +125°C
VDD15 = CVDD = 1.5V ± 10%
VDD30 = AVDD = 3.3V ± 0.3V
VSS15 = CVSS = VSS30 = AVSS = 0V
The load capacity of the output terminal is CL = 35pF.

Table 1-23: Serial Writing Characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit
FLMD0 setup time (from VDD15) tDP 1 ms

RESET release (from FLMD0) tPR a 2 ms

Count start time from RESET to FLMD0 fRP 1.2 ms

Count finish time from RESET to FLMD0 fRPE 10 ms
FLMD0 high / low level width tPW 10 100 µs
FLMD0 rise / fall time tR / tF 1 µs

a. Turning on timing has to be considered for all power supply voltages, refer to 1.6.1 Power Supply Turning On
/ Interception Timing

26 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
Figure 1-24: Serial Write Operation Timing

V DD15
V DD15
0V

V DD30 V IH V IH
FLMD0
0V V IL

V DD30 t PW t PW tR tF
FLMD1
0V

V DD30 V IH
RESET
0V

t DP t PR t RP

t RPE

DATA SHEET U19538EE2V0DS00 27

V850E/PHC3
2. Recommended Soldering Conditions

Solder this product under the following recommended conditions.

For details of the recommended soldering conditions, refer to the Joint Industry Standard:

JEDEC J-STD-020C (MSL=3)

For soldering methods and conditions other than those recommended please consult NEC.

28 DATA SHEET U19538EE2V0DS00

 V850E/PHC3
3. Package

3.1 Package Dimension of µPD70F3485GJ(A2)-GAE

144-PIN PLASTIC LQFP (FINE PITCH) (20x20)

HD detail of lead end

D
L1
108 73
109 72 A3
c

L
E HE Lp

(UNIT:mm)
ITEM DIMENSIONS
D 20.00±0.20
144 37 E 20.00±0.20
1 36 HD 22.00±0.20
HE 22.00±0.20

ZE A 1.60 MAX.
b x M S e A1 0.10±0.05
A2 1.40±0.05
ZD A3 0.25
+
A b 0.20 0.07
0.03
A2 c 0.125 +0.075
0.025
L 0.50
S
Lp 0.60±0.15
L1 1.00±0.20
y S A1 3° + 4°
3°
e 0.50
x 0.08
y 0.08
ZD 1.25
ZE 1.25
P144GJ-50-GAE-2

NEC Electronics Corporation 2008

DATA SHEET U19538EE2V0DS00 29

V850E/PHC3
4. Revision History

Table 4-1: Revision History

Version Date Remarks
1.0 2008/11/21 Initial version
2.0 2010/01/14 Flash memory size of 512 KB splitted into internal flash memory of
480 KB and data flash of 32 KB.
µPD70F3485W-CAR (bare die) derivate removed.
VDD15x, VSS15x replaced by VDD15, VSS15.
CVDD15, CVSS15 replaced by CVDD, CVSS.
VDD3x, VSS3x replaced by VDD30, VSS30.
IDD3 replaced by IDD30.
Input level VIH/VIL of MODE1 (FLMD0) pin corrected (to same
input level as MODE0 pin).
Frequency name fXX replaced by fCPU in Table 1-7 conditions.
Parameter “Reprogramming” replaced by “Rewrite count CERWR”
in Table 1-22.
Reference voltage supply for FLMD0 setup time changed from
(unspecific) VDD to VDD15 in Table 1-23 and Figure 1-24.

30 DATA SHEET U19538EE2V0DS00

 V850E/PHC3

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DATA SHEET U19538EE2V0DS00 31