Universal Process Migration Solution of MAGICAL for Analog IC Layout

Automation
Yufeng Wei1,†, Yifan Xu1,†, Keren Zhu2, Ye Lu1,*
1
State Key Lab. of Integrated Chips and Systems and School of Information Science and Technology,
Fudan University, Shanghai, China;
2
Department of Computer Science and Engineering at The Chinese University of Hong Kong, Hong
Kong, China
Email: [email protected]； † These authors contributed equally.

Biography IC layout generation tool developed by the university of Texas

2024 Conference of Science and Technology for Integrated Circuits (CSTIC) | 979-8-3503-6219-0/24/$31.00 ©2024 IEEE | DOI: 10.1109/CSTIC61820.2024.10531849

Yufeng Wei received B.S. degree in Electrical at Austin group is considered as one of the best achievements
Engineering and Automation from Shanghai University, in the field[1-4]. However, currently MAGICAL is only able
Shanghai, China, in 2021. He is currently working toward the to work at TSMC 40nm, which significantly restricted its
M.S. degree in Electronic Information Science with the School application scenarios. Importing other technology filesinto
of information science and technology, Fudan University, MAGICAL is non-trivial[1]. Mutiple improvements need to be
Shanghai, China. His research interest focuses on automated accomplishsed to reach this goal：(1) The device generation
methods for analog circuit layout generation. Yifan Xu is needs to be correctly changed according to the technology. (2)
currently a Master’s degree candidate at School of Information All changes should obey the design rules in different
Science and Technology, Fudan University, Shanghai, China, technologies. (3) After the migration and corresponding
focusing on the automation of analog and mixed-signal circuit modifications, the speed and accuracy of layout generation
design. He earned his Bachelor’s degree in Electronic must not be compromised.
Engineering from the same institution. In this work, we have developed a complete set of process
migration solutions that can provide a convenient technology
Abstract migration environment for MAGICAL. The proposed new
Analog IC layout automation has been a hot topic in the flow meets the process technology conversion requirements of
field in recent years[1]. An open-source software MAGICAL different process libraries with minimum modifications.
developed by the University of Texas team is one of the most
effective means to achieve this goal[2]. However, so far Technology Migration Solution
MAGICAL is only able to support one process library The Device Generator is the most important compoenent
currently, i.e., TSMC 40nm, and this imposes limitations of its for technology migration of layout generation. To generate
practical application. This work proposes a solution for the devices' layout in accordance with design rules, designer
technology migration of MAGICAL, and this greatly broadens should plan the geometric structure reasonably, as well as the
its application scenarios. Firstly, the MAGICAL's device connection relationships of each layer. Therefore, the device
generator is rewritten to take in the general design rule generator of MAGICAL version 1.0 was manually modified
information of different technology nodes. Second, the first to better receive the key parameters without any conflicts
parameters of a given technology’s tech file are extracted by in design rules. This step only needs to be completed once to
customerized Parameter Extractor. Finally, the extracted correspond to flat devices of different technology libraries with
parameters are set into the device generator of MAGICAL as similar structures.
well as the LEF file used for routing. As demonstrations,
layouts of multiple circuits such as inverter, Foleded Cascode,
Nbooster and Pbooster are generated sucessfully using this new
flow at different technology nodesincluding but not limited to
TSMC 65nm and TSMC 130nm. In addition, all GDS files
generated with this method are DRC-clean and LVS-clean.
This work paves the way for MAGICAL to be used in design
automation at various technology nodes.

Keywords: Analog IC Layout Automation, technology

migration, MAGICAL, Parameter Extractor, design rule,
device generator
Figure 1: Flow of the technologies migration solutions of
MAGICAL.
Introduction
Layout automation for Analog IC has been an active Figure 1 shows the proposed flow. Due to the abundance
research area for many years and a complete solution for this of design rules, manually inputting them can be tedious. We
challenge is still desired. MAGICAL, a fully automated analog

Authorized licensed use limited to: VIT University. Downloaded on July 15,2024 at 17:18:45 UTC from IEEE Xplore. Restrictions apply.
propose a customerized Parameter Extractor to effectively Figure 2 depicts the layouts of the inverter and the Folded
locate and parse the key parameters in deisgn rule files, and cascode generated. It is formed with instances from TSMC
send them to the corresponding modules. The Parameter 130nm library. Figure 3 shows the schematic of the Nbooster
Extractor also takes on the task of parsing converting the netlist and Pbooster. Figure 4 are the layouts of the Nbooster and
of the circuits. Pbooster using TSMC 130nm process as well. They both
The first module, the Device Generator, contains two maintain the symmetry of analog circuit layout, as shown on
important sections which need to be rewritten. They are the schematic, and the layout generated by MAGICAL has the
MOSFET and Guard Ring (GR). We parameterize and same topology with the schematic. All of the instances and the
templateize the Device Generator to receive the parsed design routing layers obey the design rules of TSMC 130nm.
rules from the Parameter Extractor. On this basis, a detection We also migrate TSMC 65nm technology into
mechanism is set up to ensure that the generated device layout MAGICAL by using the same method. All the GDS files
does not violate the design rule. generated by MAGICAL at the new technology node
After modifying the device generator, the Parameter successfully pass DRC and LVS.
Extractor first reads the input design rule files, especially the
technical file and DRC rule file. Then, the Parameter Extractor
inputs these parameters into the device generator and LEF file
for routing, and update the corresponding modules. Then, the
Parameter Extractor will parse and convert the input netlist into
a format that conforms to the device generator's input. The
device generator sub module is transmitted to the subsequent
PLACER module. After the layout is completed, the ROUTER
module will route the wires according to the updated LEF file
for routing, ensuring that the metal wires and VIA generated
by the wiring meet the requirements of the design rule file. The Figure 3: Schematic of CFMB. (a) Nbooster. (b) Pbooster.
final GDS file obtained must be able to pass through DRC and
LVS, and meet the design rules requirements. In this flow,
designers can easily migrate process relying on the Parameter
Extractor and the modified Device Generator, which allows
MAGICAL to be applied at varying technology nodes, rather
than only TSMC 40nm.
This proposed and implemented method is universal and
requires minimum adjustment to acomplish automatic layout
generation at different nodes. It effectively enhances the
migratability and applicability of MAGICAL, and this set of
solutions may also suit other EDA tools which require
technology migration.

Applications on Analog Circuits

As demonstrations, layouts of several circuits including
an inverter, a Folded Cascode, a Pbooster and a Nbooster are
automatically generated using the aforementioned method.

Figure 4: Layout generated by MAGICAL in TSMC 130nm

process. (a) Nbooster. (b) Pbooster.

In order to verify the feasibility of this solution for placing

and routing of large-scale analog integrated circuits, we test the
MAGICAL with migration on a gain amplifier consisting of 50
MOSFETs, with Pbooster and Nbooster as sub circuits in the
netlist structure. Figure 5 shows the layout of the gain amplifier
using TSMC 130nm process and TSMC 65nm process. The
results indicate that migrating the TSMC 130nm and TSMC
65nm technologies into MAGICAL can successfully generate
corresponding layouts from netlists of large-scale analog
integrated circuits.

Figure 2: Layout generated by MAGICAL in TSMC 130nm

process. (a) inverter. (b) Folded cascode.

Authorized licensed use limited to: VIT University. Downloaded on July 15,2024 at 17:18:45 UTC from IEEE Xplore. Restrictions apply.
 TABLE I. CONPARISON OF MANUAL WORK, MAGICAL AND
MAGICAL WITH MIGRATION.
Methods for Generating Layouts
Under Different Processes
MAGICAL
Manual MAGICAL
with migration
time 10h~120h 5s~120s 5s~120s
workload Heavy Heavy Light
reusability Unable Difficult Easy
DRC & LVS Clean Clean Clean

b) Employing MAGICAL for design purposes drastically

reduces the time requirement to a range between 5 seconds and
2 minutes. However, should there be a necessity to incorporate
different technology libraries within the design process, the
workload remains significant. Despite the marked acceleration
in speed, there is no substantial enhancement in flexibility, as
the design's transferability continues to be constrained.
c) The optimized version of MAGICAL with migration
not only reduces the design duration significantly but also
alleviates the workload while facilitating ease of migration.
Consequently, MAGICAL provides not only rapid design
capabilities but also the versatility to modify and adapt to
varying technology nodes, thus considerably augmenting
flexibility.

Conclusions
This article proposes a technology migration solution
based on MAGICAL which is EDA for Analog IC Layout
automation. This scheme is mainly based on the templating
adjustment of device generator and parameter extraction and
input of Parameter Extractor. Through this solution, developers
can easily complete the technology migration for MAGICAL,
and the resulting layout can meet the design rules of the new
process library, expanding the applicability of MAGICAL.
This scheme can also be extended to other EDA tools that
parameterize devices.

References
[1] K. Zhu, H. Chen, M. Liu and D. Z. Pan, "Tutorial and
Perspectives on MAGICAL: A Silicon-Proven Open-
Source Analog IC Layout System," in IEEE Transactions
on Circuits and Systems II: Express Briefs, vol. 70, no. 2,
pp. 715-720, Feb. 2023.
[2] B. Xu et al., "MAGICAL: Toward Fully Automated
Figure 5: Layout generated of Gain amplifier by MAGICAL Analog IC Layout Leveraging Human and Machine
using different TSMC process. (a) TSMC 130nm process. (b) Intelligence: Invited Paper," 2019 IEEE/ACM
TSMC 65nm process. International Conference on Computer-Aided Design
(ICCAD), Westminster, CO, USA, 2019, pp. 1-8.
[3] H. Chen et al., "MAGICAL 1.0: An Open-Source Fully-
Comparisons
Automated AMS Layout Synthesis Framework Verified
Table Ⅰ. shows the comparisons between layouts
With a 40-nm 1GS/s Δ∑ ADC," 2021 IEEE Custom
generated by manual work, MAGICAL and MAGICAL with
Integrated Circuits Conference (CICC), Austin, TX, USA,
migration. It is shown that all three methodologies are capable
2021.
of generating layouts which comply with DRC and LVS.
[4] H. Chen et al., "MAGICAL: An Open- Source Fully
a) An experienced engineer specialized in the design of
Automated Analog IC Layout System from Netlist to
analog integrated circuit layouts, would necessitate a time
GDSII," in IEEE Design & Test, vol. 38, no. 2, pp. 19-26,
frame spanning from 10 to 120 hours. This process is
April 2021.
characterized by a substantial workload with the resultant
design exhibiting a deficiency in reusability and an incapacity
for migration.

Authorized licensed use limited to: VIT University. Downloaded on July 15,2024 at 17:18:45 UTC from IEEE Xplore. Restrictions apply.