CD54HC147, CD74HC147, CD74HCT147

SCHS149G – NOVEMBER 1998 – REVISED JANUARY 2025

CDx4HC147, CD74HCT147 High-Speed CMOS Logic 10- to 4-Line Priority Encoder

1 Features 2 Description
• Buffered inputs and outputs The CDx4HC147 and CD74HCT147 are 9-input
• Typical propagation delay: 13ns at VCC = 5V, CL = priority encoders. These devices provide the 10-line to
15pF, TA = 25oC 4-line priority encoding function by use of the implied
• Fanout (over temperature range) decimal “zero.”
– Bus driver outputs: 15 LSTTL loads Device Information
• Wide operating temperature range: -55oC to 125oC PART NUMBER PACKAGE(1) BODY SIZE (NOM)(2)
• Balanced propagation delay and transition times CD54HC147 J (CDIP, 16) 21.34mm × 6.92mm
• Significant power reduction compared to LSTTL N (PDIP, 16) 19.31mm × 6.35mm
logic ICs CD74HC147 D (SOIC, 16) 9.90mm × 3.90mm
• HC types PW (TSSOP, 16) 5.00mm × 4.40mm

– 2V to 6V Operation CD74HCT147 N (PDIP, 16) 19.31mm × 6.35mm

– High noise immunity: NIL = 30%, NIH = 30% of

(1) For more information, see Mechanical, Packaging, and
VCC at VCC = 5V Orderable Information.
• HCT types (2) The body size (length × width) is a nominal value and does
– 4.5V to 5.5V Operation not include pins.
– Direct LSTTL input logic compatibility, VIL= 0.8V
(Max), VIH = 2V (Min)
– CMOS input compatibility, Il ≤ 1µA at VOL, VOH

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC147, CD74HC147, CD74HCT147
SCHS149G – NOVEMBER 1998 – REVISED JANUARY 2025 www.ti.com

Table of Contents
1 Features............................................................................1 7 Application and Implementation.................................... 9
2 Description.......................................................................1 7.1 Power Supply Recommendations...............................9
3 Pin Configuration and Functions...................................3 7.2 Layout......................................................................... 9
4 Specifications.................................................................. 4 8 Device and Documentation Support............................11
4.1 Absolute Maximum Ratings........................................ 4 8.1 Documentation Support............................................ 11
4.2 Recommended Operating Conditions.........................4 8.2 Receiving Notification of Documentation Updates.... 11
4.3 Thermal Information....................................................4 8.3 Support Resources................................................... 11
4.4 Electrical Characteristics.............................................5 8.4 Trademarks............................................................... 11
4.5 Switching Characteristics............................................6 8.5 Electrostatic Discharge Caution................................ 11
5 Parameter Measurement Information............................ 7 8.6 Glossary.................................................................... 11
6 Detailed Description........................................................8 9 Revision History............................................................ 11
6.1 Overview..................................................................... 8 10 Mechanical, Packaging, and Orderable
6.2 Functional Block Diagram........................................... 8 Information.................................................................... 12
6.3 Device Functional Modes............................................8

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3 Pin Configuration and Functions

CD54HC147 J Package; CD74HC(T)147 N, D, or PW Package;

16-Pin CDIP, PDIP, SOIC, or TSSOP
(Top View)

Table 3-1. Pin Functions

PIN
I/O1 DESCRIPTION
NO. NAME
1 I4 I Active low input 4
2 I5 I Active low input 5
3 I6 I Active low input 6
4 I7 I Active low input 7
5 I8 I Active low input 8
6 Y2 O Active low output 2
7 Y1 O Active low output 1
8 GND — Ground
9 I0 I Active low input 0
10 I9 I Active low input 9
11 I1 I Active low input 1
12 I2 I Active low input 2
13 I3 I Active low input 3
14 Y3 O Active low output 3
15 NC N/A No internal connection
16 VCC — Positive supply

1. I = input, O = output, P = power, FB = feedback, GND = ground, N/A = not applicable

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4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage -0.5 7 V
IIK Input diode current For VI < -0.5V or VI > VCC + 0.5V ±20 mA
IOK Output diode current For VO < -0.5V or VO > VCC + 0.5V ±20 mA
Output source or sink current per output
IO For VO > -0.5V or VO < VCC + 0.5V ±25 mA
pin
Continuous current through VCC or GND ±50 mA

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
HC Types 2 6
VCC Supply voltage range V
HCT Types 4.5 5.5
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2V 1000
tt Input rise and fall time VCC = 4.5V 500 ns
VCC = 6V 400
TA Temperature range -55 125 °C

4.3 Thermal Information

N (PDIP) NS (SOP) D (SOIC) PW (TSSOP)
THERMAL METRIC 16 PINS 16 PINS 16 PINS 16 PINS UNIT
RθJA Junction-to-ambient thermal
67 64 117.2 137.5 °C/W
resistance(1)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report

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4.4 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS 25°C -40°C to 85°C -55°C to 125°C
PARAMETER VCC (V) UNIT
VI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 1.5 1.5 1.5 V
High-level input
VIH 4.5 3.15 3.15 3.15 V
voltage
6 4.2 4.2 4.2 V
2 0.5 0.5 0.5 V
VIL Low-level input voltage 4.5 1.35 1.35 1.35 V
6 1.8 1.8 1.8 V

High-level output -0.02 2 1.9 1.9 1.9 V

voltage -0.02 4.5 4.4 4.4 4.4 V
CMOS loads
VOH VIH or VIL -0.02 6 5.9 5.9 5.9 V
High-level output –4 4.5 3.98 3.84 3.7 V
voltage
–5.2 6 5.48 5.34 5.2 V
TTL loads

Low-level output 0.02 2 0.1 0.1 0.1 V

voltage 0.02 4.5 0.1 0.1 0.1 V
CMOS loads
VOL VIH or VIL 0.02 6 0.1 0.1 0.1 V
Low-level output 4 4.5 0.26 0.33 0.4 V
voltage
5.2 6 0.26 0.33 0.4 V
TTL loads
II Input leakage current VCC or GND 6 ±0.1 ±1 ±1 µA
Quiescent device 6 80 160
ICC VCC or GND 0 8 µA
current
HCT TYPES
High-level input 4.5 to
VIH 2 2 2 V
voltage 5.5
4.5 to
VIL Low-level input voltage 0.8 0.8 0.8 V
5.5
High-level output
voltage -0.02 4.5 4.4 4.4 4.4 V
CMOS loads
VOH VIH or VIL
High-level output
voltage -4 4.5 3.98 3.84 3.7 V
TTL loads
Low-level output
voltage 0.02 4.5 0.1 0.1 0.1 V
CMOS loads
VOL VIH or VIL
Low-level output
voltage 4 4.5 0.26 0.33 0.4 V
TTL
VCC and 5.5 ±1 ±1
II Input leakage current 0 ±0.1 µA
GND
Quiescent device 5.5 80 160
ICC VCC or GND 0 8 µA
current
Additional quiescent
4.5 to
∆ICC(1) device current per VCC -2.1 100 360 450 490 µA
5.5
input pin: 1 Unit Load

(1) VI = VIH or VIL, unless otherwise noted.

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HCT Input Loading Table

4.4 Electrical Characteristics
INPUT UNIT LOADS(1)
I 1 ,I 2 ,I 3 ,I 6 ,I 7 1.1
I 4,I 5,I 8,I 9 1.5

(1) Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,

360µA max at 25oC.

4.5 Switching Characteristics

Input tt = 6ns. Unless otherwise specified, CL = 50pF
TEST 25°C -40°C to 85°C -55°C to 125°C
PARAMETER CONDITIONS VCC (V) UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 160 200 240

tPLH, Propagation delay, 4.5 32 40 48

CL = 50pF ns
tPHL input to output 5 13
6 27 34 41
2 75 95 110
tTLH, tTHL Transition times CL = 50pF 4.5 15 19 22 ns
6 13 16 19
CIN Input capacitance 10 10 10 pF
Power dissipation
CPD 5 32 pF
capacitance(1) (2)
HCT TYPES

tPLH, Propagation delay, 4.5 35 44 53 ns

CL = 50pF
tPHL input to output 5 14 ns
tTLH, tTHL Transition times CL = 50pF 4.5 15 19 22 ns
CIN Input capacitance 10 10 10 pF
Power dissipation
CPD 5 42 pF
capacitance(1) (2)

(1) CPD is used to determine the dynamic power consumption, per gate.
(2) PD = VCC 2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

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5 Parameter Measurement Information

tpd is the maximum between tPLH and tPHL
tt is the maximum between tTLH and tTHL

Figure 5-2. HCT transition times and propagation

Figure 5-1. HC and HCU transition times and
delay times, combination logic
propagation delay times, combination logic

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6 Detailed Description
6.1 Overview
The CDx4HC147 and CD74HCT147 devices are high speed silicon-gate CMOS devices and are pin-compatible
with low power Schottky TTL (LSTTL).
The CDx4HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l1 to l9)
and provide binary representation on the four active LOW outputs (Y0 to Y3). A priority is assigned to each input
so that when two or more inputs are simultaneously active, the input with the highest priority is represented on
the output, with input line l9 having the highest priority.
These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”. The
“zero” is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.
6.2 Functional Block Diagram

Figure 6-1. Functional Block Diagram

6.3 Device Functional Modes

Function Table lists the functional modes of the CDx4HC(T)147.
(1) (2) (3)
Table 6-1. Truth Table
INPUTS OUTPUTS
I1 I2 I3 I4 I5 I6 I7 I8 I9 Y3 Y2 Y1 Y0
H H H H H H H H H H H H H
X X X X X X X X L L H H L
X X X X X X X L H L H H H
X X X X X X L H H H L L L
X X X X X L H H H H L L H
X X X X L H H H H H L H L
X X X L H H H H H H L H H
X X L H H H H H H H H L L
X L H H H H H H H H H L H
L H H H H H H H H H H H L

(1) H = High logic level

(2) L = Low logic level
(3) X = Don't care

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass
capacitors to reject different frequencies of noise. The 0.1μF and 1μF capacitors are commonly used in parallel.
The bypass capacitor should be installed as close to the power terminal as possible for best results.
7.2 Layout
7.2.1 Layout Guidelines
• Bypass capacitor placement
– Place near the positive supply terminal of the device
– Provide an electrically short ground return path
– Use wide traces to minimize impedance
– Keep the device, capacitors, and traces on the same side of the board whenever possible
• Signal trace geometry
– 8mil to 12mil trace width
– Lengths less than 12cm to minimize transmission line effects
– Avoid 90° corners for signal traces
– Use an unbroken ground plane below signal traces
– Flood fill areas around signal traces with ground
– For traces longer than 12cm
• Use impedance controlled traces
• Source-terminate using a series damping resistor near the output
• Avoid branches; buffer signals that must branch separately
7.2.2 Layout Example
WORST BETTER BEST
2W

W
≥

≥ 5W

W
W

Figure 7-1. Example Trace Corners for Improved Signal Integrity

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GND VCC VCC GND

0.1
F
0.1
F
VCC
1 14 VCC
1 20
2 13 2 19
3 12 3 18
4 11 4 17
5 10
5 16
6 9
6 GND 15
GND 7 8
7 14
Figure 7-2. Example Bypass Capacitor Placement 8 13
for TSSOP and Similar Packages
9 12
10 11
GND

Figure 7-3. Example Bypass Capacitor Placement

for WQFN and Similar Packages

GND VCC
0.1
F
1 6 VCC
2 5
GND 3 4

Figure 7-4. Example Bypass Capacitor Placement for SOT, SC70 and Similar Packages

Transmitting Port Receiving Port

22
Long controlled-impedance trace

Figure 7-5. Example Damping Resistor Placement for Improved Signal Integrity

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
• Texas Instruments, Designing With Logic application report
• Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application report
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2003) to Revision G (January 2025) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards.............................................................................................................................1
• Added Device Information table, Pin Functions table, Thermal Information table, Device Functional Modes,
Application and Implementation section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ................................................................................................. 1
• Updated thermal values to reflect current function. D was 73 is now 117.2; PW was 108 is now 137.5........... 4

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

8406401EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8406401EA Samples
& Green CD54HC147F3A
CD54HC147F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8406401EA Samples
& Green CD54HC147F3A
CD74HC147E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC147E Samples

CD74HC147M OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 HC147M

CD74HC147M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC147M Samples

CD74HC147MT OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 HC147M

CD74HC147PW OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 HJ147
CD74HC147PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ147 Samples

CD74HC147PWT OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 HJ147

CD74HCT147E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT147E Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Dec-2024

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC147, CD74HC147 :

• Catalog : CD74HC147
• Military : CD54HC147

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC147M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC147PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC147M96 SOIC D 16 2500 356.0 356.0 35.0
CD74HC147PWR TSSOP PW 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

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TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC147E N PDIP 16 25 506 13.97 11230 4.32
CD74HC147E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT147E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT147E N PDIP 16 25 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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