Nuclear Inst.

and Methods in Physics Research, A 919 (2019) 119–124

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Nuclear Inst. and Methods in Physics Research, A

journal homepage: www.elsevier.com/locate/nima

A HV silicon vertical JFET: TCAD simulations

Gabriele Giacomini ∗, Wei Chen, David Lynn
Brookhaven National Laboratory, Upton 11973, NY, USA

ARTICLE INFO ABSTRACT

Keywords: In the future ATLAS Inner Tracker detector (ITk), several silicon strip modules will be biased by a single High-
TCAD simulations Voltage (HV) line, so that a switch between each strip sensor and the HV line is required to disconnect faulty
JFET sensors. Such a switch must satisfy strict requirements, such as being radiation hard, being able to sustain
Power devices
high voltages in the OFF state and being able to operate in a high magnetic field. At Brookhaven National
High voltage
Laboratory we conceived a new kind of solid-state switch that can potentially meet all the specs: it is a HV silicon
vertical JFET. Before designing and fabricating the JFET, we did a study using numerical TCAD simulations that
demonstrate the feasibility of fabricating the device in a standard planar technology. We report such simulations,
highlighting in particular a few key parameters to which the JFET performances are most sensitive.

1. Introduction
promises to be simpler and cheaper to fabricate than the 3D Trench
JFET. The emphasis in this paper is on the TCAD simulations which
The ATLAS detector at the Large Hadron Collider (LHC) will undergo
guided the JFET design. In Section 2, the geometry of the device is pre-
multiple upgrades to improve detector performance to prepare for the
sented and compared with the standard JFET by using an oversimplified
LHC’s transition to the High Luminosity LHC (HL-LHC). One of the main
structure for both JFETs. In Section 3, the effect of various parameters
upgrades is the replacement of the current tracker with an all-silicon
is described, and finally in Section 4 the feasibility in the planar process
inner tracker (ITk) [1]. The outer part of the ITk consists of silicon
is described.
strip detectors mounted on carbon composite structures that provide
mechanical support, cooling, and electrical services to groups of sensors.
Due to lack of space, groups of sensors will need to share the same High 2. Standard JFET vs vertical JFET
Voltage (HV) bias line. Consequently, the failure of a single sensor due
to its developing a short or going into breakdown will result in the loss The standard silicon JFET is an elementary solid-state device, whose
of operation of the other sensors sharing the same HV bias. It is desirable theoretical treatment can be found in any textbook on silicon devices
to have a remote-controlled switch on each sensor’s HV line that could (for example [5], chapter 6). For the sake of comparison with the HV ver-
be opened to isolate a failed sensor from the common HV bus and allow tical JFET that we are going to discuss, we simulated an oversimplified
continued operation of the working sensors on that bus. structure. Fig. 1 shows the two-dimensional geometry of the standard
An R&D program called HV Mux was initiated by Brookhaven JFET. The top and bottom gates, which in this particular simulation are
National Laboratory (BNL) to find a high voltage switch that could shorted together (JFET in triode configuration), are uniformly doped
operate above the 500 V sensor bias, operate in a 2T magnetic field, and with an acceptor concentration of 1018 cm−3 (in the following, we
survive radiation doses of 50 Mrad and fluences of 1.2 ⋅ 1015 𝑛𝑒𝑞 ∕cm2 [2]. consider n-type JFETs only). The channel is n-doped with a donor
The switch is the key component of an HV Mux circuit made of concentration of 1016 cm−3 ; it makes then step junctions with the two
additional discrete components driven by a custom ASIC, all of which gates. The channel length is 5 μm, which is the length of the overlapping
are mounted on a kapton circuit board epoxied to each silicon sensor. of the two gates, while the channel thickness is 1 μm. The source and
Commercial transistors fabricated in wide bandgap materials such as the drain sit close to the channel ends. The output characteristics of such
silicon carbide and gallium nitride have been investigated. Additionally, a device, i.e. the drain currents as a function of the drain voltage, for
BNL has collaborated on a custom silicon vertical JFET using 3D trench different values of the gate voltage, are shown in Fig. 1.
technology [3]. Prototypes have been fabricated by CNM (Barcelona, Fig. 2 shows the two-dimensional geometry of the proposed HV
Spain) [4]. vertical JFET. At the surface of the device, as in the case of the regular
Here we report on the design of a custom vertical JFET for HV Mux JFET, there are the source and the top gate. Again, as in the case of
that is fabricated using only planar silicon technology and therefore the regular JFET, the channel runs over all the length of the surface.

∗ Corresponding author.
E-mail address: [email protected] (G. Giacomini).

https://doi.org/10.1016/j.nima.2018.12.046
Received 1 October 2018; Received in revised form 27 November 2018; Accepted 13 December 2018
Available online 21 December 2018
0168-9002/© 2018 Elsevier B.V. All rights reserved.
G. Giacomini, W. Chen and D. Lynn Nuclear Inst. and Methods in Physics Research, A 919 (2019) 119–124

Fig. 1. Geometry of the simulated standard JFET (the red arrow shows the path of the electrons of the source-to-drain current), and its output characteristics (referring to a 1-μm wide
structure).

Fig. 2. Left, geometry of the simulated 2D HV-JFET (the red arrow shows the path of the electrons of the source-to-drain current). From 𝑌 = 2 μm downward, the current flows in a
medium- or high-resistivity epitaxial layer. Right, output characteristics (referring to a 1-μm wide structure). Also shown for comparison, the standard JFET current for 𝑉𝑔𝑎𝑡𝑒 = 0, as in
Fig. 1, which shows a breakdown at 40 V.

The drain contact, instead, sits on the opposite side of the wafer. The will be typically less than 1 μA with a full depletion voltage specified to
distance between the surface and the drain is set by the wafer thickness, be less than 300 V. The curves show that this device, which is however
or by the thickness of the epitaxial layer. The bottom gate features an just an oversimplification, is perfectly able to handle the pre-irradiation
interruption in its implant to allow the source-to-drain current to flow requirements on the voltage and on the current. We comment about the
through it, between these two terminals. The top gate overlaps with post-irradiation requirements at the end of this section.
the bottom gate by the channel length, in this case 5 μm to ease the The turn-off voltage, defined as the gate voltage which fully depletes
comparison with the standard JFET of Fig. 1. The top gate covers also the channel close to the source end, is given analytically by the equation
the gap in the bottom gate. ([6], page 250):
To increase the channel width (and thus the source-to-drain current 𝑞
𝑉𝑡𝑢𝑟𝑛−𝑜𝑓 𝑓 = −𝑉𝑏𝑖 + 𝑁 𝑋2
and the transconductance), standard JFETs usually adopt an inter- 8𝜀𝑆𝑖 𝐶 𝐶
digitated geometry, where wide parallel source and drain electrodes where 𝑉𝑏𝑖 is the built-in voltage of the gate/channel junction. 𝑉𝑡𝑢𝑟𝑛−𝑜𝑓 𝑓
alternate themselves in a linear array (with the top gate separating in the HV JFET is the same as in the regular JFET (about 2 V), since the
them). In the vertical JFET, top gate electrodes alternate only with dimensions and the doping of the channel and the gates are the same for
source electrodes, the drain being the uniform electrode on the back. both simulated devices. The parameter, as extracted from these curves,
In the structure of Fig. 2, which will be in the following our reference that is very different between the two types of devices is the drain
geometry for the HV-JFET, to ease the comparison with the JFET of voltage required for the onset of saturation, 𝑉𝐷,𝑠𝑎𝑡 . In fact, due to the
Fig. 1, the channel parameters are the same, i.e. the donor doping small dimension of the gap, the bottom gate is very effective in shielding
concentration 𝑁𝐶 is 1016 cm−3 , the thickness 𝑋𝐶 is 1 μm and the length the drain voltage: a much larger drain voltage must be applied so that
5 μm. The acceptor doping concentration of both gates (again short- the channel gets the sufficient bias at its end to deplete the channel
circuited during the simulations) is 1018 cm−3 . The device of Fig. 2 itself. However, this structure can sustain very large drain voltages,
is symmetric with respect to a vertical axis passing through mid top because the full 𝑉𝑔𝑎𝑡𝑒 − 𝑉𝑑𝑟𝑎𝑖𝑛 voltage difference falls in the high or
gate and, since in TCAD simulations Neumann’s boundary conditions medium resistivity substrate, as happens in the case of a 1-dimensional
apply, only half of the geometry needs to be simulated. Fig. 2 shows the PIN diode. For comparison, the regular JFET breaks down at about 40 V,
simulated output characteristics of this half device. As can be seen, the due to the proximity of the gate and drain terminals. The breakdown
magnitude of drain currents in saturation is comparable to the standard voltage of the bottom gate/drain junction is strongly dependent on the
JFET, given the same 𝑉𝑔𝑎𝑡𝑒 . Before irradiation the total sensor current doping concentration and thickness of the epitaxial layer, as happens

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Fig. 3. (a) Equipotential lines for an applied bias of 𝑉𝑑𝑟𝑎𝑖𝑛 = 100 V, source at zero, gate at −0.5 V, red color is +6 V, blue is 0 V. (b), electron current density. The plots are zooms of the
first 5 μm from the Si/SiO2 interface.

Fig. 4. (a) Equipotential lines in the bulk of the vertical JFET for an applied bias of 𝑉𝑑𝑟𝑎𝑖𝑛 = 100 V, source at zero, gate at −0.5 V. (b), electron current density.

in a regular PIN diode [7]. Also, a guard ring termination structure • as a thin semiconductor device, it can be operated in magnetic
must be carefully designed, externally to the bottom gate, to prevent fields;
the development of high electric fields at the Si/SiO2 interface. This • it is normally ON;
termination must sustain at least the foreseen operating voltage between • the turn-off voltage can be adjusted to be |𝑉𝑔𝑠 | ≲ 3 V;
the gate and the drain (this topic is outside of the scope of the present
paper). While JFETs are known to be resistant to a large extent to ionization
Another difference is the amount of the gate leakage current. As the damage [8], tolerance to displacement damage can be an issue. The radi-
depletion region extends into the substrate, a leakage current will be ation damage increases the effective ohmic resistance of the undepleted
generated in this volume. This current flows between the drain and the substrate in the ON state, with the net result that, for the same 𝑉𝑑𝑠 and
gate and, for geometrical reasons, is much higher than in the standard 𝑉𝑔𝑠 , a lower current flows. To mitigate this issue, larger devices, made
JFET. by very wide sources, should be chosen by design. Also, low resistivity
In Fig. 3a, the electrostatic potential in the bulk, a few microns thin substrates would be preferable, but would lead to lower breakdown
from the Si/SiO2 interface, is plotted in the case of 𝑉𝑔𝑎𝑡𝑒 = −0.5 V and voltages as opposed to the 500 V requirement above. On the other hand,
𝑉𝑑𝑟𝑎𝑖𝑛 = 100 V. The potential distribution within the channel is very larger devices lead to higher gate currents after irradiation in the OFF
similar to the one expected in the regular JFET in saturation for the state. In fact, if before irradiation the gate leakage current is negligible,
same 𝑉𝑔𝑎𝑡𝑒 ; in fact the currents are almost the same. Despite the high
during irradiation the gate current scales up with the fluence and the
voltage applied to the drain, the bottom gate prevents the high voltage
depleted volume below the bottom gate.
from penetrating the gap and limits the maximum voltage in this region
to only about 6 V. The electron current that flows in the channel is To check if this device can sustain the maximum expected fluence
shown in Fig. 3b. It flows from source to drain without encountering of 1.2 ⋅ 1015 𝑛𝑒𝑞 ∕cm2 , TCAD simulations have been run inserting the
any potential barrier along its path and along the maximum gradient of radiation-generated traps according to the ‘‘Perugia model’’ [9]. We
the electrostatic potential. used again the structure of Fig. 2, which refers to a device 1 μm wide
In Fig. 4, for the same bias point of Fig. 3, the equipotential lines (the width is the dimension into the paper). From the results, a source-to-
in the bulk are shown. In these simulations, the bulk is an n-type drain current of 10 nA has been obtained at 𝑉𝑔𝑎𝑡𝑒 = 0 V (i.e. ON state), a
epitaxial layer 50 μm thick (doping concentration of 1014 cm−3 , so the 103 decrease with respect to the pre-irradiation simulations. Since after
depletion voltage is 200 V). The simulation has been done below the irradiation, the total sensor current is expected to be 1 mA, a device
depletion voltage with 𝑉𝑑𝑟𝑎𝑖𝑛 = 100 V. Nevertheless, the substrate is width of 1 mA∕(10 nA∕μm) = 10 cm is therefore needed. Considering
slightly depleted by the current flow, which creates a voltage drop in that the device in Fig. 2 is 25 μm long, 40 of them can be parallelized in
the resistive substrate. Note how the current spreads laterally. an interdigitated configuration to fit in a length of 1 mm. In a 1 ⋅ 1 mm2
This new device potentially satisfies the conditions required (or area, thus, a 40 ⋅ 103 μm = 4 cm wide device can fit and, accordingly, a
preferred) for HV Mux: 10-cm wide vertical JFET can be as small as 2.5 mm2 .
• a voltage larger than 500 V can be sustained by the bottom The post-fluence gate leakage current will be 7.5 μA, considering
gate/drain junction, once the substrate doping concentration and a depleted volume of 50 μm ⋅ 2.5 mm2 and a damage constant of 5 ⋅
thickness are optimized. High-resistivity thick substrates are pre- 10−17 A∕cm [9], as confirmed by the same TCAD numerical simulations.
ferred ([7], chapter 2); These numbers are within the specifications.

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source-to-drain current flows. We simulated the output characteristics

of a few structures that differ from the reference geometry in Fig. 2 just
by the gap length (10 or 15 μm instead of 5 μm). We verified that the
saturation current for a given gate voltage is the same. This indicates
that the potential distribution inside the channel, which governs that
amount of current flowing through the channel, is unaffected by the
gap dimension. Therefore, the turn-off voltage remains the same. The
saturation voltage 𝑉𝐷,𝑠𝑎𝑡 , however, depends on the gap dimension as
shown in Fig. 5. Larger gaps result in lower 𝑉𝐷,𝑠𝑎𝑡 since the drain voltage
is less effectively shielded by the bottom gate and thus more strongly
influences the channel potential. Making the gap longer introduces an
unwanted effect: there is an increase in the peak electric field at the
top gate/channel junction at mid-gap, which can potentially lead to
breakdowns. Here, higher electric fields develop because the channel
sees a large voltage under the gap. As can be seen in Fig. 6, the larger
the gap, the greater is the electric field. However, the magnitude of the
electric field in this region is almost impossible to calculate analytically
and must be numerically simulated.
Fig. 5. 𝑉𝐷,𝑠𝑎𝑡 as a function of the (half) aperture in the bottom gate, for different gate Increasing the channel doping results in higher turn-off voltages
voltages.
and higher electric fields at the top gate/channel junction (a shown
in Fig. 6), which limits the maximum operating drain voltage that
avoids breakdown. However, it is interesting to notice how the output
characteristics modify under an increase of the doping concentration of
the channel, while keeping all the other parameters fixed as in Fig. 2 (so,
the gap length is again 5 μm). In the case of a doping of 3 ⋅ 1016 cm−3 ,
as in Fig. 7, for 𝑉𝑔𝑎𝑡𝑒 = 0, the device reaches the saturation regime for
drain voltages much larger than 1 kV, since the channel does not reach
the necessary voltage to pinch off the channel. For higher gate voltages,
the drain current can reach saturation, although at very high voltages.
For example, at 𝑉𝑔𝑎𝑡𝑒 = −1 V, 𝑉𝐷,𝑠𝑎𝑡 = 1000 V. The output characteristics
of a few vertical JFET structures have been simulated, which differ only
for the doping of the channel, while keeping the gap dimension at 5 μm,
as in Fig. 2. The 𝑉𝐷,𝑠𝑎𝑡 extracted from these curves is reported in Fig. 7:
as can be seen, it is a strong function of the channel doping. In the
HV-Mux application, when in the ON state, the device does not need to
operate in saturation, provided the current capacity is high enough in
the linear region. However, the 𝑉𝐷𝑆 must be minimized to reduce the
power dissipation within the HV-JFET.
Fig. 6. Vertical cutlines of the electric field at mid gap in the OFF state, for structures
differing for the gap length or the channel doping. In all cases, 𝑉𝑑𝑟𝑎𝑖𝑛 = 500 V, while
𝑉𝑔𝑎𝑡𝑒 = −2 V for the channel doping of 1016 cm−3 , and 𝑉𝑔𝑎𝑡𝑒 = −6 V for the channel doping 4. Situation in a real device
of 3 ⋅ 1016 cm−3 .
The device structure of the reference geometry is clearly an over-
simplification of a real device. Its aim was to help in determining the
3. Effect of gap dimension and channel doping device performances and the main parameters that govern the behavior
of the device. During an actual fabrication, an approximation of this
One important feature in the design of the HV-JFET is the dimension geometry can be obtained if we follow a process flow as sketched in
of the gap in the bottom gate, covered by the top gate, through which the Fig. 8, left column, which is like the one described in [10]. Here, over

Fig. 7. Left: output characteristic of a HV JFET with channel concentration of 3 ⋅ 1016 cm−3 , instead of 1 ⋅ 1016 cm−3 , as in the structure of Fig. 2. Right: 𝑉𝐷,𝑠𝑎𝑡 as a function of the channel
doping concentration, for different values of the gate voltages.

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Fig. 10. Output characteristic of the HV JFETs of Fig. 8: solid (respectively dashed) lines
refer to the structure in Fig. 9a (respectively b).

The term ‘‘horn’’ has been introduced in [10], where a description of

Fig. 8. On the left, process flow using an additional epitaxial layer growth which can this effect is detailed. The acceptors introduced by this implant (boron)
avoid the horn effect: (a) a low energy boron implantation (in the case of an n-type JFET)
is performed, the pattern being defined using a standard photoresist, (b) an additional
can compensate for the donors of the channel implant (phosphorus) and
epitaxial layer is grown on the top, and the implant is diffused, (c) another boron implant block (or limit) the source-to-drain current (Fig. 8f). As a consequence,
connects the deep boron implant to the surface, for metal connection. The other implants the implanted dose of the bottom gate must not be too high with respect
(source, channel and top gate) are within this well. Right, process flow using only ion- to the implanted dose of the channel. For example, in Fig. 9, the problem
implantations: (d) high-energy boron implant, suffering from horn effect, (e) the same
is depicted. Here the channel is as in Fig. 2 (1 μm thick and 1016 cm−3
implant as in c) may be needed, (f) the channel implant must be high enough for it not to
be compensated by the bottom gate implant. doped, simulating a net implanted dose of 1012 cm−2 ). Fig. 9a shows
the case when the bottom gate has been implanted with a boron dose
of 1.2 ⋅ 1012 cm−2 , and a horn is visible, connecting the edge of the
bottom gate to the surface. Still it is not enough to compensate the n-
the thickness of the substrate (which can be an epitaxial layer), a bottom
type channel. Fig. 9b shows the case in which a dose of 1.4 ⋅ 1012 cm−2
gate implant is first performed (Fig. 8a) and then a second thin epitaxial
layer is grown (Fig. 8b). This epitaxial layer, if properly doped, can act is implanted, which is slightly larger than the case in Fig. 9a: in this
as the channel of the JFET; however in this case it will extend also situation the horn compensates for the channel doping, resulting in a
externally to the bottom gate and potentially cause problems in the parasitic junction between channel and bottom gate.
guard ring termination. A possible alternative is to grow an epitaxial The effect of the presence of the horn on the I-Vs of the output char-
layer as doped as the substrate and to implant on it the channel. On this acteristics is striking (Fig. 10). A horn which is unable to compensate
additional thin epitaxial layer, the other implants, such as the top gate for the channel doping does not affect the current, which is the same
and the source, can be then implanted and diffused. It may be necessary as in Fig. 3 (in fact the horn is in a region where the currents already
to implant also a boron layer to ohmically connect the bottom gate at experience a drift toward the drain). On the other hand, a horn which
the surface (Fig. 8c). If we are limited by process capability to use just compensates for the channel doping severely decreases the amount of
a single epilayer planar process, this ideal situation is not achievable. current and lowers the turn-off voltage as well. The horn effect, thus,
In this case, the starting point will be the epitaxial layer (or the high- must be avoided in an actual fabrication. Since the doping of the horn
resistivity wafer) in which the bottom gate is implanted first (Fig. 8d), is not controllable, it is advisable to process in parallel a few wafers
by means of a high energy ion beam. Since in the region of the gap differing for the channel dose to have at least one functional wafer
there are a thick oxide and a photoresist to prevent the bottom gate among them.
high-energy implant to go through, we suffer from a ‘‘horn effect’’ at the The channel doping is constrained by the requirements to have
edge of this region, where some of the bottom gate implant gradually reasonably low turn-off voltages, and to avoid high electric fields below
passes through the stack and finally reaches the silicon/oxide interface. the top gate. This constrains the doping of the bottom gate (as to avoid

Fig. 9. Simulations of possible structures fabricated in a single-epitaxial layer planar process. A ‘‘horn’’ appears, when the bottom gate implant, which goes through the oxide/resist
stack at the edge of the gap, compensates for the channel doping. In (a) bottom gate dose is 1.2 ⋅ 1012 cm−2 , in (b) bottom gate dose is 1.4 ⋅ 1012 cm−2 .

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Fig. 11. For the geometry shown in (a), (b) shows the electric field at breakdown, in this case at 𝑉𝐷 = 850 V.

the horn effect), which can be so low as to result in a non-negligible intercorrelated, and additional care is needed in optimizing within that
depletion of the bottom gate implant, as large drain voltages are applied parameter space. In fact, at BNL we did fabricate working prototypes of
to the JFET. This is especially severe when the resistivity of the epitaxial both 𝑛-type and 𝑝-type HV vertical JFETs using the planar process only:
layer is not high. For example, an epitaxial thickness of 50 μm with a the adopted fabrication technology as well as the measurement results
donor doping of 1014 cm−3 (as the one used in the simulations) has an will be detailed in a future paper.
integrated dose of 5 ⋅ 1011 cm−2 , about half of the bottom gate dose.
This fact can also limit the maximum voltage that can be applied to Acknowledgment
the drain. These considerations show that the parameter space that
can be chosen for a fabrication is limited but, as demonstrated by the This material is based upon work supported by the U.S. Department
TCAD simulations reported in Fig. 9, it is still wide enough to assure a of Energy, Office of Science, Office of High Energy Physics, under
functional production. contract number DE-SC0012704.
We expect differences between the breakdown voltage in a simple
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