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CVD Assignment-1

This document outlines the assignment for III B.Tech II Semester in CMOS VLSI Design, detailing course outcomes and associated Bloom's levels. It includes questions divided into Part-A and Part-B, covering topics such as switching characteristics, logic styles, and propagation delays in CMOS circuits. The assignment is scheduled for March 2025 and carries a maximum of 20 marks.

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5 views

CVD Assignment-1

This document outlines the assignment for III B.Tech II Semester in CMOS VLSI Design, detailing course outcomes and associated Bloom's levels. It includes questions divided into Part-A and Part-B, covering topics such as switching characteristics, logic styles, and propagation delays in CMOS circuits. The assignment is scheduled for March 2025 and carries a maximum of 20 marks.

Uploaded by

aravindkumar3375
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Hall Ticket No: Course Code: A8428

III B.Tech II Semester Assignment - I, March - 2025


(Regulations: VCE-R22)
CMOS VLSI DESIGN
(ECE)
Date: 21/03/2025 Max. Marks:20 Marks
Answer all Questions in Part-A
Answer any Three Questions in Part-B
Course Outcomes with Bloom’s Levels:

Bloom’s
CO# CO Statement
Level (L#)
CO1 Analyze the switching characteristics of CMOS circuits L4
CO2 Analyze the characteristics of logic styles to build complex circuits. L4
CO3 Construct logic circuits using static, dynamic and transmission gate-based logic styles. L3
CO4 Apply clocking and data synchronization in dynamic circuits. L3
CO5 Analyze logic circuits using dynamic and differential logic design styles. L4
Questions:
PART-A
COs BLs Marks
1. a) Write short notes on channel length? CO1 L3 1M
b) Define Noise Margin? CO1 L1 1M
c) Write the Ids current equations in cutoff, non-saturation and saturation 1M
CO1 L3
regions of nMOS transistor?
d) Define rise time and fall time? CO1 L1 1M
e) Distinguish between enhancement and depletion mode transistor? CO1 L4 1M
PART-B
2. Derive the expression for drain to source current (Ids) versus drain to source
CO1 L4 5M
voltage (Vds), Assuming that nMOS transistor is in non-saturation region.
3. Draw and explain the DC and transfer characteristics of a CMOS inverter
CO1 L2 5M
with necessary conditions for the different regions of operations.
4. Analyze the five regions of operation of CMOS inverter with the help of its
CO1 L4 5M
voltage transfer characteristics.
5. Discuss the importance of Maximum Switching Frequency of CMOS
CO1 L2 5M
inverter.
6. Use RC model to obtain simpler expressions for the propagation delay of
CMOS inverter.
i) High-to-low propagation delay, tPHL CO1 L2 5M
ii) Low-to-high propagation delay, tPLH
iii) Average propagation delay, tP

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