Birla Institute of Technology & Science, Pilani
Work Integrated Learning Programmes Division
First Semester 2024-2025
Mid-Semester Test
(EC-2 Regular)
Course No : ESZG626/MELZG651/SEZG626/SSZG626
Course Title : HARDWARE SOFTWARE CO-DESIGN
Nature of Exam : Closed Book
Weightage : 60 marks No. of Pages = 4
Duration : No. of Questions = 3
Date of Exam :
Note to Students:
1. Please follow all the Instructions to Candidates given on the cover page of the answer book.
2. All parts of a question should be answered consecutively. Each answer should start from a fresh page.
3. Assumptions made if any, should be stated clearly at the beginning of your answer.
Q.1. Introduction to HW and SW Co-Design [20 Marks]
A. Using the 8085 processor; Write the assembly SW routine for the “Linear Search
Algorithm”. The Linear Search Algorithm is defined as a sequential search algorithm
that starts at one end (the first memory index) and goes through each element of a list
until the desired element is found; otherwise, the search continues linearly till the end
of the dataset (the last memory index). If the element is not found even after reaching
the end of the dataset, a “fail” code (in this case say 0xFF) is returned. The question
and the solution are provided in the snapshot below. “Use Find ‘20’ and allow your
SW to do the same”.
B. If instead of using software on the 8085 processor for “Linear Search Algorithm”, it
was done using a peripheral, then draw the HW block Peripheral (IP) for the IP.
C. What are the different configurable registers that you’d provide with the simplistic
HW block Peripheral IP.
D. Draw a system level block diagram (SoC block diagram) with the Processor and the
HW Peripheral block.
E. Write a software program for the processor assuming the IP is part of the SoC.
Hints and Basic assumptions:
1. Keep the loops simple. Let the memory locations be incremental in nature.
2. The final memory location should be in the Accumulator of the 8085 upon finding
the right match.
3. The algorithm stops after the first match is found. No need to complicate by finding
duplicates et., all.
[6 + 4 + 4 + 4 + 2 = 20]
Q.2. Modeling Analysis and Estimation [20 Marks]
The Radix-2 butterfly is an atomic computation in DFT engines. The equation and the
diagram looks as the below.
A. Create a ‘data flow graph’ i.e, a task graph of how you would arrive at the solution of
the expression after evaluating the terms in the right order.
B. How many multipliers, adders, subtractors are needed.
C. If the multiplier takes 3 clock cycles, and adder & subtractor takes 1 clock cycles.
What would be the #clock cycles for the complete expression to be evaluated.
D. Mention the schedule (time taken) at each level of the graph.
Hints and Basic assumptions:
1. Keep it simple. Optimization and operator sharing is not expected.
2. The problem is not to provide a solution to the Digital Fourier Transform (DFT), but to
create the “data flow graph” of the equation which is used repeatedly in carrying out the
DFT.
[8 + 2 + 4 + 6 = 20]
Q.3. Binary Partitioning [20 Marks]
A. For the Graph as below with Tasks T1, T2, T3, T4 and T5 the HW / SW partitioning
for the same has been provided in the table. Enumerate the total number of ways in
which the partitioning can be done. Assume any number of components can be used
any number of times. Simplify the tabulation, if it gets too big.
B. Based on the enumeration done, mark the design scenario, which gives (1) the best
timing (2) the best area (3) the median point between timing and area.
C. Based on your experience with (a) and (b) derive a pseudo code of an algorithm
which can derive the best timing based partitioning.
[10 + 4 + 6 = 20]
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