VL St > Denqn Prddhndls QuelLa The combinational and sequential digital circuits have been discussed in earlier chapters. Various ICs for performing basic digital operations and other functions, such as-multiplexers, demultiplexers, adders, comparators, code converters, shift registers and counters, etc. have also been discussed. These ICs are referred to as _fixed-fuunction ICs, ie. each one of them performs a specific , fixed function. These devices are designed by their manufacturers and are ‘manufactured in large quantities to mect the needs of a wide variety of applications and are readily available. : To design a circuit, a designer can select from the available ICs most appropriate for the circuit, usually working from a block diagram design concept. The design may have to be modified to meet the special requirements of these devices. The advantages of this method are: 1. Low development cost, r 2. Fast turn around of designs, and 3. Relatively easy to test the cirenits Some of the disadvantages of this method are: 1. Large board space requirements, 2. Large power requirements, 3. Lack of security, ie. the circuits can be copied by others, and 4. Additional cost, space, power requirements, etc. required to modify the design or to introduce more features. To overcome the disadvantages of designs using fixed-function ICs, application specific inte- grated circuits (ASICs) have been developed. The ASICs are designed by the users to meet the specific requirements of a circuit and are produced by an IC manufacturer (foundry) as per the/ specifications supplied by the user. Usually, the designs are too complex to be implemented using fixed-finction ICs. . The advantages of this method are: )-\* 1; Reduced space requirement, 2. Reduced power requirement, 8. If produced in large volumes, the cost is considerably reduced, 4, Large reduction in size through the use of high level of integration, and 5. Designs implemented in this form are almost impossible to copy. The disadvantages of this method are: 1. initial development cost may be enormous, and 2. testing methods may have to be developed which may also increase the cost and effort, Another approach which has the advantages of both the above methods is the use of programmable logic devices (PLDs). A programmable logic device is an IC that is user configurable and is capable of implementing logic functions. It is an ISI chip that contains a ‘regular’ structure and allows the designer to customize it for any specific application, ie. it is ‘pro- grammed by the user to perform a function required for his application. PLDs have the following advantages of fixed function ICs: {i) Short design eycle (it) Low development cost The advantages over fixed-function ICs are: (}) Reduction in board space requirements (ii) Reduction in power requirements (iii). Design security (iv) Compact circuitry (v) Higher switching speed PLDs have many of the advantages of ASICs as given below: (i) Higher densities {ii) Lower quantity production costs (ii) Design security (iy) Reduced power requirement : (vy) Reduced space requirement ‘ The PLDs allow designers more flexibilities to experiment with designs be se these can be reprogrammed in seconds. The design deficiencies and modifications etc. can be carried out in short time thereby reducing the possibility of huge cost over-runs. PLDs are also useful for prototyping ASIC designs since foundry produced ASICs may require months of costly development. “ Because of various advantages of PLDs mentioned above, a large number of PLDs have been produced by IC manufacturers with variety of flexibilities and options available for a Gireuit designer and have become very popular. The architecture and various other features of PLDs such as ROMs, programmable logic arrays (PLAs), programmable array logic (PAL), simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), and field-programmable gate array (FPGA) have been discussed in this chapter. The use of these devices require changes traditional design methods, although the basic concepts remain the same. “aeele Re llnorenocanangeeseeeeeeees Read-only memories (ROMS) have been discussed in Section 11.6. A read-only memory is basically a combinational circuit and can be used to implement a logic function. A ROM of size Mx Nhas M number of locations and N number of bits can be stored at each location. The number of address inputs is P, where 2’= Mand the number of data output lines is N. It can also be considered as a logic device with Pinputs and N outputs as shown in Fig. 12.1. (Address) ROM (Data) inputs MN outputs Fig. 121 ROM as a combinational circuit, The 16-bit ROM array shown in Fig. 11.14 has four inputs and one output, ie. M= 16, N=1 and P= 4. The bit pattern stored, as given in Table 11.5, can be considered as truth table with 4, 4; 4, Ay as 4-bil input and Yas the output which is same as the bit stored. The logic fimetion corresponding to this is ¥= ¥ m(0, 6, 9, 12, 13, 15) In general, a P variable, N outputs logic function can be implemented using a ROM of size 2! N since all the possible 2” minterms are effectively generated as is clear from the above discussion If a mask programmable ROM is used, the user can specify the bil pattern to be stored according to the requirements of the logic function, whereas the user can himself program it in case of PROM, EPROM and E?PROM. Since programmable ROMs can be used for logic design, therefore, it is also referred to as a programmable logic device (PLD). The advantages of using ROM as a programmable logic device are: 1. Ease of design since no simplification or minimization of logic function is required. 2. Designs can be changed, modified rapidly. 3. It is usually faster than discrete SSI/MSI circuit. 4. Cost is reduced. . There are few disadvantages also of ROM-based circuits, such as non-utilization of complete circuil, increased power requirement, and enormous increase in size with increase in number of input variables making it impractical. A programmable logic device (PLD) usually consists of programmable array of logic gates and interconnections with array inputs and outputs connected to the device pins through fixed logic elements, such as inverting/non-inverting buffers and FLIP-PLOPs. The logic gates used maybe two-level AND-OR, NAND-NAND or NOR-NOR configuration. In some cases, AND-OR-SX-OR configuration is also used. Basically, there are two types of PLDs, programmable logic array (PLA) and programmable array logic (PAL). These are suitable for implementing logic functions in SOP for A PLA consi two-level AND-OR circuits on a single chip. The number of AND and OR iputs are fixed for a given PLA chip. The AND gai 's provide the product terms, and the OR gates logically sum these product terms and thereby generate a SOP expression. It has Minputs, n product terms, and N outputs with 1 <2", and can be used to implement a logic function of M variables with N outputs. Since all of the possible 2 minterms are not available, therefore, logic minimization is requited to accommodate a given logic function The internal architecture of a PLA is shown in block diagram form in Fig. 12.2. loo he ie te a 1 feta of} | treet LIE axe e| | butter * matrx tas Iss lags I, FP Prite[s Le! 5; Po) Fuae- | inven |) stores of noninvert |® | Output Outputs matrix Je] matrix |¢| butters S. {Sux te e— s Fig. 12.2 a Block diagram of a PLA device. 5AG3.1 input Butter The bufler circuits at the input are required to limit loading of the sources that drive the imputs. It produces inverted as well as non-inverted inputs at the output as shown in Fig. 12.3 for one input. Similar buffers are there for each of the M inputs. ea ig. 123 An input buffer.12.3.2 AND Matrix An AND matrix is used to form product terms. A typical AND matrix is shown in Fig. 12.4 It has m AND gates with outputs P, through P,, and 2Af inputs (J through Jy, and 7, through 7,,_,) for each AND gate. This shows that each AND gate has all the input variables in complemented and uncomplemented form. There is a nichrome fuse link in series with each diode. All the links are intact in an unprogrammed PLA device. Each AND gate generates one product term which is given by Poly hy hy ty ly te and it is logic 0 in an unprogrammed device. For generating a required product term the unwanted links are opened through the method of programming by a programmer device in case of a field-programmable logic device (FPLA). A section of the AND matrix for F, output is 8 Nichrome: Vee cells ; S " i 2 2 $ Pe Fig. 12.4 An AND matrix.shown in Fig, 12.5a and its equivalent logic gate representation is shown in Fig. 12.56, A similar arrangement exists for each of the other outputs. Fig. 12.5 A section of the AND mai Vee Jy a0 9 + Ty o—\ 9— a Ty 2 2 ioe 1, oe | \ toe T oN» oP, : j Toa ° I hay SNe 0 Po Tas be tus o—\ 9 —< ‘ we bet ge fa) (b) Figure 12.6 illustrates a convenient method of showing the input buffers and the with the interconnections marked as Xs, Each AND gate has 2M inputs which is indicated by a single line in the figure. When an array is programmed to implement a particular logic func tion, the desired interconnections are left with X marks and the unwanted interconnections without X marks. 12.3.3 OR Matrix The OR matrix is used to produce the logical sum f the product term outputs of the ANO matrix. Figure 12,7 shows an OR matrix using RTL circuitry. An OR gate consists of parallel connected transistors with a common emitter load. The outputs of the OR matrix are obtained at S$, through Sy ,. Consider the output S, when all the fuse links are intact, which is given by H= P+ Pt. t+ Pry ‘The required sum terms can be generated by opening the unwanted fuse kinks. For example,Ins Po Py Pe Pos Fig.126 - a Representation of input buffers and AND matrix. Py Pp, Poa Pot Voc o- -- : to les Fig. 12.7 ‘An OF matrix.if all the fuse links, except the ones for the product terms P, and P,, are blown off for the output S, then RaRth Thus an OR matrix can be programmed by opening the unwanted fuse links, which effec. tively makes logic level 0 at the corresponding OP. gate inputs. Figure 12.8 gives logic symbol for one of the OR gates, and Fig. 12.9 illustrates the relevant portion of the PLA containing OR matrix in a way similar to Fig. 12.6. Fig. 12.8 I Logic symbol of a section of OR matrix Fig. 129 Representation of matrix, 12.3.4 INVERT/NON-INVERT Matrix This is a programmable buffer that can be set for INVERTING or NON-INVERTING operation corresponding to activelow or active-high output, respectively. Typical circuits for this opera- tion are shown in Fig. 12.10. _ In the case of an EX-OR gate, if the fuse is intact, the output is S, whereas the output is 9 if the fuse is blown off. Similarly, the output in case of Fig. 12.1048 S or S depending upon whether the fuse is intact or open. 12.3.5 Output Buffer Output buffers are required to increase the driving capability of the PLA. Usually, the outputs are TTL compatible. The outputs may be totem-pole, open-collector, or three-state. Figure 12.11 shows the three-state output buffers.§o——_— )> . > ——e sr $ so—l[>o sos (@) Fig. 12.10 oe Inverting /non-inverting circuits. Fig. 12.11 Output buffers Ps and Buffers 12.3.6 Output through PLIr-i The PLA devices suitable for state machine applications have PLIP~ output cireuitry as shown in Fig. 12 12 In this positive-edge triggered. S-R Fs are connected al the outputs of the OF gates, and the device outputs are available through tristate buffers. Ps and buffers in the 12.3.7 Programming the PLA A PLA device is to be programmed for the desired input-output telationship similar to the programming of ROMs. For a mask-programmable PLA. device, the data pattern is to be specified by the customer. The appropriate masks are designed by the manufacturers and the data pattern are built in during the manufacturing process. An FPLA has all its nichrome fuse links intact at the time of manufacturing. The unwanted links are electrically open circuited during programming The links to be opened are accessed by applying voltages at the inputs and outputs of the device, The FPLAs are not reprogrammable. 12.3.8 Expanding PLA Capacity Some applications require a capacity that excees: the capacity of a single PLA. The required capacity can be achieved by suitably connecting several identical devices together. For increas-Clock ee + ss @ | Fy = R on Matrix acs 7 s Q F, tet Na R . i ; . 1 1 oe . 1 , . \ =F “ al | ae R Fig. 12.12 A section of PLA with sin the output ing the number of outputs, the inputs of two or more devices are to be connected individually in parallel. This connection does not change the number of inputs and the product terms. For increasing the number of product terms keeping the number of inputs and outputs unchanged, the inputs and outputs of two or more devices are to be individually connected in parallel. ‘The number of inputs-can-be increased by making the connections as shown in Fig, 12.13. This Greuit has (M+ Q) inputs and N outputs. This connection also increases the number of product terms. he number of product terms is Px (2% ~ 1). The outputs are allowed to be connected ‘together for the devices with passive a up only, _A2.3.9 Applications of PLAs ‘The PLAs can beused to implement combinational and sequential logic circuits. For the design of combinational circuits, PLAs with output cireuit as shown in Fig. 12.10 or Fig. 12.11 are uused, whereas the devices having FL1P-FLOPs in the output circuit ay shown in Fig. 12.12 are required for the design of sequential circt ‘The following steps can be used for 1. Prepare the truth table. 2. Write the Boolean equations in SOP form. plenrenting combinational logic functions: