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Low Power Text Compression for Huffman Coding
using Altera FPGA with Power Management
Controller
Maan Hameed Hussein Shakor Intesar Razak
Ministry of Water Resources, State Department of Communications Ministry of Water Resources, State
Commission for Reservoirs and Dams, Engineering, University of Diyala Commission for Reservoirs and Dams,
Iraq Iraq Iraq
[email protected] [email protected] [email protected]Abstract: Huffman coding is very important technique in transmit a specific in an efficient form [2]. Furthermore, the
information theory. It is the process of encoding data using fewer demand in the increased low power and high performance in
bits than an uncompressed data. Furthermore, Clock gating and
frequency scaling are efficient techniques for reducing power electronic devices has led to the research of low power
consumption in sequential design. It saves more power by technique [3]. Power dissipation are estimated by several
partitioning the main clock and distributing the clock to the logic factors such as leakage power, short-circuit power and
blocks only when there is a need for those blocks to be activated.
dynamic power including the frequency, supply voltage,
This paper aims to design and implementation of Huffman
coding based on binary tree using FPGA (Field Programmable switching activity and capacitor [4]. The power dissipation
Gate Arrays), and proposing a novel method of clock gating and mathematical presented in equation (1).
frequency scaling to achieve low power consumption and
reliability of design. The proposed Huffman was achieved Power consumption= dynamic power +short circuit power+
47.95% saving percentage in data size. While, reduce power
consumption up to 52.52% comparing to traditional design.
leakage power (1)
Huffman design was implemented by using ASIC and FPGA
design methodologies. In order to implement the encoder and Dynamic power involved switching activity, because the
decoder architectures, 130 nm standard cell technology libraries current flows only during logic transitions on the net, the term
were used for ASIC implementation. The simulations are carried of dynamic power depends on the clock frequency (possible
out by using Modelsim tool. The architecture of coding and transitions per second) and the switching activity (presence or
decoding process has been created using Verilog HDL language. absence of transitions actually occurring on the net in
Quartus II 11.1 Web Edition (32-Bit). In addition, simulated successive clock cycles). Synopsys power compiler is a tool
using ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition. used to automatically downsizing power dissipation at the
Keywords: clock gating, power dissipation, data compression,
Gate Level and Register Transfer Level (RTL) of design. After
FPGA, ASIC and binary trees. uploading a full Huffman design in Synopsys tool, with
specific system restrictions, the power compiler implements
improvements for the area, timing, and power with each other
[5]. In this field, Suvvari, et al., [6]. Proposed Huffman
I. INTRODUCTION decoder is implemented by using FPGA and ASIC design
Based on computation algorithms, compression processes methodologies. Huffman architectures is implemented on
are divided into two categories such as loss/lossless. In 0.6-micron standard cell libraries for power consumption
general, medical images are compressed in a lossless manner analysis.
in order to preserve details and to avoid wrong diagnosis. The In the same direction, Bedruz and Quiros, [7] introduced a
advantages of this compression are efficient usage of channel comprehensive study for two of the most common and most
widely utilized for data compression techniques are the
bandwidth and storage size data Source coding using Huffman
Huffman coding and Lempel-Ziv coding. The main objective
compression algorithm reduces the number of bits in the data of this research is to identify which technique is better in text.
when it compared with the ASCII representation of the string. Farthermore, Soni and Hiradhar [8]. Proposed a new technique
Text coding is an application of data compression that encodes for clock gating will provide immunity to the current problem
the original text with few bits [1]. The objective of data was obtained from the existing techniques. Those methods
compression is to reduce the redundancy of the text to store or which required less size had problem in other areas like
978-1-5386-1498-3/ 18/31.00$©2018 IEEE
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glitches while those approaches that required large size did not
have glitch problem but increase static problem.
In this paper, the proposed Huffman using binary tree
was implemented to produce VLC for all English alphabets.
Then, Low Power Management Control (PMC) at the sub-
system level is applied for the encoder and decoder process.
Also the proposed Huffman design which is synchronous
system work with reference to the clock input of design and
the clock consumes power up to 30% of the total power
consumption of design.
II. HUFFMAN DESIGN METHODOLOGY
In this section, the procedures for building Huffman coding
and low power analysis were discussed. Furthermore, the steps
of implementation on FPGA with validations in module level
design and top-level design were discussed too. In Fig.1,
shows the steps taken in designing this project. Basically, the
methodology of Huffman design consists of seven stages. The
first two steps relate to Huffman construction, the third step is
special for Huffman implementation on FPGA, the last four
steps relate to improvement and analysis of power
consumption of Huffman as shown in Fig. 1. During power
analysis section was used different values of frequencies to
show the design limitations and avoid design restriction
frequencies.
A. Steps Of Building Huffman Tree
Production of a list of symbols sorted by frequency can
be done using priority queues. Huffman coding process has
Fig. 1 Design methodology
been proven to be advantageous in reducing the overall length
of the information because it assigns smaller code words to Then, there will be removal of the component nodes from the
more frequently occurring symbols, and employs the list. After that, the parent node is added to the list of free
procedure of exchanging fixed length codes for input data nodes. This process is repeated until the construction becomes
ASCII by VLC. The procedure for constructing Huffman tree a single tree [9]. After generating Huffman tree, the procedure
involves making a list of free nodes, and then selecting two of algorithm generates a codeword for each symbol from the
free nodes with the lowest weight from the list. It should be text simply by traversing the binary tree from the root to the
noted that each node match to a letter in the alphabet. After node. Huffman codewords and the frequencies of data must be
that, there will be creation a new node named a parent for the stored. This information is required in decompression process
two selected nodes and its weight is equal to the sum of the and it is stored in the header of the compressed file. Initially,
weight of the nodes used to generate new parent node. each node contains a symbol and its probability. Huffman tree
is employed by encoder and decoder. The alphabet consists of
the uppercase letters and space. Huffman tree is based on the
following assumed frequencies: {(E 130), (T 93) ,(N 78), (R
77), (I 74), (O 74), (A 73),( S 63) ,(D 44) ,(H 35),( L 35),( C
30),( F 28),( P 27),( U 27),( M 25), (Y 19),( G 16),( W 16),( V
13),( B 9),( X 5),( K 3),( Q 3),( J 2),( Z 1)}. Each number
represents the frequency of each character. Every 1000 letters
have 180 spaces. Arrange the alphabet characters in ascending
order by their frequencies for generating Huffman tree as
shown in Fig.2. HDLs and their simulators allow designers to
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partition their designs into components that can work B. Performance Measures
concurrently and communicate with one another. Fig. 3 shows When estimating the quality of execution, the main
all inputs and outputs for Huffman design and top-level difficulty will be size competence. Coding mode which
simulation. depends on the repetition of symbols in the text, the quality of
compression depends on the model and the arrangement of the
input source. Estimation of compressed size will be done by
determining the size of the uncompressed data. This is equal to
sum of the frequencies of all the letters of alphabet.
Calculation of total size for original data is shown in equation
(2). Equation (3) shows the process of calculating compressed
data size [10].
Original size=total frequency*ASCII (2)
Original Data Size = 1180 * 8 = 9440 bits.
Compressed size=cod word*frequency (3)
Compressed Data Size = 4913 bits
Saving percentage is derived through calculating the shrinkage
of the source file in percentages. This is widely accepted as the
measure of efficiency of a compression and is defined in
percentage [11].
Saving Percentage = ((original size - new size)/original size)
*100% (4)
Saving Percentage = 47.95%.
The proposed method of Huffman design has high
saving percentage of data size up to 47.95%. Fig. 4 shows the
comparison of compressed and uncompressed sizes. The VLC
Fig. 2 Huffman binary tree for compressed size has been obtaining in an appropriate way
depend on the calculated probability of occurring for any
possible value of the source file. Furthermore, measuring
performance of the proposed method for compression process
based on the type and the structure of the input data and
constructing Huffman tree for generating the code words.
Fig. 3 Full Huffman design waveform validation
Fig.4 Compressed and uncompressed sizes
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III. FIELD PROGRAMMABLE GATE ARRAY
Field Programmable Gate Arrays (FPGA) is a newly Total Huffman Power=encoder (mode) +decoder (mode)
tool to achieve the real-time implementation for Huffman +PMC power (7)
design, there is need for starting new step of the design. Altera Total Huffman Power=encoder (slow) +decoder (off) +PMC
power (8)
Quartus II design software is used in conjunction with FPGA.
Total Huffman Power=encoder (high) +decoder (off) +PMC
It maps the design for a particular resource on the FPGA and
power (9)
check that the design meets the coding constraints. The data
Total Huffman Power=encoder (off) +decoder (slow) +PMC
file is converted to text file because FPGA can interpret the
power (10)
digital values. Moreover, this text file is regarded as input file
for FPGA kit [12]. This technology used to simulate designs to
Total Huffman Power=encoder (off) +decoder (high) +PMC
get real system behavior. In the proposed design, 8 LEDs
power (11)
green, 18 LEDs red and 18 SW was used to implement the
design on FPGA. In encoder implementation, 8 LEDs green TABLE II. POWER ANALYSIS FOR FOUR DIFFERENT MODES.
are used to represent the ASIC encoder input. The first 9
Decoder S.M Decoder
switches and the first 9 LEDs red are used to represent the Frequency Encoder S.M Encoder H.P
H.P
encoder outputs. Furthermore, the last four LEDs red are used 40 0.01508 0.02907 0.01494 0.02799
to represent the output length. However, in decoder
80 0.02991 0.05788 0.02963 0.05575
implementation, the first 9 LEDs red are used to represent the
120 0.04473 0.08670 0.04433 0.08351
decoder input and the 8 LEDs green are used to decoder
output. 160 0.05955 0.11551 0.05902 0.11127
IV. POWER ANALYSIS PHASE 1 From Table II, Encoder S.M show the power consumed in
Power dissipation includes two types of power: static Encoder slow mode power analysis (eq.8). Encoder H.P show
power and dynamic power [13]. Static power is very small and the power consumed in Encoder high power analysis (eq. 9).
the main effect of the total power consumption is generated Decoder S.M show the power consumed in Decoder slow
from dynamic power. For dynamic power, it consists of mode power analysis (eq.10). Decoder H.P show the power
internal power and switching activity. From Table I, it is consumed in Decoder Huffman high power analysis (eq. 11).
concluded that the main effect of the low power techniques
It is clear from table II, that the power consumption was
used in this research is to reduce the switching, because of the
increased when the design worked in high performance, while
static power is very small and the main part for consisting total
the power consumption decreased when the design worked in
power is the dynamic power.
slow mode. Therefore, the design work in high performance
when required only to avoid losing power. High frequency
TABLE I. POWER CONSUMPTION FOR STANDARD HUFFMAN (PHASE1)
referred to the design work in high performance, while low
No Freq.(MHz)
Dynamic Total frequency referred to the design work in slow mode.
(mW) power(mW)
1 40 0.03098 0.03119
2 80 0.06205 0.06227 VI. POWER MANAGEMENT CONTROL
3 120 0.09308 0.09329 Power Management Control (PMC) combines two
4 160 0.12411 0.12431 techniques to create a signal that can make the output design
overcome the limitations of power dissipation and data size
[14]. Fig. 5 shows the hardware design for PMC to achieve the
function of clock gating and frequency scaling, the clock
V.POWER ANALYSIS PHASE 2
signal created named Power Optimization Frequency Scaling
The procedures for estimating power consumption for and Clock Gating (POFSCG) for encoder and decoder
each mode of Huffman design is by separating each sub- modules. The procedures of clock gating refer to activation of
module and present it as a top-level design for power clocks in the logic block when there is work to be done only
consumption estimation. and switch off the clock in the second module. This way leads
significantly reducing power consumption in Huffman design
Power consumption= dynamic power +static power (5)
[15]. The second signal named high_slow (h_s) mode. It is
used to determine the function of frequency scaling. The
Total Huffman Power=encoder power +decoder power +PMC
ability of Master Clock Divider (MCD) in slow mode (8x) is
power (6)
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to determine the function of frequency scaling within the VII. CONCLUSION
boundaries of Huffman design. Therefore, PMC has two This paper has shown that higher level data help increase
phases in its mode of operation for each module that is the compression quality. The proposed design is used to
controlled by the two-input signal as shown in Table II. The compress text files of size 9440 bits to achieve a new
improved version of Table III in the simulation waveform is compressed size of 4913bits and has saving percentage about
shown in Fig. 6. 47.95% of the original size. Embedding PMC was successful
to synthesize and analyze power in four different cases. The
method for power calculation by considering each sub-module
TABLE III. HUFFMAN OUTPUT OPERATION MODE
separate led to calculate the exact power consumption in each
CG FS Huffman output phase
sub-module and complete full design. High percentage in
power consumption was achieved in Huffman encoder and
0 0 Decoder Huffman _Slow_ Mode decoder saving modes. It achieved 52.52% in decoder slow
0 1 Decoder Huffman _ High _ Performance
mode. This led to achievement of 52.10% in encoder slow
mode. The experiments with a simulated environment and
1 0 Encoder Huffman _ Slow _ Mode
real-time implementation of FPGA with Synopsys power
1 1 Encoder Huffman _ High _ Performance analysis show that the constraint has been fulfilled and the
target design of the buffer length is appropriate. Finally, data
compression besides low power techniques and FPGA
technology can improve and make the system completely at
high-level. This paper provides a strong foundation for the
excellent career as an ASIC designer.
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