Superlattices and Microstructures 144 (2020) 106574

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Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Assessment of Dual-Gate AlGaN/GaN MISHEMT for high

temperature DC to DC converter
Preeti Singh a, Vandana Kumari b, Manoj Saxena c, Mridula Gupta a, *
a
Department of Electronics Science, University of Delhi, South Campus, New Delhi, 110021, India
b
Department of Electronics, Maharaja Agrasen College, University of Delhi, New Delhi, India
c
Dept. of Electronics Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India

A R T I C L E I N F O A B S T R A C T

Index Terms: Numerical assessment of Dual-Gate AlGaN/GaN MISHEMT have been presented in this paper.
—MISHEMT Analytical model has been developed and the various parameters extracted are surface potential,
TCAD electric field and threshold voltage for different device specifications. Threshold voltage of nearly
Modeling
0.15 V has been computed which is nearly same to that of simulated Dual-Gate MISHEMT.
Dual-gate
Converter
Simulations have been performed using ATLAS TCAD tool. Dual-Gate MISHEMT with different
gate dielectric materials such as Si3N4 and gate stack combinations like HfO2/Al2O3 has been
analyzed. From the results it has been inferred that at higher temperature, drain current and
transconductance reduces due to lower electron sheet concentration. Different combinations of
gate biases (applied at the second gate i.e. Gate 2 presented near the drain side) has been used for
optimizing the device parameter for better switching performance. For DG-MISHEMT with barrier
thickness of 22 nm (both the gates connected together), ION/IOFF ratio reduces from 109 to 106 for
high temperature (upto 423 K) due to reduced sheet carrier concentration. For inductance load,
output drain voltage exhibits voltage range of 9.2V/2.3V for gate pulse of -8V/þ2V with 30%
duty cycle. Also, it is seen that as barrier thickness is varied from 18 nm to 30 nm, IOFF increases
and results in reduced output drain voltages. Performance of Single Gate and Double Gate MIS­
HEMTs has also been compared for DC-to DC converter using inductance load circuit.

1. INTRODUCTION

With the growing demand for energy consumption (i.e. expected to increase by nearly 40% worldwide in next 20 years), highly
efficient power devices are needed for power electronics [1]. Devices based on wide bandgap materials such as GaN and SiC, have
become alternative to dominant silicon-based devices and meet the continuous demand of high voltage, current and power handling
capability [2]. Due to properties such as wide bandgap, high saturation velocity and high breakdown voltage, GaN
High-Electron-Mobility-Transistors (HEMTs) have demonstrated their candidature for future high frequency [3–5] and high-power
applications [6–10]. High sheet carrier densities with carrier mobilities upto 2000 cm2V-1.s 1 have been achieved in such devices
and this results in increased power densities and current drive capability as compared to devices based on Si or GaAs counterparts [11,
12]. Countless applications of GaN HEMTs have been reported recently such as power switch [13], dc-to-dc converter [14], resonant
converters [15], motor drives [16] etc. GaN power switch for kW power conversion with switching speed more than 2 MHz, reduced

* Correponding author.
E-mail address: [email protected] (M. Gupta).

https://doi.org/10.1016/j.spmi.2020.106574
Received 3 December 2019; Received in revised form 24 March 2020; Accepted 11 May 2020
Available online 16 May 2020
0749-6036/© 2020 Elsevier Ltd. All rights reserved.
P. Singh et al. Superlattices and Microstructures 144 (2020) 106574

Fig. 1. (a) 2D-Device structure of Dual-Gate AlGaN/GaN MISHEMT. Comparison of simulation and experimental [32] results (b) ID-VGS plot at VDS
¼ 8V (c) ID-VDS plot at VGS ¼ 0V and VGS ¼ 2V.

rise and fall times (<25ns) and switching losses ~11 μJ (resistive load) has been reported [17].
However, device performance of Schottky gated AlGaN/GaN HEMTs is restricted by high leakage current under reverse bias [18].
To improve the device performance, AlGaN/GaN MOS-HFETs have been reported by Khan et al. in Ref. [19]. Various gate insulators
have been identified such as Al2O3 [20], HfO2 [21], TiO2 [22], Si3N4 [23] etc. that resulted in suppressed gate leakage current [24] and
current collapse phenomenon [25]. MISHEMTs with HfO2 gate insulator exhibits small threshold voltage shift (towards negative
value), reduced transconductance with small increase in ON-current [26]. To improve RF power gain and reduce drain conductance,
Dual-Gate AlGaN/GaN HEMTs with Si3N4 gate insulator have been demonstrated in Ref. [27]. In our previous work [28], improved
threshold voltage stability has been reported using TCAD simulation for DG-MISHEMT with HfO2/Al2O3 gate stack against interface
charge density variation. Also, physics-based modeling of DG-MISHEMT need to be explored which is beneficial for understanding and
predicting the device performance.
This paper presents the influence of high temperature on DG-MISHEMT and TCAD simulations have been performed to evaluate the
performance in terms of ION, IOFF, trans-conductance and drain conductance of AlGaN/GaN DG-MISHEMT at various temperatures.
Surface potential based analytical model for Dual-Gate MISHEMTs have also been presented. Thus, this work presents the mathe­
matical expressions for Dual-Gate AlGaN/GaN HEMT with different gate dielectric to evaluate surface potential, electric field and VTH
(threshold voltage). The effect of permittivity variation of gate insulator and AlGaN barrier thickness has also been studied along with
temperature variation. The results of the analytical model have been verified with ATLAS TCAD simulation results [29]. Additionally,
performance has been evaluated for SG-and DG-AlGaN/GaN MISHEMTs for switching across an inductive load i.e. coil of
dc-to-dc-converter.

2. Model formulation

The AlGaN/GaN Dual-Gate MISHEMT used in this study is shown in Fig. 1 which consists of 22 nm AlGaN barrier layer with
aluminum mole fraction of 0.25. Hafnium oxide (HfO2) has been used as gate dielectric (with thickness of 10 nm) and as passivation
layer. The gate length of the device is 180 nm and distance between two gates (LGG) is 100 nm. The influence of interface traps and
substrate is not included in the development of the mathematical model for the device.
To develop the mathematical model for the device, the structure is divided into five regions: Region I - between source contact and
Gate 1 edge; Region II – under the Gate 1 metal; Region III – between the two gate contacts; Region IV – under the Gate 2 metal; Region
V – between Gate 2 contact edge and drain contact. The 2D potential variation ψi(x,y) in AlGaN region is obtained by considering
assumptions such as the uniform impurity concentration and that the regions are fully depleted and solving 2D-Poisson equation where
i ¼ 1, 2, ….,5 for corresponding regions. The following assumption has been considered for developing the analytical model:

(a) The analytical model has been derived by dividing the AlGaN/GaN heterostructure into series of five zones. The barrier layer is
assumed to be uniformly doped and for normal operating conditions, region under the gate is fully depleted. It is also assumed
that electric field in the GaN buffer is negligible.
(b) The internal electric field distribution (Einti) in various zones is depending on channel concentration (nsi) by using simple
polynomial function given by Refs. [30]:
σp qnsi
Einti ¼ (1)
ε1

where σp is the total charge concentration induced due to spontaneous and piezoelectric polarization.

(c) Channel concentration (nsi) is dependent on surface potential (φs) by non-linear expression [31]:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
nsi ¼ ½ A þ A2 ðB þ Cðφs þ Vgoi Þ D�2 (2)

where Vgoi ¼ VFi-VTH. For constants k1, k2 and k3 defined in Ref. [31], values of A, B, C and D are given as:

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P. Singh et al. Superlattices and Microstructures 144 (2020) 106574

Fig. 2. Flowchart for mathematical formulation of surface potential and electric field for Single Gate (SG) and Dual Gate (DG) AlGaN/
GaN MISHEMT.

ε1 k2 ε1 ðk1 ΔEcÞ ε1 d1 qσp

A¼ B¼ C¼ D¼
2ðε1 k3 þ qd1 Þ ε1 k3 þ qd1 ε1 k3 þ qd1 ε1 k3 þ qd1

(d) It is assumed that fringing field effects between the two gates (G1 and G2) is negligible.

Analytical model is compared with TCAD simulation results and to validate the simulation models, simulated drain characteristics
has been compared with experimental results performed by Liao et al., in 2014 [32]. The device structure consists of AlGaN barrier (18
nm), GaN buffer (0.8 μm) on silicon substrate. The gate length is 150 nm and source-to-drain distance is 1 μm. The choice of simulation
models has been validated by close proximity of simulated and experimental results [32] as shown in Fig. 1(b) and (c). Same models
were further used to validate the proposed analytical model with TCAD. Fig. 1(b) depicts the comparison ID-VGS plot at VDS ¼ 8V and
Fig. 1(c) shows the comparison of ID-VDS characteristics at VGS ¼ 0V and VGS ¼ 2V. Following assumptions have been used for TCAD
settings to compare the results in Fig. 1(b) and (c):

(a) It is assumed that acceptor trap level of 3 eV is present at GaN/silicon interface.

(b) An interface charge of 1.5 � 1013 cm 2 is assumed to be present at AlGaN/GaN heterostructure to match the 2DEG density in
channel as used in model.
(c) Models that are used for simulation setup include Shockley-Read-Hall model, high field mobility model, Fermi (to activate
Carrier-Fermi-statistics). Coefficients of Low-field-mobility-model ALBRCT has been calibrated to match the experiment results.

The flowchart for solving the analytical equations of single gate (SG) and dual gate (DG) AlGaN/GaN MISHEMTs is given in Fig. 2.
The equations are solved where N1: doping concentration of the AlGaN barrier layer; ε1: relative permittivity of the AlGaN barrier
layer; ψsi (x): surface potential; c1i(x)and c2i(x): arbitrary coefficients in respective five regions. Input parameters used to calibrate
model calculations data with the experimental data include k1, k2 and k3 constant parameters that have been calibrated to match

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P. Singh et al. Superlattices and Microstructures 144 (2020) 106574

Fig. 3. (a) Surface potential and (b) Electric field variation for different device geometry of MISHEMT i.e. Single Gate (SG) and Dual-Gate (DG)
AlGaN/GaN MISHEMTs with different gate lengths at VDS ¼ 5V (Line: Analytical; Symbols: Simulated).

Fig. 4. Variation of Surface potential for DG-MISHEMT (with LG ¼ 180 nm; HfO2 gate dielectric) (a) different drain bias at VGS ¼ 0Vand (b) different
gate bias at VDS ¼ 0V where screen gate G2 is grounded while bias is applied to control gate G1only and (c) different gate bias applied to both
control gate G1 and screen gate G2 (shorted together) at VDS ¼ 0V; (Line: Analytical; Symbols: Simulated).

Fig. 5. (a) Surface potential and Electric field variation with position along surface for DG AlGaN/GaN MISHEMT HfO2/Al2O3 (with gate length LG
¼ 180 nm) for different gate stack materials at VGS ¼ 2V and VDS ¼ 0V (Line: Analytical; Symbols: Simulated); Electric field contours for DG-
MISHEMT (with gate length LG ¼ 180 nm) with (b) Si3N4 (c) HfO2/Al2O3 gate stack at VGS ¼ -2V and VDS ¼ 0V.

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P. Singh et al. Superlattices and Microstructures 144 (2020) 106574

Fig. 6. Surface potential and Electric field variation with position along surface for (a) T ¼ 300K, and (b) T ¼ 500K at VGS ¼ 0V and VDS ¼ 0V.

Fig. 7. (a) Validation of simulation models with experimental results [33] for ID-VGS plot at VDS ¼ 15V for single gated (LGS ¼ 1 μm, LGD ¼ 2.85 μm
and Gate length, LG ¼ 150 nm) AlGaN/GaN HEMT (b) Comparison of ID-VDS plot at VGS ¼ 2V for single gated (SG-HEMT), single gated device with
gate dielectric (SG-MISHEMT) and dual gated MISHEMT (DG-MISHEMT) (LGS ¼ 1 μm, LGD ¼ 2.6 μm, LG ¼ 150 nm and Distance between the two
gates, LGG ¼ 100 nm); (c) Influence of GaN buffer trap energy level (ET) on OFF-current for DG-MISHEMT at VDS ¼ 15V.

electron sheet concentration used in the model with experimental results.

Lower surface potential is observed for DG-MISHEMTs due to presence of G2 which change the gate-to-drain lengths (LGD) as
compare to SG-MISHEMT as demonstrated in Fig. 3(a). Higher electric field near drain side (for LG ¼ 180 nm device) is seen in Fig. 3(b)
due to reduced LGD compared to device with LG ¼ 140 nm device (i.e. ~ doubles for LG ¼ 180 nm). Also influence of drain bias is
negligible on control gate G1 for DGMISHEMT for both the gate lengths. Calculated model values are validated and compared with
simulation results.
The impact of drain and gate bias on surface potential for different biasing on control gate G1 (screen gate G2 is grounded) is shown
in Fig. 4 (a)-(c). It is observed from Fig. 4(a) that minimum surface potential at gate edge of G1 doesn’t changes with VDS but surface
potential rises at gate edge of G2 near drain side (from 1.0V to 1.74V) i.e. with increase in VDS from 0V to 5V. Similarly, electric field
rises at gate edge of G2 near drain side and changes by nearly 10 times with applied VDS while it is almost constant between two gates.
This implies that impact of VDS is screened at control gate (G1) due to introduction of second gate (G2). The influence on surface
potential profile with negative bias on control gate G1, VGS ¼ 1V and VGS ¼ 2V, for zero drain bias is shown in Fig. 4(b). Surface
potential under G1 changes upto 1.17 V with negative bias of VGS ¼ 2V at G1 while there is gradual increase in potential from this
value to 0.85V as G2 is connected to source. Also, electric field doubles (nearly) between the two gates due to potential difference
between G1 and G2. Considering another case where both the gates are connected (i.e. same bias is applied at G1 and G2), center
potential and electric field between the two gates doesn’t changes much as shown on Fig. 4(c).
In our previous work [28], optimized DC performance of DG-MISHEMT (with HfO2/Al2O3 gate stack) has been reported. Threshold
voltage stability against interface charge variation has also been observed. Fig. 5(a) shows the comparison of modeling and TCAD
simulations results for DG-MISHEMT with HfO2/Al2O3 gate stack. Effective gate oxide thickness is computed by using toxeff ¼ tox1 þ
(εox1/εox2).tox2 expression for the gate stack. Fig. 5(b)–(c) shows electric field contours for DG-MISHEMT with different gate oxides
such as Si3N4 and HfO2/Al2O3 and it is observed that G1 gate edge (control gate) with HfO2/Al2O3 gate stack exhibits similar electric
field distribution as that of device with Si3N4 gate insulator but changes by 4.9% at gate edge of screen gate G2 near drain side. Also,
lower fringing field effect has been observed from DG-MISHEMT with high-K gate stack as compared Si3N4 based device. It is seen that
electric field termination on S/D regions for low-K dielectric weakens the coupling between gate and the channel. Also fringe field are
not seen in region between the two gates i.e. control gate G1 is screened by additional gate G2.

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P. Singh et al. Superlattices and Microstructures 144 (2020) 106574

Fig. 8. (a) Log ID-VGS plot and (b) Transconductance vs gate voltage at VDS ¼ 15V; (c) Drain Conductance plot at VGS ¼ 2V for different tem­
peratures (TCAD simulation results).

For switching power applications, temperature performance of the device is a critical parameter as this will also determine the
reliability of the device. The influence of temperature variation on surface potential and electric field for DG-MISHEMT (with gate
length LG ¼ 180 nm; HfO2 gate dielectric) has been studied in Fig. 6(a)-(b). The surface potential drops by 3.6% at gate edge G2 near
drain side with rise in temperature while corresponding electric field reduces by 4.6%. Reduced surface potential is due to lower
electron affinity and 2DEG concentration at higher temperature.

3. TCAD BASED INVESTIGATION

For further study, simulations have been performed after calibrating the results of single gate AlGaN/GaN HEMT (on SiC substrate)
with experimental results as shown in Fig. 7(a). Universal schottky model have been used to simulate the schottky junction and po­
larization parameter have been added to match the experimental drain current values. The simulated values of drain current for single
gated device matches well with the experimental results [33] in Fig. 7(a) and results in shift in threshold voltage as compared to
analytical results (i.e. 0.15 V to 6.2 V). Also it has been observed from Fig. 7(b) that for VGS ¼ 2V and VDS ¼ 5V, drain current
increases by 13.1% for Single Gate MISHEMT with addition of gate insulator (Si3N4) of 6 nm thickness due to the rise in pinch off
voltage [26]. Improvement of drain current (nearly 14.7%) has also been observed by amalgamating another gate i.e. DG-MISHEMT in
Fig. 7(b) as the gate-to-drain (LGD) distance is reduced due to insertion of second gate (with gate G2 shorted to source) as compared to
Single Gate HEMT. Input parameters used to calibrate TCAD data for Fig. 7(a) with the experimental results [33] include:

(a) Energy level of traps is assumed to be 0.6 eV for acceptor-like traps and 1.8eV for donor-like traps [34].
(b) It is assumed that acceptor trap level of 3 eV is present at AlN/SiC interface.
(c) Interface charge at AlGaN/GaN heterointerface is calibrated to be 1.54 � 1013 cm 2.

Fig. 7(c) shows the impact of buffer trap energy level on OFF-current of the device and it is seen that IOFF increases with reduced
trap energy level and thus ION/IOFF ratio degrades for DG-MISHEMT.
Influence of temperature on DC performance of DG-MISHEMT is shown in Fig. 8(a)–8(c). It is seen that IDS reduces from 2040 mA/
mm to 1370 mA/mm with rise in temperature from 300K to 423 K (@ VDS ¼ 15V and VGS ¼ 1V). While, the corresponding OFF-
current also increases from 2.51 � 10 6 mA/mm to 2.53 � 10 3 mA/mm @ VDS ¼ 15V and VGS ¼ 11V (plotted in Fig. 8(a)). The
degradation in drain current at higher temperature (for DG-MISHEMT) is due to the fact that conduction band offset, ΔEc, decreases
with increase in temperature from 300K to 423K. This results in reduced 2DEG confinement and hence lower sheet carrier concen­
tration at higher temperature. Also, trans-conductance i.e. gmpeak reduces (from 285 mS/mm to 198 mS/mm) by ~ 30% if temperature
rises from 300K to 423K as shown in Fig. 8(b). Also, at higher temperatures, mobility of 2DEG charge carriers reduces resulting in
degraded DC performance as given in Ref. [35]. These results are in consistent with previous results where increased temperature
results in reduced 2DEG concentration.
It has been observed from Fig. 8(a) that Zero Temperature Coefficient (ZTC) point or Temperature Compensation Point (TCP) of
drain current for DG-MISHEMT is 8.4V which implies that the gate voltage lower than ZTC results in higher drain current (i.e. IOFF)
with increase in temperature i.e. IDS has positive temperature coefficient while for bias voltages above this ZTC point, drain current
(IDS) possesses negative temperature coefficient. ZTC point for trans-conductance differs slightly from that for drain current i.e. 8.6 V.
This indicates that trans-conductance increases with temperature for gate voltages below this value while opposite trend is observed
for gate voltages above temperature compensation point as given in Fig. 8(b). Temperature variation influence on drain conductance is
seen in Fig. 8(c). Peak drain conductance reduces to half (from 305 mS/mm to 141 mS/mm) if temperature is increased from 300K to
423K. This may be due to screening of control gate G1 due the introduction of second gate G2 and thus impact of drain voltage on
resistance under gate G1 reduces [36] and also due to reduced charge carrier mobility [35].
Fig. 9(a) shows performance comparison of different cases of MISHEMT in terms of ION/IOFF ratio for five different cases i.e. (a) Case
I: Single Gate MISHEMT (b) Case II: DG-MISHEMT with control gate (G1) and screen gate (G2) connected together (c) Case III: G2 and
source electrode are shorted (d) Case IV: G1 act as floating gate while bias is applied at G2 (e) Case V: gate bias is applied at G1 while
G2 act as floating gate. It is observed that ION/IOFF ratio is highest ~109 at 300 K for DG-MISHEMT with LG ¼ 150 nm where both the

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P. Singh et al. Superlattices and Microstructures 144 (2020) 106574

Fig. 9. (a) Comparison of ION/IOFF ratio of DG-MISHEMT for different connections to control gate G1 and screen gate G2 (LG ¼ 150 nm) for IOFF at
VGS ¼ 11V and ION at VGS ¼ 1V for VDS ¼ 15V. Electron concentration contours for DG-MISHEMT with (b) case II: G1 and G2 are at same bias (c)
case III: G1 is biased and G2 is connected to source for VDS ¼ 15V and VGS ¼ 11V.

Fig. 10. (a) Comparison of ION/IOFF ratio for G1 and G2 shorted together with varying barrier thickness tbarrier for different temperature for ION at
VGS ¼ -1V, IOFF at VGS ¼ 11V at VDS ¼ 15V (b) Channel potential profiles with different barrier thickness for DG-MISHEMT for VDS ¼ 0V and VGS ¼
0V at 300K.

gates are shorted together (i.e. Case II) as compared to other cases. This is because of extended depletion region under gate 2 due to the
introduction of second gate (as both gates are at VGS ¼ 11V) and results in decreased electron concentration under gate 2 for case II as
compared to case III (as clearly visible from Fig. 9 (b) and (c)) which results in lower leakage current for the former case. However, the
performance in terms of ION/IOFF degrades nearly same with temperature for all the cases i.e. reduces by an order of 4 if temperature is
enhanced from 300K to 500K (as shown in Fig. 9(a)).
Influence of AlGaN barrier thickness variation on ION/IOFF ratio for different temperatures of DG-MISHEMT (with both the gate
shorted together) is shown in Fig. 10(a). It has been observed, that for DG-MISHEMT (barrier thickness, tbarrier ¼ 22 nm), ION/IOFF ratio
reduces from 109 to 106 if temperature is increased because of degraded 2DEG concentration at higher temperature. Also, it is seen that
IOFF enhances from 1.14 � 10 13 mA/mm to 2.83 � 10 10 mA/mm at 300K as barrier thickness varies from 18 nm to 30 nm due to
increase in channel potential minima (as shown in Fig. 10(b)) resulting in reduced surface potential. Although IOFF improves with
reduced barrier thickness but ION also degrades which may result in reduced power density of the device.
Another investigation of AlGaN/GaN MISHEMTs includes the switching characteristic for an inductive load. The three cases
considered for the study include case I, case II and case III (as discussed previously). The schematic diagram of the circuit used for
simulation is given in Fig. 11(a). The circuits (based on different devices) are switched with -8V/þ2V gate voltages VGS as V [1] and
duty cycle of the pulse is 30% while rise time and fall times are considered to be 1ns. The switching transients at 300K at the cor­
responding drain terminals, V [2], are given in Fig. 11(b). It is clearly evident that for case II, higher output has been achieved i.e. 9.2V

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P. Singh et al. Superlattices and Microstructures 144 (2020) 106574

Fig. 11. (a) Circuit diagram (b) Transient response for VGS and VDS for case I, case II and case III at 300K (c) Variation in VDS for varying barrier
thickness for case II at 300K.

Fig. 12. Comparison of transient behaviour for (a) case I (b) case II and (c) case III at T ¼ 300K and T ¼ 423K.

(when input is in OFF-state) which is 9% and 8% higher as compared to case I and case III respectively. Transient response at drain
terminal also varies with barrier thickness as shown in Fig. 11(c). For increased barrier thickness, IOFF increases (as discussed pre­
viously) results in reduced voltage at output terminal. It is also seen that for AlGaN barrier thickness of 20 nm, VDS reaches maximum of
10V.
Additionally, the impact of temperature on transient response for the three cases has been compared in Fig. 12 (a)-(c). Due to higher
ION/IOFF ratio for varying temperature (as seen in Fig. 9(a), the influence of temperature on VDS is least for case II as compared to case I
and case III as illustrated in Fig. 12 (a)–(c). It has also been seen that with increase in temperature, both OFF and ON state voltage has
been deteriorates due to the reduction in ION/IOFF ratio of the device (as discussed previously).

4. Conclusion

It is observed that IDS and gm peak reduces with increase in temperature due to reduced sheet carrier concentration. ION/IOFF ratio
has been obtained with TCAD simulations for DG-MISHEMT with various gate bias combinations and observed that this ratio degrades
at higher operating temperature. Mathematical expression has been derived to calculate potential and electric field of the Dual-Gate
MISHEMT structure with HfO2 gate dielectric. Developed analytical results have been verified with ATLAS TCAD simulation results. It
is observed that the computed value of threshold voltage is nearly same to that of results obtained using simulations. Also, performance
has been evaluated for DG-MISHEMT with HfO2/Al2O3 gate stack and computed results have been verified with TCAD simulation
results. It is seen that ION/IOFF ratio degrades with increased AlGaN barrier thickness if control gate G1 and screen gate G2 are con­
nected together. Transient performance for SG and DG (case II and case III) AlGaN/GaN MISHEMTs has been compared for inductance
load and it is observed that dual gate configuration with both gates shorted results in higher drain voltage swing as compared to other
cases for input OFF-state.

ACKNOWLEDGEMENT

This work was financially supported by the Ministry of Science and Technology, Department of Science and Technology (SR/WOS-
A/ET-143/2017), Government of India and one of the authors, Preeti Singh would like to acknowledge, Department of Electronic
Science, University of Delhi South Campus, New Delhi-110021.

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Appendix A. Supplementary data

Supplementary data to this article can be found online at https://doi.org/10.1016/j.spmi.2020.106574.

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